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// OpenSPARC T2 Processor File: dmu_ilu_iil_bufmgr.v
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module dmu_ilu_iil_bufmgr (
//synopsys sync_set_reset "rst_l"
// >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//---------------------------------------------------------------------
// Clock and Reset Signals
//---------------------------------------------------------------------
input clk; // input clock
input rst_l; // input reset
//---------------------------------------------------------------------
// IHB and IHB management interface
//---------------------------------------------------------------------
input [6:0] p2d_ihb_wptr; // gray-coded IHB write pointer
output [5:0] d2p_ihb_addr; // binary read pointer to IHB
//---------------------------------------------------------------------
// IIL internal interface
//---------------------------------------------------------------------
input ihb_rptr_inc; // advance d2p_ihb_addr, from *_xfrfsm.v
output ihb_empty; // to *_xfrfsm.v
//---------------------------------------------------------------------
//---------------------------------------------------------------------
output [6:0] ihb_rptr; // binary IHB read pointer
output [6:0] ihb_wptr; // binary IHB write pointer
// >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
// ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
reg [6:0] ihb_rptr; // binary IHB read pointer
// ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire [6:0] gray_ihb_wptr; // gray-coded IHB write pointer
// >>>>>>>>>>>>>>>>>>>>>>>>> Zero In Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
// 0in known_driven -var ihb_rptr_inc
// >>>>>>>>>>>>>>>>>>>>>>>>> Function Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<
// converts gray-coded to binary-coded
for (i=6; i>=0; i=i-1) begin
// >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<<
assign ihb_empty = (ihb_rptr == ihb_wptr);
assign ihb_wptr = gray2bin(gray_ihb_wptr);
assign d2p_ihb_addr = ihb_rptr[5:0];
else if(ihb_rptr_inc) begin
ihb_rptr <= ihb_rptr + 1'b1;
// ******************************** Instantiation ************************
// pcie_common_sync_flop #(7) sync_flop (
// .dout(gray_ihb_wptr));
cl_a1_clksyncff_4x sync_flop_6 ( .d(p2d_ihb_wptr[6]), .si(1'b0), .q( gray_ihb_wptr[6]), .so(),
.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
cl_a1_clksyncff_4x sync_flop_5 ( .d(p2d_ihb_wptr[5]), .si(1'b0), .q( gray_ihb_wptr[5]), .so(),
.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
cl_a1_clksyncff_4x sync_flop_4 ( .d(p2d_ihb_wptr[4]), .si(1'b0), .q( gray_ihb_wptr[4]), .so(),
.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
cl_a1_clksyncff_4x sync_flop_3 ( .d(p2d_ihb_wptr[3]), .si(1'b0), .q( gray_ihb_wptr[3]), .so(),
.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
cl_a1_clksyncff_4x sync_flop_2 ( .d(p2d_ihb_wptr[2]), .si(1'b0), .q( gray_ihb_wptr[2]), .so(),
.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
cl_a1_clksyncff_4x sync_flop_1 ( .d(p2d_ihb_wptr[1]), .si(1'b0), .q( gray_ihb_wptr[1]), .so(),
.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
cl_a1_clksyncff_4x sync_flop_0 ( .d(p2d_ihb_wptr[0]), .si(1'b0), .q( gray_ihb_wptr[0]), .so(),
.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
endmodule // dmu_ilu_iil_bufmgr