Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: lsu_ard_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module lsu_ard_dp ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | tcu_scan_en, | |
40 | spc_aclk, | |
41 | spc_bclk, | |
42 | scan_out, | |
43 | rngl_lsu_cdbus, | |
44 | tlu_rngf_cdbus, | |
45 | arc_retl_vld_2f, | |
46 | arc_retf_vld_2f, | |
47 | arc_sel_fast, | |
48 | lsu_asi_clken, | |
49 | ard_retl_ctl_1f, | |
50 | ard_retl_vld_1f, | |
51 | ard_retl_rd_1f, | |
52 | ard_retl_tid_1f, | |
53 | ard_retl_ack_1f, | |
54 | ard_retl_exc_1f, | |
55 | ard_retf_ctl_1f, | |
56 | ard_retf_vld_1f, | |
57 | ard_retf_rd_1f, | |
58 | ard_retf_tid_1f, | |
59 | ard_retf_ack_1f, | |
60 | ard_retf_exc_1f, | |
61 | ard_pid_data); | |
62 | wire stop; | |
63 | wire se; | |
64 | wire pce_ov; | |
65 | wire siclk; | |
66 | wire soclk; | |
67 | wire i_rngl_stg1_reg_scanin; | |
68 | wire i_rngl_stg1_reg_scanout; | |
69 | wire [64:0] ardl_retl_pkt_1f; | |
70 | wire i_rngl_stg2_reg_scanin; | |
71 | wire i_rngl_stg2_reg_scanout; | |
72 | wire [63:0] ardl_retl_pkt_2f; | |
73 | wire i_rngf_stg1_reg_scanin; | |
74 | wire i_rngf_stg1_reg_scanout; | |
75 | wire [64:0] ardl_retf_pkt_1f; | |
76 | wire i_rngf_stg2_reg_scanin; | |
77 | wire i_rngf_stg2_reg_scanout; | |
78 | wire [63:0] ardl_retf_pkt_2f; | |
79 | wire [63:0] ardl_pid_data; | |
80 | ||
81 | ||
82 | // globals | |
83 | input l2clk; | |
84 | input scan_in; | |
85 | input tcu_pce_ov; // scan signals | |
86 | input tcu_scan_en; | |
87 | input spc_aclk; | |
88 | input spc_bclk; | |
89 | output scan_out; | |
90 | ||
91 | ||
92 | input [64:0] rngl_lsu_cdbus; // 64:0, 65 bit control/data bus coming from the ring | |
93 | // 64 - ctl/data | |
94 | // 63 - valid/hole | |
95 | // 62 - ack | |
96 | // 61:60 - 00-ASI, 01-ASR, 10-PR, 11-HPR | |
97 | // 59 - rd/wrx | |
98 | // 58:56 - Thread ID | |
99 | // 55:48 - ASI field | |
100 | // 47:0 - Virtual Address | |
101 | ||
102 | input [64:0] tlu_rngf_cdbus; // 65 bit control/data bus from mmu (fast ring) | |
103 | ||
104 | ||
105 | input arc_retl_vld_2f; // valid data returned on the ring | |
106 | input arc_retf_vld_2f; // valid data returned on the ring | |
107 | ||
108 | input arc_sel_fast; // select fast ring data to be returned to pid | |
109 | ||
110 | input lsu_asi_clken; | |
111 | ||
112 | output ard_retl_ctl_1f; // Control/Data bit from returning ring | |
113 | output ard_retl_vld_1f; // Valid/hold bit on returning ring | |
114 | output ard_retl_rd_1f; // rd/wrx bit on returning ring | |
115 | output [2:0] ard_retl_tid_1f; // Thread id on returning ring | |
116 | output ard_retl_ack_1f; // Ack bit returning on ring | |
117 | output [1:0] ard_retl_exc_1f; // Exception status returning on ring | |
118 | ||
119 | output ard_retf_ctl_1f; // Control/Data bit from returning ring | |
120 | output ard_retf_vld_1f; // Valid/hold bit on returning ring | |
121 | output ard_retf_rd_1f; // rd/wrx bit on returning ring | |
122 | output [2:0] ard_retf_tid_1f; // Thread id on returning ring | |
123 | output ard_retf_ack_1f; // Ack bit returning on ring | |
124 | output [1:0] ard_retf_exc_1f; // Exception status returning on ring | |
125 | ||
126 | output [63:0] ard_pid_data; // 63:0 - data being returned to pid | |
127 | ||
128 | // scan renames | |
129 | assign stop = 1'b0; | |
130 | // end scan | |
131 | ||
132 | lsu_ard_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_4 test_rep0 ( | |
133 | .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}), | |
134 | .dout({se,pce_ov,siclk,soclk}) | |
135 | ); | |
136 | ||
137 | ||
138 | //////////////////////////////////////////////////////////////// | |
139 | //Return data coming over FAST and LOCAL RING | |
140 | //////////////////////////////////////////////////////////////// | |
141 | // | |
142 | //Latch Return packet coming from the ring | |
143 | // This comes over two cycles. Combine | |
144 | // into a single packet before returning to pid. | |
145 | // Data comes simultaneously over the local ring and fast ring, but | |
146 | // since it comes over 2 cycles and the data is returned to pid in | |
147 | // 1 cycle, we can sustain simultaneous pipelined transfers on local | |
148 | // and fast rings. | |
149 | // | |
150 | ||
151 | // Local ring | |
152 | lsu_ard_dp_msff_macro__stack_66c__width_65 i_rngl_stg1_reg | |
153 | ( | |
154 | .scan_in(i_rngl_stg1_reg_scanin), | |
155 | .scan_out(i_rngl_stg1_reg_scanout), | |
156 | .clk (l2clk), | |
157 | .en (lsu_asi_clken), | |
158 | .din (rngl_lsu_cdbus[64:0]), | |
159 | .dout(ardl_retl_pkt_1f[64:0]), | |
160 | .se(se), | |
161 | .siclk(siclk), | |
162 | .soclk(soclk), | |
163 | .pce_ov(pce_ov), | |
164 | .stop(stop) | |
165 | ); | |
166 | ||
167 | // control bits are sent to arc where they are staged for | |
168 | // two more cycles. | |
169 | assign ard_retl_ctl_1f = ardl_retl_pkt_1f[64]; | |
170 | assign ard_retl_vld_1f = ardl_retl_pkt_1f[63]; | |
171 | assign ard_retl_rd_1f = ardl_retl_pkt_1f[59]; | |
172 | assign ard_retl_tid_1f[2:0] = ardl_retl_pkt_1f[58:56]; | |
173 | assign ard_retl_ack_1f = ardl_retl_pkt_1f[62]; | |
174 | assign ard_retl_exc_1f[1:0] = ardl_retl_pkt_1f[49:48]; | |
175 | ||
176 | // Stage the data being sent to PID in the output register | |
177 | // This register is loaded only when valid control is | |
178 | // set in stage2. It implies that valid control came | |
179 | // in the previous cycle. This can happen at the most | |
180 | // every other cycle. | |
181 | lsu_ard_dp_msff_macro__stack_66c__width_64 i_rngl_stg2_reg | |
182 | ( | |
183 | .scan_in(i_rngl_stg2_reg_scanin), | |
184 | .scan_out(i_rngl_stg2_reg_scanout), | |
185 | .clk (l2clk), | |
186 | .en (arc_retl_vld_2f), | |
187 | .din(ardl_retl_pkt_1f[63:0]), | |
188 | .dout(ardl_retl_pkt_2f[63:0]), | |
189 | .se(se), | |
190 | .siclk(siclk), | |
191 | .soclk(soclk), | |
192 | .pce_ov(pce_ov), | |
193 | .stop(stop) | |
194 | ); | |
195 | ||
196 | // Fast ring | |
197 | lsu_ard_dp_msff_macro__stack_66c__width_65 i_rngf_stg1_reg | |
198 | ( | |
199 | .scan_in(i_rngf_stg1_reg_scanin), | |
200 | .scan_out(i_rngf_stg1_reg_scanout), | |
201 | .clk (l2clk), | |
202 | .en (lsu_asi_clken), | |
203 | .din (tlu_rngf_cdbus[64:0]), | |
204 | .dout(ardl_retf_pkt_1f[64:0]), | |
205 | .se(se), | |
206 | .siclk(siclk), | |
207 | .soclk(soclk), | |
208 | .pce_ov(pce_ov), | |
209 | .stop(stop) | |
210 | ); | |
211 | ||
212 | // control bits are sent to arc where they are staged for | |
213 | // two more cycles. | |
214 | assign ard_retf_ctl_1f = ardl_retf_pkt_1f[64]; | |
215 | assign ard_retf_vld_1f = ardl_retf_pkt_1f[63]; | |
216 | assign ard_retf_rd_1f = ardl_retf_pkt_1f[59]; | |
217 | assign ard_retf_tid_1f[2:0] = ardl_retf_pkt_1f[58:56]; | |
218 | assign ard_retf_ack_1f = ardl_retf_pkt_1f[62]; | |
219 | assign ard_retf_exc_1f[1:0] = ardl_retf_pkt_1f[49:48]; | |
220 | ||
221 | // Stage the data being sent to PID in the output register | |
222 | // This register is loaded only when valid control is | |
223 | // set in stage2. It implies that valid control came | |
224 | // in the previous cycle. This can happen at the most | |
225 | // every other cycle. | |
226 | lsu_ard_dp_msff_macro__stack_66c__width_64 i_rngf_stg2_reg | |
227 | ( | |
228 | .scan_in(i_rngf_stg2_reg_scanin), | |
229 | .scan_out(i_rngf_stg2_reg_scanout), | |
230 | .clk (l2clk), | |
231 | .en (arc_retf_vld_2f), | |
232 | .din(ardl_retf_pkt_1f[63:0]), | |
233 | .dout(ardl_retf_pkt_2f[63:0]), | |
234 | .se(se), | |
235 | .siclk(siclk), | |
236 | .soclk(soclk), | |
237 | .pce_ov(pce_ov), | |
238 | .stop(stop) | |
239 | ); | |
240 | ||
241 | ||
242 | // Data being sent to PID aligns with the control being sent | |
243 | // over arc_pid_ctl[6:0] from arc. Mux between the Fast Output | |
244 | // register and the Local Output register. | |
245 | lsu_ard_dp_mux_macro__mux_aope__ports_2__stack_66c__width_64 i_ret_pkt_mux | |
246 | ( | |
247 | .din0( ardl_retf_pkt_2f[63:0]), | |
248 | .din1( ardl_retl_pkt_2f[63:0]), | |
249 | .sel0( arc_sel_fast), | |
250 | .dout( ardl_pid_data[63:0]) | |
251 | ); | |
252 | ||
253 | lsu_ard_dp_buff_macro__dbuff_32x__stack_66c__width_64 pid_data_buf ( | |
254 | .din (ardl_pid_data[63:0]), | |
255 | .dout(ard_pid_data[63:0]) | |
256 | ); | |
257 | ||
258 | // fixscan start: | |
259 | assign i_rngl_stg1_reg_scanin = scan_in ; | |
260 | assign i_rngl_stg2_reg_scanin = i_rngl_stg1_reg_scanout ; | |
261 | assign i_rngf_stg1_reg_scanin = i_rngl_stg2_reg_scanout ; | |
262 | assign i_rngf_stg2_reg_scanin = i_rngf_stg1_reg_scanout ; | |
263 | assign scan_out = i_rngf_stg2_reg_scanout ; | |
264 | // fixscan end: | |
265 | endmodule | |
266 | ||
267 | ||
268 | ||
269 | // | |
270 | // buff macro | |
271 | // | |
272 | // | |
273 | ||
274 | ||
275 | ||
276 | ||
277 | ||
278 | module lsu_ard_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_4 ( | |
279 | din, | |
280 | dout); | |
281 | input [3:0] din; | |
282 | output [3:0] dout; | |
283 | ||
284 | ||
285 | ||
286 | ||
287 | ||
288 | ||
289 | buff #(4) d0_0 ( | |
290 | .in(din[3:0]), | |
291 | .out(dout[3:0]) | |
292 | ); | |
293 | ||
294 | ||
295 | ||
296 | ||
297 | ||
298 | ||
299 | ||
300 | ||
301 | endmodule | |
302 | ||
303 | ||
304 | ||
305 | ||
306 | ||
307 | ||
308 | ||
309 | ||
310 | ||
311 | // any PARAMS parms go into naming of macro | |
312 | ||
313 | module lsu_ard_dp_msff_macro__stack_66c__width_65 ( | |
314 | din, | |
315 | clk, | |
316 | en, | |
317 | se, | |
318 | scan_in, | |
319 | siclk, | |
320 | soclk, | |
321 | pce_ov, | |
322 | stop, | |
323 | dout, | |
324 | scan_out); | |
325 | wire l1clk; | |
326 | wire siclk_out; | |
327 | wire soclk_out; | |
328 | wire [63:0] so; | |
329 | ||
330 | input [64:0] din; | |
331 | ||
332 | ||
333 | input clk; | |
334 | input en; | |
335 | input se; | |
336 | input scan_in; | |
337 | input siclk; | |
338 | input soclk; | |
339 | input pce_ov; | |
340 | input stop; | |
341 | ||
342 | ||
343 | ||
344 | output [64:0] dout; | |
345 | ||
346 | ||
347 | output scan_out; | |
348 | ||
349 | ||
350 | ||
351 | ||
352 | cl_dp1_l1hdr_8x c0_0 ( | |
353 | .l2clk(clk), | |
354 | .pce(en), | |
355 | .aclk(siclk), | |
356 | .bclk(soclk), | |
357 | .l1clk(l1clk), | |
358 | .se(se), | |
359 | .pce_ov(pce_ov), | |
360 | .stop(stop), | |
361 | .siclk_out(siclk_out), | |
362 | .soclk_out(soclk_out) | |
363 | ); | |
364 | dff #(65) d0_0 ( | |
365 | .l1clk(l1clk), | |
366 | .siclk(siclk_out), | |
367 | .soclk(soclk_out), | |
368 | .d(din[64:0]), | |
369 | .si({scan_in,so[63:0]}), | |
370 | .so({so[63:0],scan_out}), | |
371 | .q(dout[64:0]) | |
372 | ); | |
373 | ||
374 | ||
375 | ||
376 | ||
377 | ||
378 | ||
379 | ||
380 | ||
381 | ||
382 | ||
383 | ||
384 | ||
385 | ||
386 | ||
387 | ||
388 | ||
389 | ||
390 | ||
391 | ||
392 | ||
393 | endmodule | |
394 | ||
395 | ||
396 | ||
397 | ||
398 | ||
399 | ||
400 | ||
401 | ||
402 | ||
403 | ||
404 | ||
405 | ||
406 | ||
407 | // any PARAMS parms go into naming of macro | |
408 | ||
409 | module lsu_ard_dp_msff_macro__stack_66c__width_64 ( | |
410 | din, | |
411 | clk, | |
412 | en, | |
413 | se, | |
414 | scan_in, | |
415 | siclk, | |
416 | soclk, | |
417 | pce_ov, | |
418 | stop, | |
419 | dout, | |
420 | scan_out); | |
421 | wire l1clk; | |
422 | wire siclk_out; | |
423 | wire soclk_out; | |
424 | wire [62:0] so; | |
425 | ||
426 | input [63:0] din; | |
427 | ||
428 | ||
429 | input clk; | |
430 | input en; | |
431 | input se; | |
432 | input scan_in; | |
433 | input siclk; | |
434 | input soclk; | |
435 | input pce_ov; | |
436 | input stop; | |
437 | ||
438 | ||
439 | ||
440 | output [63:0] dout; | |
441 | ||
442 | ||
443 | output scan_out; | |
444 | ||
445 | ||
446 | ||
447 | ||
448 | cl_dp1_l1hdr_8x c0_0 ( | |
449 | .l2clk(clk), | |
450 | .pce(en), | |
451 | .aclk(siclk), | |
452 | .bclk(soclk), | |
453 | .l1clk(l1clk), | |
454 | .se(se), | |
455 | .pce_ov(pce_ov), | |
456 | .stop(stop), | |
457 | .siclk_out(siclk_out), | |
458 | .soclk_out(soclk_out) | |
459 | ); | |
460 | dff #(64) d0_0 ( | |
461 | .l1clk(l1clk), | |
462 | .siclk(siclk_out), | |
463 | .soclk(soclk_out), | |
464 | .d(din[63:0]), | |
465 | .si({scan_in,so[62:0]}), | |
466 | .so({so[62:0],scan_out}), | |
467 | .q(dout[63:0]) | |
468 | ); | |
469 | ||
470 | ||
471 | ||
472 | ||
473 | ||
474 | ||
475 | ||
476 | ||
477 | ||
478 | ||
479 | ||
480 | ||
481 | ||
482 | ||
483 | ||
484 | ||
485 | ||
486 | ||
487 | ||
488 | ||
489 | endmodule | |
490 | ||
491 | ||
492 | ||
493 | ||
494 | ||
495 | ||
496 | ||
497 | ||
498 | ||
499 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
500 | // also for pass-gate with decoder | |
501 | ||
502 | ||
503 | ||
504 | ||
505 | ||
506 | // any PARAMS parms go into naming of macro | |
507 | ||
508 | module lsu_ard_dp_mux_macro__mux_aope__ports_2__stack_66c__width_64 ( | |
509 | din0, | |
510 | din1, | |
511 | sel0, | |
512 | dout); | |
513 | wire psel0; | |
514 | wire psel1; | |
515 | ||
516 | input [63:0] din0; | |
517 | input [63:0] din1; | |
518 | input sel0; | |
519 | output [63:0] dout; | |
520 | ||
521 | ||
522 | ||
523 | ||
524 | ||
525 | cl_dp1_penc2_8x c0_0 ( | |
526 | .sel0(sel0), | |
527 | .psel0(psel0), | |
528 | .psel1(psel1) | |
529 | ); | |
530 | ||
531 | mux2s #(64) d0_0 ( | |
532 | .sel0(psel0), | |
533 | .sel1(psel1), | |
534 | .in0(din0[63:0]), | |
535 | .in1(din1[63:0]), | |
536 | .dout(dout[63:0]) | |
537 | ); | |
538 | ||
539 | ||
540 | ||
541 | ||
542 | ||
543 | ||
544 | ||
545 | ||
546 | ||
547 | ||
548 | ||
549 | ||
550 | ||
551 | endmodule | |
552 | ||
553 | ||
554 | // | |
555 | // buff macro | |
556 | // | |
557 | // | |
558 | ||
559 | ||
560 | ||
561 | ||
562 | ||
563 | module lsu_ard_dp_buff_macro__dbuff_32x__stack_66c__width_64 ( | |
564 | din, | |
565 | dout); | |
566 | input [63:0] din; | |
567 | output [63:0] dout; | |
568 | ||
569 | ||
570 | ||
571 | ||
572 | ||
573 | ||
574 | buff #(64) d0_0 ( | |
575 | .in(din[63:0]), | |
576 | .out(dout[63:0]) | |
577 | ); | |
578 | ||
579 | ||
580 | ||
581 | ||
582 | ||
583 | ||
584 | ||
585 | ||
586 | endmodule | |
587 | ||
588 | ||
589 | ||
590 |