// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: lsu_ard_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// ========== Copyright Header End ============================================
wire i_rngl_stg1_reg_scanin;
wire i_rngl_stg1_reg_scanout;
wire [64:0] ardl_retl_pkt_1f;
wire i_rngl_stg2_reg_scanin;
wire i_rngl_stg2_reg_scanout;
wire [63:0] ardl_retl_pkt_2f;
wire i_rngf_stg1_reg_scanin;
wire i_rngf_stg1_reg_scanout;
wire [64:0] ardl_retf_pkt_1f;
wire i_rngf_stg2_reg_scanin;
wire i_rngf_stg2_reg_scanout;
wire [63:0] ardl_retf_pkt_2f;
wire [63:0] ardl_pid_data;
input tcu_pce_ov; // scan signals
input [64:0] rngl_lsu_cdbus; // 64:0, 65 bit control/data bus coming from the ring
// 61:60 - 00-ASI, 01-ASR, 10-PR, 11-HPR
// 47:0 - Virtual Address
input [64:0] tlu_rngf_cdbus; // 65 bit control/data bus from mmu (fast ring)
input arc_retl_vld_2f; // valid data returned on the ring
input arc_retf_vld_2f; // valid data returned on the ring
input arc_sel_fast; // select fast ring data to be returned to pid
output ard_retl_ctl_1f; // Control/Data bit from returning ring
output ard_retl_vld_1f; // Valid/hold bit on returning ring
output ard_retl_rd_1f; // rd/wrx bit on returning ring
output [2:0] ard_retl_tid_1f; // Thread id on returning ring
output ard_retl_ack_1f; // Ack bit returning on ring
output [1:0] ard_retl_exc_1f; // Exception status returning on ring
output ard_retf_ctl_1f; // Control/Data bit from returning ring
output ard_retf_vld_1f; // Valid/hold bit on returning ring
output ard_retf_rd_1f; // rd/wrx bit on returning ring
output [2:0] ard_retf_tid_1f; // Thread id on returning ring
output ard_retf_ack_1f; // Ack bit returning on ring
output [1:0] ard_retf_exc_1f; // Exception status returning on ring
output [63:0] ard_pid_data; // 63:0 - data being returned to pid
lsu_ard_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_4 test_rep0 (
.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
.dout({se,pce_ov,siclk,soclk})
////////////////////////////////////////////////////////////////
//Return data coming over FAST and LOCAL RING
////////////////////////////////////////////////////////////////
//Latch Return packet coming from the ring
// This comes over two cycles. Combine
// into a single packet before returning to pid.
// Data comes simultaneously over the local ring and fast ring, but
// since it comes over 2 cycles and the data is returned to pid in
// 1 cycle, we can sustain simultaneous pipelined transfers on local
lsu_ard_dp_msff_macro__stack_66c__width_65 i_rngl_stg1_reg
.scan_in(i_rngl_stg1_reg_scanin),
.scan_out(i_rngl_stg1_reg_scanout),
.din (rngl_lsu_cdbus[64:0]),
.dout(ardl_retl_pkt_1f[64:0]),
// control bits are sent to arc where they are staged for
assign ard_retl_ctl_1f = ardl_retl_pkt_1f[64];
assign ard_retl_vld_1f = ardl_retl_pkt_1f[63];
assign ard_retl_rd_1f = ardl_retl_pkt_1f[59];
assign ard_retl_tid_1f[2:0] = ardl_retl_pkt_1f[58:56];
assign ard_retl_ack_1f = ardl_retl_pkt_1f[62];
assign ard_retl_exc_1f[1:0] = ardl_retl_pkt_1f[49:48];
// Stage the data being sent to PID in the output register
// This register is loaded only when valid control is
// set in stage2. It implies that valid control came
// in the previous cycle. This can happen at the most
lsu_ard_dp_msff_macro__stack_66c__width_64 i_rngl_stg2_reg
.scan_in(i_rngl_stg2_reg_scanin),
.scan_out(i_rngl_stg2_reg_scanout),
.din(ardl_retl_pkt_1f[63:0]),
.dout(ardl_retl_pkt_2f[63:0]),
lsu_ard_dp_msff_macro__stack_66c__width_65 i_rngf_stg1_reg
.scan_in(i_rngf_stg1_reg_scanin),
.scan_out(i_rngf_stg1_reg_scanout),
.din (tlu_rngf_cdbus[64:0]),
.dout(ardl_retf_pkt_1f[64:0]),
// control bits are sent to arc where they are staged for
assign ard_retf_ctl_1f = ardl_retf_pkt_1f[64];
assign ard_retf_vld_1f = ardl_retf_pkt_1f[63];
assign ard_retf_rd_1f = ardl_retf_pkt_1f[59];
assign ard_retf_tid_1f[2:0] = ardl_retf_pkt_1f[58:56];
assign ard_retf_ack_1f = ardl_retf_pkt_1f[62];
assign ard_retf_exc_1f[1:0] = ardl_retf_pkt_1f[49:48];
// Stage the data being sent to PID in the output register
// This register is loaded only when valid control is
// set in stage2. It implies that valid control came
// in the previous cycle. This can happen at the most
lsu_ard_dp_msff_macro__stack_66c__width_64 i_rngf_stg2_reg
.scan_in(i_rngf_stg2_reg_scanin),
.scan_out(i_rngf_stg2_reg_scanout),
.din(ardl_retf_pkt_1f[63:0]),
.dout(ardl_retf_pkt_2f[63:0]),
// Data being sent to PID aligns with the control being sent
// over arc_pid_ctl[6:0] from arc. Mux between the Fast Output
// register and the Local Output register.
lsu_ard_dp_mux_macro__mux_aope__ports_2__stack_66c__width_64 i_ret_pkt_mux
.din0( ardl_retf_pkt_2f[63:0]),
.din1( ardl_retl_pkt_2f[63:0]),
.dout( ardl_pid_data[63:0])
lsu_ard_dp_buff_macro__dbuff_32x__stack_66c__width_64 pid_data_buf (
.din (ardl_pid_data[63:0]),
.dout(ard_pid_data[63:0])
assign i_rngl_stg1_reg_scanin = scan_in ;
assign i_rngl_stg2_reg_scanin = i_rngl_stg1_reg_scanout ;
assign i_rngf_stg1_reg_scanin = i_rngl_stg2_reg_scanout ;
assign i_rngf_stg2_reg_scanin = i_rngf_stg1_reg_scanout ;
assign scan_out = i_rngf_stg2_reg_scanout ;
module lsu_ard_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_4 (
// any PARAMS parms go into naming of macro
module lsu_ard_dp_msff_macro__stack_66c__width_65 (
.so({so[63:0],scan_out}),
// any PARAMS parms go into naming of macro
module lsu_ard_dp_msff_macro__stack_66c__width_64 (
.so({so[62:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_ard_dp_mux_macro__mux_aope__ports_2__stack_66c__width_64 (
module lsu_ard_dp_buff_macro__dbuff_32x__stack_66c__width_64 (