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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / libs / analog / n2_rng_cust_l / n2_rng_cust / rtl / n2_rng_cust.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: n2_rng_cust.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module n2_rng_cust(vreg_selbg_l ,rng_arst_l ,ch_sel ,anlg_sel ,
36 vcoctrl_sel ,vdd_hv15 ,soclk ,si ,anlg_char_out ,bypass ,
37 tcu_se_scancollar_out ,so ,stop ,l2clk ,siclk ,rng_data );
38input [1:0] ch_sel ;
39input [1:0] anlg_sel ;
40input [1:0] vcoctrl_sel ;
41output anlg_char_out ;
42output so ;
43output rng_data ;
44input vreg_selbg_l ;
45input rng_arst_l ;
46input vdd_hv15 ;
47input soclk ;
48input si ;
49input bypass ;
50input tcu_se_scancollar_out ;
51input stop ;
52input l2clk ;
53input siclk ;
54supply1 vdd ;
55supply0 vss ;
56
57wire [3:0] vcoctrl_sel2 ;
58wire [3:0] vcoctrl_sel1 ;
59wire [2:0] raw_data ;
60wire [1:0] amux_sel1 ;
61wire [1:0] amux_sel0 ;
62wire [3:0] vcoctrl_sel0 ;
63wire [1:0] amux_sel2 ;
64wire net102 ;
65wire net103 ;
66wire vbn ;
67wire net093 ;
68wire v300m ;
69wire fast_vco ;
70wire i50n4_lowv ;
71wire i50n6_lowv ;
72wire i50n8_lowv ;
73wire vdd_reg ;
74wire i50n0_lowv ;
75wire i50n2_lowv ;
76wire net95 ;
77wire virt_vss ;
78wire v400m ;
79wire net055 ;
80wire v500m ;
81wire net0117 ;
82wire net0118 ;
83wire i50n3_lowv ;
84wire i50n5_lowv ;
85wire i50n7_lowv ;
86wire i50n9_lowv ;
87wire amux_off ;
88wire i50n1_lowv ;
89
90
91//n2_vreg_cust x3 (
92// .i50n ({i50n9_lowv ,i50n8_lowv ,i50n7_lowv ,i50n6_lowv ,
93// i50n5_lowv ,i50n4_lowv ,i50n3_lowv ,i50n2_lowv ,i50n1_lowv ,
94// i50n0_lowv } ),
95// .v1p1reg_lowv (vdd_reg ),
96// .vdd_hv15 (vdd_hv15 ),
97// .vref (net0118 ),
98// .vrefb (net0117 ),
99// .selbg_l (vreg_selbg_l ) );
100//n2_esd_vddo x4 (
101// .vdd_esd (vdd ),
102// .vddo_esd (vdd_hv15 ) );
103//terminator i21 (
104// .TERM (net093 ) );
105//n2_esd_sig_3diode x10 (
106// .sig (anlg_char_out ) );
107//terminator i30 (
108// .TERM (net102 ) );
109//terminator i31 (
110// .TERM (net055 ) );
111//terminator i35 (
112// .TERM (v500m ) );
113//n2_rng_rc_filter_cust x98 (
114// .vdd_reg (vdd_reg ),
115// .rc_fltr_out (virt_vss ),
116// .rc_fltr_in (v300m ),
117// .vbn (vbn ) );
118//terminator i36 (
119// .TERM (v400m ) );
120//n2_rng_resarray_cust x24 (
121// .r ({net95 ,net093 ,v300m ,v400m ,v500m ,net055 ,vbn
122// ,net102 ,net103 } ),
123// .vm (vss ),
124// .vp (vdd_reg ) );
125//terminator i45 (
126// .TERM (fast_vco ) );
127//terminator iia (
128// .TERM (net0118 ) );
129//terminator ib (
130// .TERM (net0117 ) );
131n2_rng_sampler_cust xs (
132 .anlg_sel ({anlg_sel } ),
133 .vcoctrl_sel ({vcoctrl_sel } ),
134 .ch_sel ({ch_sel } ),
135 .vcoctrl_sel2 ({vcoctrl_sel2 } ),
136 .amux_sel0 ({amux_sel0 } ),
137 .amux_sel1 ({amux_sel1 } ),
138 .amux_sel2 ({amux_sel2 } ),
139 .vcoctrl_sel0 ({vcoctrl_sel0 } ),
140 .vcoctrl_sel1 ({vcoctrl_sel1 } ),
141 .raw_data ({raw_data } ),
142 .arst_l (rng_arst_l ),
143 .amux_off (amux_off ),
144 .fast_vco (fast_vco ),
145 .si (si ),
146 .so (so ),
147 .rng_data (rng_data ),
148 .se (tcu_se_scancollar_out ),
149 .l2clk (l2clk ),
150 .stop (stop ),
151 .siclk (siclk ),
152 .soclk (soclk ) );
153//terminator ia_0_ (
154// .TERM (i50n6_lowv ) );
155//n2_rng_channel_cust xx1_0_ (
156// .vcoctrl_sel ({vcoctrl_sel0 } ),
157// .amux_sel ({amux_sel0 } ),
158// .inb40u (i50n3_lowv ),
159// .ina40u (i50n0_lowv ),
160// .bypass (bypass ),
161// .vbn (vbn ),
162// .virt_vss (virt_vss ),
163// .vdd_hv15 (vdd_hv15 ),
164// .anlg_char_out (anlg_char_out ),
165// .ch_out (raw_data[0] ),
166// .vdd_reg (vdd_reg ),
167// .arst_l (rng_arst_l ),
168// .l2clk (vss ),
169// .fast_vco (vdd_reg ) );
170//pfet_thox m1 (
171// .B (vdd_reg ),
172// .G (vss ),
173// .D (vdd_reg ),
174// .S (vdd_reg ) );
175//pfet_thox m2 (
176// .B (vdd ),
177// .G (vss ),
178// .D (vdd ),
179// .S (vdd ) );
180//terminator ia_1_ (
181// .TERM (i50n7_lowv ) );
182//n2_rng_channel_cust xx1_1_ (
183// .vcoctrl_sel ({vcoctrl_sel1 } ),
184// .amux_sel ({amux_sel1 } ),
185// .inb40u (i50n4_lowv ),
186// .ina40u (i50n1_lowv ),
187// .bypass (bypass ),
188// .vbn (vbn ),
189// .virt_vss (virt_vss ),
190// .vdd_hv15 (vdd_hv15 ),
191// .anlg_char_out (anlg_char_out ),
192// .ch_out (raw_data[1] ),
193// .vdd_reg (vdd_reg ),
194// .arst_l (rng_arst_l ),
195// .l2clk (vss ),
196// .fast_vco (vdd_reg ) );
197//terminator ia_2_ (
198// .TERM (i50n8_lowv ) );
199//n2_rng_channel_cust xx1_2_ (
200// .vcoctrl_sel ({vcoctrl_sel2 } ),
201// .amux_sel ({amux_sel2 } ),
202// .inb40u (i50n5_lowv ),
203// .ina40u (i50n2_lowv ),
204// .bypass (bypass ),
205// .vbn (vbn ),
206// .virt_vss (virt_vss ),
207// .vdd_hv15 (vdd_hv15 ),
208// .anlg_char_out (anlg_char_out ),
209// .ch_out (raw_data[2] ),
210// .vdd_reg (vdd_reg ),
211// .arst_l (rng_arst_l ),
212// .l2clk (vss ),
213// .fast_vco (vdd_reg ) );
214//terminator ix5 (
215// .TERM (net103 ) );
216//terminator ia_3_ (
217// .TERM (i50n9_lowv ) );
218//terminator ix6 (
219// .TERM (net95 ) );
220//n2_rng_hvamux_cust x0 (
221// .vdd_hv15 (vdd_hv15 ),
222// .amux_sel (amux_off ),
223// .in_lowv (vss ),
224// .out (anlg_char_out ) );
225
226//===== following code added for testbench (7/26/06) =====
227
228reg [2:0] noise_cells;
229integer seed;
230
231initial begin
232 seed = 1;
233 if (!($test$plusargs("disable_rng_noisecell"))) begin
234 force raw_data = noise_cells;
235 while (1) begin
236 @(posedge l2clk or negedge rng_arst_l);
237 if (!rng_arst_l)
238 noise_cells <= 3'b000;
239 else
240 noise_cells <= $random (seed);
241 end
242 end
243end
244
245endmodule
246
247
248//
249// N2_RNG_SAMPLER_CUST - vgate file generated by KC
250//
251module n2_rng_sampler_cust(arst_l ,anlg_sel ,vcoctrl_sel ,ch_sel ,
252 vcoctrl_sel2 ,amux_off ,amux_sel0 ,amux_sel1 ,amux_sel2 ,
253 vcoctrl_sel0 ,vcoctrl_sel1 ,fast_vco ,si ,so ,rng_data ,raw_data ,
254 se ,l2clk ,stop ,siclk ,soclk );
255output [3:0] vcoctrl_sel2 ;
256output [1:0] amux_sel0 ;
257output [1:0] amux_sel1 ;
258output [1:0] amux_sel2 ;
259output [3:0] vcoctrl_sel0 ;
260output [3:0] vcoctrl_sel1 ;
261input [1:0] anlg_sel ;
262input [1:0] vcoctrl_sel ;
263input [1:0] ch_sel ;
264input [2:0] raw_data ;
265output amux_off ;
266output fast_vco ;
267output so ;
268output rng_data ;
269input arst_l ;
270input si ;
271input se ;
272input l2clk ;
273input stop ;
274input siclk ;
275input soclk ;
276
277wire [2:0] ctrl ;
278
279
280n2_rng_reg_cust x3 (
281 .ctrl ({ctrl } ),
282 .amux_sel1 ({amux_sel1 } ),
283 .amux_sel0 ({amux_sel0 } ),
284 .amux_sel2 ({amux_sel2 } ),
285 .anlg_sel ({anlg_sel } ),
286 .vcoctrl_sel ({vcoctrl_sel } ),
287 .ch_sel ({ch_sel } ),
288 .vcoctrl_sel0 ({vcoctrl_sel0 } ),
289 .vcoctrl_sel1 ({vcoctrl_sel1 } ),
290 .vcoctrl_sel2 ({vcoctrl_sel2 } ),
291 .fast_vco (fast_vco ),
292 .amux_off (amux_off ),
293 .l2clk (l2clk ),
294 .stop (stop ),
295 .arst_l (arst_l ) );
296n2_rng_sync_cust x0 (
297 .ctrl ({ctrl } ),
298 .raw_data ({raw_data } ),
299 .si (si ),
300 .so (so ),
301 .rng_data (rng_data ),
302 .se (se ),
303 .l2clk (l2clk ),
304 .stop (stop ),
305 .siclk (siclk ),
306 .soclk (soclk ) );
307endmodule
308
309
310//
311// N2_RNG_SYNC_CUST - vgate file generated by KC
312//
313module n2_rng_sync_cust(ctrl ,si ,so ,rng_data ,raw_data ,se ,l2clk ,
314 stop ,siclk ,soclk );
315input [2:0] ctrl ;
316input [2:0] raw_data ;
317output so ;
318output rng_data ;
319input si ;
320input se ;
321input l2clk ;
322input stop ;
323input siclk ;
324input soclk ;
325supply1 vdd ;
326supply0 vss ;
327
328wire [3:0] qb2 ;
329wire [3:0] so0 ;
330wire [2:0] data ;
331wire [3:0] so1 ;
332wire [3:0] net143 ;
333wire [3:0] q1 ;
334wire [3:0] q0 ;
335wire [2:0] so2 ;
336wire [3:0] qb0 ;
337wire [3:0] net141 ;
338wire [3:0] net145 ;
339wire [3:0] q2 ;
340wire [3:0] qb1 ;
341wire net190 ;
342wire net192 ;
343wire net193 ;
344wire net129 ;
345wire sob ;
346wire sof ;
347wire net154 ;
348wire net057 ;
349wire l2clk_v1 ;
350wire net068 ;
351wire net081 ;
352
353assign so=sob;
354assign rng_data=net193;
355
356cl_u1_buf_4x x2 (
357 .out (l2clk_v1 ),
358 .in (l2clk ) );
359cl_u1_inv_1x x5_1_ (
360 .out (net141[2] ),
361 .in (q2[1] ) );
362cl_u1_inv_2x x4_3_ (
363 .out (qb1[3] ),
364 .in (net143[0] ) );
365cl_u1_inv_1x x8_3_ (
366 .out (net145[0] ),
367 .in (q0[3] ) );
368cl_sc1_msff_4x x9 (
369 .q (net193 ),
370 .so (sof ),
371 .soclk (net192 ),
372 .siclk (net190 ),
373 .si (si ),
374 .l1clk (net154 ),
375 .d (net068 ) );
376cl_sc1_msff_4x xa0_0_ (
377 .q (q0[0] ),
378 .so (so0[0] ),
379 .soclk (net192 ),
380 .siclk (net190 ),
381 .si (sof ),
382 .l1clk (net154 ),
383 .d (data[0] ) );
384cl_u1_inv_1x x5_2_ (
385 .out (net141[1] ),
386 .in (q2[2] ) );
387cl_u1_inv_2x x6_0_ (
388 .out (qb2[0] ),
389 .in (net141[3] ) );
390cl_u1_inv_4x x10 (
391 .out (net068 ),
392 .in (net129 ) );
393cl_sc1_msff_4x xa0_1_ (
394 .q (q0[1] ),
395 .so (so0[1] ),
396 .soclk (net192 ),
397 .siclk (net190 ),
398 .si (so0[0] ),
399 .l1clk (net154 ),
400 .d (qb0[0] ) );
401cl_u1_xnor3_1x x14 (
402 .out (net129 ),
403 .in2 (qb0[3] ),
404 .in0 (qb2[3] ),
405 .in1 (qb1[3] ) );
406cl_u1_inv_2x xb_0_ (
407 .out (qb0[0] ),
408 .in (net145[3] ) );
409cl_u1_inv_1x x5_3_ (
410 .out (net141[0] ),
411 .in (q2[3] ) );
412cl_u1_inv_2x x6_1_ (
413 .out (qb2[1] ),
414 .in (net141[2] ) );
415cl_sc1_msff_4x xa0_2_ (
416 .q (q0[2] ),
417 .so (so0[2] ),
418 .soclk (net192 ),
419 .siclk (net190 ),
420 .si (so0[1] ),
421 .l1clk (net154 ),
422 .d (qb0[1] ) );
423cl_sc1_msff_4x xa1_0_ (
424 .q (q1[0] ),
425 .so (so1[0] ),
426 .soclk (net192 ),
427 .siclk (net190 ),
428 .si (so0[3] ),
429 .l1clk (net154 ),
430 .d (data[1] ) );
431cl_u1_buf_8x xc (
432 .out (net190 ),
433 .in (siclk ) );
434cl_u1_nand2_2x x3_0_ (
435 .out (data[0] ),
436 .in1 (ctrl[0] ),
437 .in0 (raw_data[0] ) );
438cl_u1_inv_2x xb_1_ (
439 .out (qb0[1] ),
440 .in (net145[2] ) );
441cl_u1_inv_1x x7_0_ (
442 .out (net143[3] ),
443 .in (q1[0] ) );
444cl_u1_inv_2x x6_2_ (
445 .out (qb2[2] ),
446 .in (net141[1] ) );
447cl_sc1_msff_4x xa0_3_ (
448 .q (q0[3] ),
449 .so (so0[3] ),
450 .soclk (net192 ),
451 .siclk (net190 ),
452 .si (so0[2] ),
453 .l1clk (net154 ),
454 .d (qb0[2] ) );
455cl_sc1_msff_4x xa1_1_ (
456 .q (q1[1] ),
457 .so (so1[1] ),
458 .soclk (net192 ),
459 .siclk (net190 ),
460 .si (so1[0] ),
461 .l1clk (net154 ),
462 .d (qb1[0] ) );
463cl_u1_nand2_2x x3_1_ (
464 .out (data[1] ),
465 .in1 (ctrl[1] ),
466 .in0 (raw_data[1] ) );
467cl_u1_inv_2x xb_2_ (
468 .out (qb0[2] ),
469 .in (net145[1] ) );
470cl_u1_inv_1x x7_1_ (
471 .out (net143[2] ),
472 .in (q1[1] ) );
473cl_u1_inv_2x x6_3_ (
474 .out (qb2[3] ),
475 .in (net141[0] ) );
476//pmos m0 (so ,vdd ,net081 );
477cl_sc1_msff_4x xa2_0_ (
478 .q (q2[0] ),
479 .so (so2[0] ),
480 .soclk (net192 ),
481 .siclk (net190 ),
482 .si (so1[3] ),
483 .l1clk (net154 ),
484 .d (data[2] ) );
485cl_sc1_msff_4x xa1_2_ (
486 .q (q1[2] ),
487 .so (so1[2] ),
488 .soclk (net192 ),
489 .siclk (net190 ),
490 .si (so1[1] ),
491 .l1clk (net154 ),
492 .d (qb1[1] ) );
493//pmos m1 (net081 ,vdd ,sob );
494//nmos m2 (so ,vss ,net081 );
495//nmos m3 (net081 ,vss ,sob );
496cl_u1_nand2_2x x3_2_ (
497 .out (data[2] ),
498 .in1 (ctrl[2] ),
499 .in0 (raw_data[2] ) );
500cl_u1_inv_2x xb_3_ (
501 .out (qb0[3] ),
502 .in (net145[0] ) );
503cl_u1_inv_2x x4_0_ (
504 .out (qb1[0] ),
505 .in (net143[3] ) );
506cl_u1_inv_1x x8_0_ (
507 .out (net145[3] ),
508 .in (q0[0] ) );
509cl_u1_inv_1x x7_2_ (
510 .out (net143[1] ),
511 .in (q1[2] ) );
512//nmos mn0 (net057 ,vss ,net193 );
513//nmos mn1 (rng_data ,vss ,net057 );
514cl_sc1_msff_4x xa2_1_ (
515 .q (q2[1] ),
516 .so (so2[1] ),
517 .soclk (net192 ),
518 .siclk (net190 ),
519 .si (so2[0] ),
520 .l1clk (net154 ),
521 .d (qb2[0] ) );
522cl_sc1_msff_4x xa1_3_ (
523 .q (q1[3] ),
524 .so (so1[3] ),
525 .soclk (net192 ),
526 .siclk (net190 ),
527 .si (so1[2] ),
528 .l1clk (net154 ),
529 .d (qb1[2] ) );
530cl_u1_inv_2x x4_1_ (
531 .out (qb1[1] ),
532 .in (net143[2] ) );
533cl_u1_inv_1x x8_1_ (
534 .out (net145[2] ),
535 .in (q0[1] ) );
536cl_u1_inv_1x x7_3_ (
537 .out (net143[0] ),
538 .in (q1[3] ) );
539cl_sc1_msff_4x xa2_2_ (
540 .q (q2[2] ),
541 .so (so2[2] ),
542 .soclk (net192 ),
543 .siclk (net190 ),
544 .si (so2[1] ),
545 .l1clk (net154 ),
546 .d (qb2[1] ) );
547cl_u1_inv_1x x5_0_ (
548 .out (net141[3] ),
549 .in (q2[0] ) );
550cl_u1_inv_2x x4_2_ (
551 .out (qb1[2] ),
552 .in (net143[1] ) );
553cl_u1_inv_1x x8_2_ (
554 .out (net145[1] ),
555 .in (q0[2] ) );
556//pmos mp0 (net057 ,vdd ,net193 );
557//pmos mp1 (rng_data ,vdd ,net057 );
558cl_sc1_msff_4x xa2_3_ (
559 .q (q2[3] ),
560 .so (sob ),
561 .soclk (net192 ),
562 .siclk (net190 ),
563 .si (so2[2] ),
564 .l1clk (net154 ),
565 .d (qb2[2] ) );
566cl_sc1_l1hdr_16x x0 (
567 .se (se ),
568 .pce (vdd ),
569 .pce_ov (vdd ),
570 .stop (stop ),
571 .l2clk (l2clk_v1 ),
572 .l1clk (net154 ) );
573cl_u1_buf_8x x1 (
574 .out (net192 ),
575 .in (soclk ) );
576endmodule
577
578//
579// N2_RNG_REG_CUST - vgate file generated by KC
580//
581module n2_rng_reg_cust(fast_vco ,ctrl ,amux_sel1 ,amux_sel0 ,amux_off ,
582 l2clk ,stop ,arst_l ,amux_sel2 ,anlg_sel ,vcoctrl_sel ,ch_sel ,
583 vcoctrl_sel0 ,vcoctrl_sel1 ,vcoctrl_sel2 );
584output [2:0] ctrl ;
585output [1:0] amux_sel1 ;
586output [1:0] amux_sel0 ;
587output [1:0] amux_sel2 ;
588output [3:0] vcoctrl_sel0 ;
589output [3:0] vcoctrl_sel1 ;
590output [3:0] vcoctrl_sel2 ;
591input [1:0] anlg_sel ;
592input [1:0] vcoctrl_sel ;
593input [1:0] ch_sel ;
594output fast_vco ;
595output amux_off ;
596input l2clk ;
597input stop ;
598input arst_l ;
599supply1 vdd ;
600supply0 vss ;
601
602wire [1:0] net399 ;
603wire [1:0] net253 ;
604wire [1:0] net395 ;
605wire [3:0] ch_sel_d ;
606wire [1:0] net328 ;
607wire [1:0] net232 ;
608wire [1:0] ch_sel_d1 ;
609wire [1:0] net258 ;
610wire [1:0] vco_sel_d1 ;
611wire [0:0] anlg_sel_d ;
612wire [1:0] net227 ;
613wire [1:0] net237 ;
614wire [1:0] net247 ;
615wire [1:0] net243 ;
616wire [1:0] net251 ;
617wire [1:0] net255 ;
618wire [1:0] net269 ;
619wire [1:0] net265 ;
620wire [2:0] net279 ;
621wire [1:0] anlg_sel_d1 ;
622wire [1:0] net400 ;
623wire [1:0] net397 ;
624wire [2:0] net393 ;
625wire [2:0] dctrl ;
626wire [1:0] net230 ;
627wire [1:0] net262 ;
628wire [1:0] net272 ;
629wire [1:0] net401 ;
630wire [1:0] net225 ;
631wire [1:0] net425 ;
632wire [1:0] net235 ;
633wire [1:0] net249 ;
634wire [1:0] net245 ;
635wire net380 ;
636wire net300 ;
637wire net283 ;
638wire net286 ;
639wire net403 ;
640wire net307 ;
641wire net389 ;
642wire net210 ;
643wire net293 ;
644wire net212 ;
645wire net0204 ;
646wire net0207 ;
647wire net394 ;
648wire net215 ;
649wire net217 ;
650wire net220 ;
651wire net222 ;
652wire net439 ;
653wire net441 ;
654wire net443 ;
655wire net445 ;
656wire net447 ;
657wire net449 ;
658wire arst ;
659wire l2clk_v1 ;
660wire net0210 ;
661wire net0212 ;
662wire l1clk ;
663wire net360 ;
664wire net364 ;
665wire net368 ;
666wire net0225 ;
667wire net372 ;
668wire net377 ;
669
670assign arst=net389;
671
672cl_u1_inv_1x x2 (
673 .out (dctrl[0] ),
674 .in (net0210 ) );
675//terminator ix32 (
676// .TERM (net394 ) );
677n2_rng_dec_cust x5 (
678 .dec_sel ({vcoctrl_sel2 } ),
679 .sel ({net237[0] ,net237[1] } ),
680 .vdd_reg (vdd ) );
681n2_core_pll_flop_reset_new_1x_cust xa_0_ (
682 .vdd_reg (vdd ),
683 .reset_val_l (vdd ),
684 .d (net251[1] ),
685 .reset (arst ),
686 .clk (l1clk ),
687 .q_l (net328[1] ),
688 .q (ch_sel_d1[0] ) );
689cl_u1_buf_2x x6 (
690 .out (net283 ),
691 .in (anlg_sel_d1[1] ) );
692//terminator ix9_0_ (
693// .TERM (net395[1] ) );
694cl_u1_buf_2x x7 (
695 .out (anlg_sel_d[0] ),
696 .in (anlg_sel_d1[0] ) );
697cl_u1_nand3_2x x8 (
698 .out (net380 ),
699 .in2 (net403 ),
700 .in1 (ctrl[2] ),
701 .in0 (net307 ) );
702n2_rng_dec_cust x9 (
703 .dec_sel ({vcoctrl_sel1 } ),
704 .sel ({net232[0] ,net232[1] } ),
705 .vdd_reg (vdd ) );
706cl_u1_inv_8x x45_1_ (
707 .out (ctrl[1] ),
708 .in (net279[1] ) );
709cl_u1_inv_4x x49_1_ (
710 .out (net253[0] ),
711 .in (net245[0] ) );
712//terminator ixn2_0_ (
713// .TERM (net401[1] ) );
714cl_sc1_aomux2_4x xm2_1_ (
715 .in1 (net425[0] ),
716 .sel1 (ch_sel_d[2] ),
717 .out (net235[0] ),
718 .in0 (net237[0] ),
719 .sel0 (net449 ) );
720n2_core_pll_flop_reset_new_1x_cust xa_1_ (
721 .vdd_reg (vdd ),
722 .reset_val_l (vdd ),
723 .d (net251[0] ),
724 .reset (arst ),
725 .clk (l1clk ),
726 .q_l (net328[0] ),
727 .q (ch_sel_d1[1] ) );
728//terminator ix9_1_ (
729// .TERM (net395[0] ) );
730//terminator i4_0_ (
731// .TERM (net393[2] ) );
732n2_core_pll_flop_reset_new_1x_cust x42_0_ (
733 .vdd_reg (vdd ),
734 .reset_val_l (vss ),
735 .d (dctrl[0] ),
736 .reset (arst ),
737 .clk (l1clk ),
738 .q_l (net279[2] ),
739 .q (net393[2] ) );
740cl_u1_inv_8x x45_2_ (
741 .out (ctrl[2] ),
742 .in (net279[0] ) );
743cl_u1_inv_4x x46_0_ (
744 .out (net251[1] ),
745 .in (net243[1] ) );
746cl_u1_inv_2x x11 (
747 .out (net443 ),
748 .in (ch_sel_d[2] ) );
749cl_u1_nand3_2x x12 (
750 .out (net377 ),
751 .in2 (net403 ),
752 .in1 (ctrl[2] ),
753 .in0 (net222 ) );
754cl_u1_inv_4x x50_0_ (
755 .out (net247[1] ),
756 .in (net249[1] ) );
757//terminator ixn0_1_ (
758// .TERM (net399[0] ) );
759cl_sc1_aomux2_4x x13 (
760 .in1 (anlg_sel_d[0] ),
761 .sel1 (ch_sel_d[2] ),
762 .out (net220 ),
763 .in0 (net222 ),
764 .sel0 (net443 ) );
765n2_core_pll_flop_reset_new_1x_cust x14 (
766 .vdd_reg (vdd ),
767 .reset_val_l (vdd ),
768 .d (net220 ),
769 .reset (arst ),
770 .clk (l1clk ),
771 .q_l (net307 ),
772 .q (net222 ) );
773cl_u1_inv_2x xi0 (
774 .out (net445 ),
775 .in (ch_sel_d[0] ) );
776cl_u1_inv_8x x15 (
777 .out (amux_sel2[1] ),
778 .in (net377 ) );
779cl_u1_inv_2x xi1 (
780 .out (net447 ),
781 .in (ch_sel_d[1] ) );
782cl_u1_inv_8x x16 (
783 .out (amux_sel2[0] ),
784 .in (net380 ) );
785cl_u1_inv_2x xi2 (
786 .out (net449 ),
787 .in (ch_sel_d[2] ) );
788cl_u1_inv_8x x17 (
789 .out (amux_sel1[0] ),
790 .in (net372 ) );
791cl_u1_inv_8x x18 (
792 .out (amux_sel1[1] ),
793 .in (net360 ) );
794n2_core_pll_flop_reset_new_1x_cust xv0_0_ (
795 .vdd_reg (vdd ),
796 .reset_val_l (vdd ),
797 .d (net225[1] ),
798 .reset (arst ),
799 .clk (l1clk ),
800 .q_l (net399[1] ),
801 .q (net227[1] ) );
802cl_u1_nand3_2x x19 (
803 .out (net372 ),
804 .in2 (net403 ),
805 .in1 (ctrl[1] ),
806 .in0 (net300 ) );
807//terminator i15_0_ (
808// .TERM (net272[1] ) );
809//terminator i4_1_ (
810// .TERM (net393[1] ) );
811n2_core_pll_flop_reset_new_1x_cust x42_1_ (
812 .vdd_reg (vdd ),
813 .reset_val_l (vdd ),
814 .d (dctrl[1] ),
815 .reset (arst ),
816 .clk (l1clk ),
817 .q_l (net279[1] ),
818 .q (net393[1] ) );
819cl_u1_nand3_2x x20 (
820 .out (net360 ),
821 .in2 (net403 ),
822 .in1 (ctrl[1] ),
823 .in0 (net217 ) );
824cl_u1_inv_4x x46_1_ (
825 .out (net251[0] ),
826 .in (net243[0] ) );
827cl_u1_inv_2x x21 (
828 .out (net439 ),
829 .in (ch_sel_d[1] ) );
830cl_u1_inv_4x x50_1_ (
831 .out (net247[0] ),
832 .in (net249[0] ) );
833cl_sc1_aomux2_4x x22 (
834 .in1 (anlg_sel_d[0] ),
835 .sel1 (ch_sel_d[1] ),
836 .out (net215 ),
837 .in0 (net217 ),
838 .sel0 (net439 ) );
839n2_core_pll_flop_reset_new_1x_cust x23 (
840 .vdd_reg (vdd ),
841 .reset_val_l (vdd ),
842 .d (net215 ),
843 .reset (arst ),
844 .clk (l1clk ),
845 .q_l (net300 ),
846 .q (net217 ) );
847cl_u1_inv_8x x24 (
848 .out (amux_sel0[1] ),
849 .in (net368 ) );
850cl_u1_inv_8x x25 (
851 .out (amux_sel0[0] ),
852 .in (net364 ) );
853//terminator ixb_0_ (
854// .TERM (net328[1] ) );
855cl_u1_nand3_2x x26 (
856 .out (net368 ),
857 .in2 (net403 ),
858 .in1 (ctrl[0] ),
859 .in0 (net212 ) );
860cl_u1_nand3_2x x27 (
861 .out (net364 ),
862 .in2 (net403 ),
863 .in1 (ctrl[0] ),
864 .in0 (net293 ) );
865cl_u1_inv_2x x28 (
866 .out (net441 ),
867 .in (ch_sel_d[0] ) );
868n2_core_pll_flop_reset_new_1x_cust xv0_1_ (
869 .vdd_reg (vdd ),
870 .reset_val_l (vdd ),
871 .d (net225[0] ),
872 .reset (arst ),
873 .clk (l1clk ),
874 .q_l (net399[0] ),
875 .q (net227[0] ) );
876cl_sc1_aomux2_4x x29 (
877 .in1 (anlg_sel_d[0] ),
878 .sel1 (ch_sel_d[0] ),
879 .out (net210 ),
880 .in0 (net212 ),
881 .sel0 (net441 ) );
882n2_core_pll_flop_reset_new_1x_cust x3_0_ (
883 .vdd_reg (vdd ),
884 .reset_val_l (vdd ),
885 .d (ch_sel[0] ),
886 .reset (arst ),
887 .clk (l1clk ),
888 .q_l (net258[1] ),
889 .q (net255[1] ) );
890//terminator i15_1_ (
891// .TERM (net272[0] ) );
892//terminator i4_2_ (
893// .TERM (net393[0] ) );
894n2_core_pll_flop_reset_new_1x_cust x42_2_ (
895 .vdd_reg (vdd ),
896 .reset_val_l (vdd ),
897 .d (dctrl[2] ),
898 .reset (arst ),
899 .clk (l1clk ),
900 .q_l (net279[0] ),
901 .q (net393[0] ) );
902n2_core_pll_flop_reset_new_1x_cust x43_0_ (
903 .vdd_reg (vdd ),
904 .reset_val_l (vdd ),
905 .d (vcoctrl_sel[0] ),
906 .reset (arst ),
907 .clk (l1clk ),
908 .q_l (net265[1] ),
909 .q (net262[1] ) );
910n2_core_pll_flop_reset_new_1x_cust x30 (
911 .vdd_reg (vdd ),
912 .reset_val_l (vdd ),
913 .d (net210 ),
914 .reset (arst ),
915 .clk (l1clk ),
916 .q_l (net293 ),
917 .q (net212 ) );
918cl_u1_inv_4x x47_0_ (
919 .out (net243[1] ),
920 .in (net255[1] ) );
921n2_core_pll_flop_reset_new_1x_cust x31 (
922 .vdd_reg (vdd ),
923 .reset_val_l (vss ),
924 .d (net283 ),
925 .reset (arst ),
926 .clk (l1clk ),
927 .q_l (net286 ),
928 .q (net394 ) );
929cl_u1_inv_8x x32 (
930 .out (amux_off ),
931 .in (net403 ) );
932cl_u1_inv_4x x51_0_ (
933 .out (net249[1] ),
934 .in (net269[1] ) );
935cl_u1_buf_8x x33 (
936 .out (net403 ),
937 .in (net286 ) );
938//terminator ixn1_1_ (
939// .TERM (net400[0] ) );
940cl_sc1_l1hdr_48x x34 (
941 .pce (vdd ),
942 .pce_ov (vdd ),
943 .stop (stop ),
944 .l2clk (l2clk_v1 ),
945 .se (vss ),
946 .l1clk (l1clk ) );
947cl_sc1_aomux2_4x xm0_0_ (
948 .in1 (net425[1] ),
949 .sel1 (ch_sel_d[0] ),
950 .out (net225[1] ),
951 .in0 (net227[1] ),
952 .sel0 (net445 ) );
953//terminator ixb_1_ (
954// .TERM (net328[0] ) );
955cl_u1_inv_2x x36 (
956 .out (net389 ),
957 .in (arst_l ) );
958cl_u1_nor2_1x x37 (
959 .out (net0204 ),
960 .in1 (ch_sel_d[2] ),
961 .in0 (ch_sel_d[3] ) );
962n2_core_pll_flop_reset_new_1x_cust xv1_0_ (
963 .vdd_reg (vdd ),
964 .reset_val_l (vdd ),
965 .d (net230[1] ),
966 .reset (arst ),
967 .clk (l1clk ),
968 .q_l (net400[1] ),
969 .q (net232[1] ) );
970cl_u1_nor2_1x x38 (
971 .out (net0207 ),
972 .in1 (ch_sel_d[1] ),
973 .in0 (ch_sel_d[3] ) );
974//terminator ix3_0_ (
975// .TERM (net397[1] ) );
976cl_u1_nor2_1x x39 (
977 .out (net0210 ),
978 .in1 (ch_sel_d[0] ),
979 .in0 (ch_sel_d[3] ) );
980n2_core_pll_flop_reset_new_1x_cust x3_1_ (
981 .vdd_reg (vdd ),
982 .reset_val_l (vdd ),
983 .d (ch_sel[1] ),
984 .reset (arst ),
985 .clk (l1clk ),
986 .q_l (net258[0] ),
987 .q (net255[0] ) );
988//terminator i16_0_ (
989// .TERM (net265[1] ) );
990n2_core_pll_flop_reset_new_1x_cust x43_1_ (
991 .vdd_reg (vdd ),
992 .reset_val_l (vdd ),
993 .d (vcoctrl_sel[1] ),
994 .reset (arst ),
995 .clk (l1clk ),
996 .q_l (net265[0] ),
997 .q (net262[0] ) );
998cl_u1_inv_4x x47_1_ (
999 .out (net243[0] ),
1000 .in (net255[0] ) );
1001n2_rng_dec_cust x41 (
1002 .dec_sel ({vcoctrl_sel0 } ),
1003 .sel ({net227[0] ,net227[1] } ),
1004 .vdd_reg (vdd ) );
1005n2_core_pll_flop_reset_new_1x_cust x10_0_ (
1006 .vdd_reg (vdd ),
1007 .reset_val_l (vdd ),
1008 .d (net247[1] ),
1009 .reset (arst ),
1010 .clk (l1clk ),
1011 .q_l (net395[1] ),
1012 .q (anlg_sel_d1[0] ) );
1013cl_u1_inv_4x x51_1_ (
1014 .out (net249[0] ),
1015 .in (net269[0] ) );
1016//terminator ixn0_0_ (
1017// .TERM (net399[1] ) );
1018cl_sc1_aomux2_4x xm0_1_ (
1019 .in1 (net425[0] ),
1020 .sel1 (ch_sel_d[0] ),
1021 .out (net225[0] ),
1022 .in0 (net227[0] ),
1023 .sel0 (net445 ) );
1024n2_core_pll_flop_reset_new_1x_cust xv1_1_ (
1025 .vdd_reg (vdd ),
1026 .reset_val_l (vdd ),
1027 .d (net230[0] ),
1028 .reset (arst ),
1029 .clk (l1clk ),
1030 .q_l (net400[0] ),
1031 .q (net232[0] ) );
1032//terminator ix3_1_ (
1033// .TERM (net397[0] ) );
1034n2_core_pll_flop_reset_new_1x_cust x4_0_ (
1035 .vdd_reg (vdd ),
1036 .reset_val_l (vdd ),
1037 .d (net253[1] ),
1038 .reset (arst ),
1039 .clk (l1clk ),
1040 .q_l (net397[1] ),
1041 .q (vco_sel_d1[0] ) );
1042//terminator i16_1_ (
1043// .TERM (net265[0] ) );
1044cl_u1_buf_2x x40_0_ (
1045 .out (net425[1] ),
1046 .in (vco_sel_d1[0] ) );
1047n2_core_pll_flop_reset_new_1x_cust x44_0_ (
1048 .vdd_reg (vdd ),
1049 .reset_val_l (vdd ),
1050 .d (anlg_sel[0] ),
1051 .reset (arst ),
1052 .clk (l1clk ),
1053 .q_l (net272[1] ),
1054 .q (net269[1] ) );
1055n2_rng_dec_cust x52 (
1056 .dec_sel ({ch_sel_d } ),
1057 .sel ({ch_sel_d1 } ),
1058 .vdd_reg (vdd ) );
1059cl_u1_inv_4x x48_0_ (
1060 .out (net245[1] ),
1061 .in (net262[1] ) );
1062cl_u1_nand2_2x x53 (
1063 .out (net0212 ),
1064 .in1 (amux_off ),
1065 .in0 (anlg_sel_d[0] ) );
1066//nmos mn0 (net0225 ,vss ,net389 );
1067cl_u1_inv_8x x54 (
1068 .out (fast_vco ),
1069 .in (net0212 ) );
1070n2_core_pll_flop_reset_new_1x_cust x10_1_ (
1071 .vdd_reg (vdd ),
1072 .reset_val_l (vss ),
1073 .d (net247[0] ),
1074 .reset (arst ),
1075 .clk (l1clk ),
1076 .q_l (net395[0] ),
1077 .q (anlg_sel_d1[1] ) );
1078//nmos mn1 (arst ,vss ,net0225 );
1079//terminator ixn2_1_ (
1080// .TERM (net401[0] ) );
1081cl_u1_buf_16x x55 (
1082 .out (l2clk_v1 ),
1083 .in (l2clk ) );
1084cl_sc1_aomux2_4x xm1_0_ (
1085 .in1 (net425[1] ),
1086 .sel1 (ch_sel_d[1] ),
1087 .out (net230[1] ),
1088 .in0 (net232[1] ),
1089 .sel0 (net447 ) );
1090cl_sc1_l1hdr_32x x56 (
1091 .se (vss ),
1092 .l1clk (l1clk ),
1093 .l2clk (l2clk_v1 ),
1094 .stop (stop ),
1095 .pce_ov (vdd ),
1096 .pce (vdd ) );
1097n2_core_pll_flop_reset_new_1x_cust xv2_0_ (
1098 .vdd_reg (vdd ),
1099 .reset_val_l (vdd ),
1100 .d (net235[1] ),
1101 .reset (arst ),
1102 .clk (l1clk ),
1103 .q_l (net401[1] ),
1104 .q (net237[1] ) );
1105n2_core_pll_flop_reset_new_1x_cust x4_1_ (
1106 .vdd_reg (vdd ),
1107 .reset_val_l (vdd ),
1108 .d (net253[0] ),
1109 .reset (arst ),
1110 .clk (l1clk ),
1111 .q_l (net397[0] ),
1112 .q (vco_sel_d1[1] ) );
1113//terminator i17_0_ (
1114// .TERM (net258[1] ) );
1115cl_u1_buf_2x x40_1_ (
1116 .out (net425[0] ),
1117 .in (vco_sel_d1[1] ) );
1118n2_core_pll_flop_reset_new_1x_cust x44_1_ (
1119 .vdd_reg (vdd ),
1120 .reset_val_l (vss ),
1121 .d (anlg_sel[1] ),
1122 .reset (arst ),
1123 .clk (l1clk ),
1124 .q_l (net272[0] ),
1125 .q (net269[0] ) );
1126cl_u1_inv_4x x48_1_ (
1127 .out (net245[0] ),
1128 .in (net262[0] ) );
1129//terminator ixn1_0_ (
1130// .TERM (net400[1] ) );
1131cl_sc1_aomux2_4x xm1_1_ (
1132 .in1 (net425[0] ),
1133 .sel1 (ch_sel_d[1] ),
1134 .out (net230[0] ),
1135 .in0 (net232[0] ),
1136 .sel0 (net447 ) );
1137n2_core_pll_flop_reset_new_1x_cust xv2_1_ (
1138 .vdd_reg (vdd ),
1139 .reset_val_l (vdd ),
1140 .d (net235[0] ),
1141 .reset (arst ),
1142 .clk (l1clk ),
1143 .q_l (net401[0] ),
1144 .q (net237[0] ) );
1145//terminator i17_1_ (
1146// .TERM (net258[0] ) );
1147cl_u1_inv_8x x45_0_ (
1148 .out (ctrl[0] ),
1149 .in (net279[2] ) );
1150cl_u1_inv_4x x49_0_ (
1151 .out (net253[1] ),
1152 .in (net245[1] ) );
1153//pmos mp0 (net0225 ,vdd ,net389 );
1154//pmos mp1 (arst ,vdd ,net0225 );
1155cl_u1_inv_1x x0 (
1156 .out (dctrl[2] ),
1157 .in (net0204 ) );
1158cl_sc1_aomux2_4x xm2_0_ (
1159 .in1 (net425[1] ),
1160 .sel1 (ch_sel_d[2] ),
1161 .out (net235[1] ),
1162 .in0 (net237[1] ),
1163 .sel0 (net449 ) );
1164cl_u1_inv_1x x1 (
1165 .out (dctrl[1] ),
1166 .in (net0207 ) );
1167endmodule
1168
1169
1170//
1171// N2_RNG_DEC_CUST - vgate file generated by KC
1172//
1173module n2_rng_dec_cust(dec_sel ,vdd_reg ,sel );
1174output [3:0] dec_sel ;
1175input [1:0] sel ;
1176input vdd_reg ;
1177
1178wire [3:0] net9 ;
1179wire [1:0] sel_d ;
1180wire [1:0] sel_l ;
1181
1182
1183n2_core_pll_inv_1x_cust x1_1_ (
1184 .vdd_reg (vdd_reg ),
1185 .out (sel_d[1] ),
1186 .in (sel_l[1] ) );
1187n2_core_pll_nand2_2x_cust x2_0_ (
1188 .vdd_reg (vdd_reg ),
1189 .out (net9[3] ),
1190 .in1 (sel_l[0] ),
1191 .in0 (sel_l[1] ) );
1192n2_core_pll_nand2_2x_cust x2_1_ (
1193 .vdd_reg (vdd_reg ),
1194 .out (net9[2] ),
1195 .in1 (sel_d[0] ),
1196 .in0 (sel_l[1] ) );
1197n2_core_pll_inv_8x_cust x3_0_ (
1198 .vdd_reg (vdd_reg ),
1199 .out (dec_sel[0] ),
1200 .in (net9[3] ) );
1201n2_core_pll_nand2_2x_cust x2_2_ (
1202 .vdd_reg (vdd_reg ),
1203 .out (net9[1] ),
1204 .in1 (sel_l[0] ),
1205 .in0 (sel_d[1] ) );
1206n2_core_pll_inv_8x_cust x3_1_ (
1207 .vdd_reg (vdd_reg ),
1208 .out (dec_sel[1] ),
1209 .in (net9[2] ) );
1210n2_core_pll_nand2_2x_cust x2_3_ (
1211 .vdd_reg (vdd_reg ),
1212 .out (net9[0] ),
1213 .in1 (sel_d[0] ),
1214 .in0 (sel_d[1] ) );
1215n2_core_pll_inv_8x_cust x3_2_ (
1216 .vdd_reg (vdd_reg ),
1217 .out (dec_sel[2] ),
1218 .in (net9[1] ) );
1219n2_core_pll_inv_1x_cust x0_0_ (
1220 .vdd_reg (vdd_reg ),
1221 .out (sel_l[0] ),
1222 .in (sel[0] ) );
1223n2_core_pll_inv_8x_cust x3_3_ (
1224 .vdd_reg (vdd_reg ),
1225 .out (dec_sel[3] ),
1226 .in (net9[0] ) );
1227n2_core_pll_inv_1x_cust x0_1_ (
1228 .vdd_reg (vdd_reg ),
1229 .out (sel_l[1] ),
1230 .in (sel[1] ) );
1231n2_core_pll_inv_1x_cust x1_0_ (
1232 .vdd_reg (vdd_reg ),
1233 .out (sel_d[0] ),
1234 .in (sel_l[0] ) );
1235endmodule
1236
Full OpenSPARC design & verification tarball including full HDL.