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// OpenSPARC T2 Processor File: n2_rng_cust.v
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module n2_rng_cust(vreg_selbg_l ,rng_arst_l ,ch_sel ,anlg_sel ,
vcoctrl_sel ,vdd_hv15 ,soclk ,si ,anlg_char_out ,bypass ,
tcu_se_scancollar_out ,so ,stop ,l2clk ,siclk ,rng_data );
input [1:0] vcoctrl_sel ;
input tcu_se_scancollar_out ;
wire [3:0] vcoctrl_sel2 ;
wire [3:0] vcoctrl_sel1 ;
wire [3:0] vcoctrl_sel0 ;
// .i50n ({i50n9_lowv ,i50n8_lowv ,i50n7_lowv ,i50n6_lowv ,
// i50n5_lowv ,i50n4_lowv ,i50n3_lowv ,i50n2_lowv ,i50n1_lowv ,
// .v1p1reg_lowv (vdd_reg ),
// .vdd_hv15 (vdd_hv15 ),
// .selbg_l (vreg_selbg_l ) );
// .vddo_esd (vdd_hv15 ) );
//n2_esd_sig_3diode x10 (
// .sig (anlg_char_out ) );
//n2_rng_rc_filter_cust x98 (
// .rc_fltr_out (virt_vss ),
//n2_rng_resarray_cust x24 (
// .r ({net95 ,net093 ,v300m ,v400m ,v500m ,net055 ,vbn
.anlg_sel ({anlg_sel } ),
.vcoctrl_sel ({vcoctrl_sel } ),
.vcoctrl_sel2 ({vcoctrl_sel2 } ),
.amux_sel0 ({amux_sel0 } ),
.amux_sel1 ({amux_sel1 } ),
.amux_sel2 ({amux_sel2 } ),
.vcoctrl_sel0 ({vcoctrl_sel0 } ),
.vcoctrl_sel1 ({vcoctrl_sel1 } ),
.raw_data ({raw_data } ),
.se (tcu_se_scancollar_out ),
// .TERM (i50n6_lowv ) );
//n2_rng_channel_cust xx1_0_ (
// .vcoctrl_sel ({vcoctrl_sel0 } ),
// .amux_sel ({amux_sel0 } ),
// .inb40u (i50n3_lowv ),
// .ina40u (i50n0_lowv ),
// .virt_vss (virt_vss ),
// .vdd_hv15 (vdd_hv15 ),
// .anlg_char_out (anlg_char_out ),
// .ch_out (raw_data[0] ),
// .arst_l (rng_arst_l ),
// .fast_vco (vdd_reg ) );
// .TERM (i50n7_lowv ) );
//n2_rng_channel_cust xx1_1_ (
// .vcoctrl_sel ({vcoctrl_sel1 } ),
// .amux_sel ({amux_sel1 } ),
// .inb40u (i50n4_lowv ),
// .ina40u (i50n1_lowv ),
// .virt_vss (virt_vss ),
// .vdd_hv15 (vdd_hv15 ),
// .anlg_char_out (anlg_char_out ),
// .ch_out (raw_data[1] ),
// .arst_l (rng_arst_l ),
// .fast_vco (vdd_reg ) );
// .TERM (i50n8_lowv ) );
//n2_rng_channel_cust xx1_2_ (
// .vcoctrl_sel ({vcoctrl_sel2 } ),
// .amux_sel ({amux_sel2 } ),
// .inb40u (i50n5_lowv ),
// .ina40u (i50n2_lowv ),
// .virt_vss (virt_vss ),
// .vdd_hv15 (vdd_hv15 ),
// .anlg_char_out (anlg_char_out ),
// .ch_out (raw_data[2] ),
// .arst_l (rng_arst_l ),
// .fast_vco (vdd_reg ) );
// .TERM (i50n9_lowv ) );
//n2_rng_hvamux_cust x0 (
// .vdd_hv15 (vdd_hv15 ),
// .amux_sel (amux_off ),
// .out (anlg_char_out ) );
//===== following code added for testbench (7/26/06) =====
if (!($test$plusargs("disable_rng_noisecell"))) begin
force raw_data = noise_cells;
@(posedge l2clk or negedge rng_arst_l);
noise_cells <= $random (seed);
// N2_RNG_SAMPLER_CUST - vgate file generated by KC
module n2_rng_sampler_cust(arst_l ,anlg_sel ,vcoctrl_sel ,ch_sel ,
vcoctrl_sel2 ,amux_off ,amux_sel0 ,amux_sel1 ,amux_sel2 ,
vcoctrl_sel0 ,vcoctrl_sel1 ,fast_vco ,si ,so ,rng_data ,raw_data ,
se ,l2clk ,stop ,siclk ,soclk );
output [3:0] vcoctrl_sel2 ;
output [3:0] vcoctrl_sel0 ;
output [3:0] vcoctrl_sel1 ;
input [1:0] vcoctrl_sel ;
.amux_sel1 ({amux_sel1 } ),
.amux_sel0 ({amux_sel0 } ),
.amux_sel2 ({amux_sel2 } ),
.anlg_sel ({anlg_sel } ),
.vcoctrl_sel ({vcoctrl_sel } ),
.vcoctrl_sel0 ({vcoctrl_sel0 } ),
.vcoctrl_sel1 ({vcoctrl_sel1 } ),
.vcoctrl_sel2 ({vcoctrl_sel2 } ),
.raw_data ({raw_data } ),
// N2_RNG_SYNC_CUST - vgate file generated by KC
module n2_rng_sync_cust(ctrl ,si ,so ,rng_data ,raw_data ,se ,l2clk ,
//pmos m0 (so ,vdd ,net081 );
//pmos m1 (net081 ,vdd ,sob );
//nmos m2 (so ,vss ,net081 );
//nmos m3 (net081 ,vss ,sob );
//nmos mn0 (net057 ,vss ,net193 );
//nmos mn1 (rng_data ,vss ,net057 );
//pmos mp0 (net057 ,vdd ,net193 );
//pmos mp1 (rng_data ,vdd ,net057 );
// N2_RNG_REG_CUST - vgate file generated by KC
module n2_rng_reg_cust(fast_vco ,ctrl ,amux_sel1 ,amux_sel0 ,amux_off ,
l2clk ,stop ,arst_l ,amux_sel2 ,anlg_sel ,vcoctrl_sel ,ch_sel ,
vcoctrl_sel0 ,vcoctrl_sel1 ,vcoctrl_sel2 );
output [3:0] vcoctrl_sel0 ;
output [3:0] vcoctrl_sel1 ;
output [3:0] vcoctrl_sel2 ;
input [1:0] vcoctrl_sel ;
.dec_sel ({vcoctrl_sel2 } ),
.sel ({net237[0] ,net237[1] } ),
n2_core_pll_flop_reset_new_1x_cust xa_0_ (
.dec_sel ({vcoctrl_sel1 } ),
.sel ({net232[0] ,net232[1] } ),
cl_sc1_aomux2_4x xm2_1_ (
n2_core_pll_flop_reset_new_1x_cust xa_1_ (
n2_core_pll_flop_reset_new_1x_cust x42_0_ (
n2_core_pll_flop_reset_new_1x_cust x14 (
n2_core_pll_flop_reset_new_1x_cust xv0_0_ (
n2_core_pll_flop_reset_new_1x_cust x42_1_ (
n2_core_pll_flop_reset_new_1x_cust x23 (
n2_core_pll_flop_reset_new_1x_cust xv0_1_ (
n2_core_pll_flop_reset_new_1x_cust x3_0_ (
n2_core_pll_flop_reset_new_1x_cust x42_2_ (
n2_core_pll_flop_reset_new_1x_cust x43_0_ (
n2_core_pll_flop_reset_new_1x_cust x30 (
n2_core_pll_flop_reset_new_1x_cust x31 (
cl_sc1_aomux2_4x xm0_0_ (
n2_core_pll_flop_reset_new_1x_cust xv1_0_ (
n2_core_pll_flop_reset_new_1x_cust x3_1_ (
n2_core_pll_flop_reset_new_1x_cust x43_1_ (
.dec_sel ({vcoctrl_sel0 } ),
.sel ({net227[0] ,net227[1] } ),
n2_core_pll_flop_reset_new_1x_cust x10_0_ (
cl_sc1_aomux2_4x xm0_1_ (
n2_core_pll_flop_reset_new_1x_cust xv1_1_ (
n2_core_pll_flop_reset_new_1x_cust x4_0_ (
n2_core_pll_flop_reset_new_1x_cust x44_0_ (
//nmos mn0 (net0225 ,vss ,net389 );
n2_core_pll_flop_reset_new_1x_cust x10_1_ (
//nmos mn1 (arst ,vss ,net0225 );
cl_sc1_aomux2_4x xm1_0_ (
n2_core_pll_flop_reset_new_1x_cust xv2_0_ (
n2_core_pll_flop_reset_new_1x_cust x4_1_ (
n2_core_pll_flop_reset_new_1x_cust x44_1_ (
cl_sc1_aomux2_4x xm1_1_ (
n2_core_pll_flop_reset_new_1x_cust xv2_1_ (
//pmos mp0 (net0225 ,vdd ,net389 );
//pmos mp1 (arst ,vdd ,net0225 );
cl_sc1_aomux2_4x xm2_0_ (
// N2_RNG_DEC_CUST - vgate file generated by KC
module n2_rng_dec_cust(dec_sel ,vdd_reg ,sel );
n2_core_pll_inv_1x_cust x1_1_ (
n2_core_pll_nand2_2x_cust x2_0_ (
n2_core_pll_nand2_2x_cust x2_1_ (
n2_core_pll_inv_8x_cust x3_0_ (
n2_core_pll_nand2_2x_cust x2_2_ (
n2_core_pll_inv_8x_cust x3_1_ (
n2_core_pll_nand2_2x_cust x2_3_ (
n2_core_pll_inv_8x_cust x3_2_ (
n2_core_pll_inv_1x_cust x0_0_ (
n2_core_pll_inv_8x_cust x3_3_ (
n2_core_pll_inv_1x_cust x0_1_ (
n2_core_pll_inv_1x_cust x1_0_ (