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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: cl_dp1lvt.behV | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module cl_dp1lvt_add12_fulllvt_8x ( | |
36 | cin, | |
37 | in0, | |
38 | in1, | |
39 | out, | |
40 | cout | |
41 | ); | |
42 | input cin; | |
43 | input [11:0] in0; | |
44 | input [11:0] in1; | |
45 | output [11:0] out; | |
46 | output cout; | |
47 | ||
48 | `ifdef LIB | |
49 | assign {cout, out[11:0]} = ({1'b0, in0[11:0]} + {1'b0, in1[11:0]} + {{12{1'b0}}, cin}); | |
50 | `endif | |
51 | ||
52 | endmodule | |
53 | ||
54 | module cl_dp1lvt_add16_fulllvt_8x ( | |
55 | cin, | |
56 | in0, | |
57 | in1, | |
58 | out, | |
59 | cout | |
60 | ); | |
61 | input cin; | |
62 | input [15:0] in0; | |
63 | input [15:0] in1; | |
64 | output [15:0] out; | |
65 | output cout; | |
66 | ||
67 | `ifdef LIB | |
68 | assign {cout, out[15:0]} = ({1'b0, in0[15:0]} + {1'b0, in1[15:0]} + {{16{1'b0}}, cin}); | |
69 | `endif | |
70 | ||
71 | endmodule | |
72 | module cl_dp1lvt_add4_fulllvt_8x ( | |
73 | cin, | |
74 | in0, | |
75 | in1, | |
76 | out, | |
77 | cout | |
78 | ); | |
79 | input cin; | |
80 | input [3:0] in0; | |
81 | input [3:0] in1; | |
82 | output [3:0] out; | |
83 | output cout; | |
84 | ||
85 | `ifdef LIB | |
86 | assign {cout, out[3:0]} = ({1'b0, in0[3:0]} + {1'b0, in1[3:0]} + {{4{1'b0}}, cin}); | |
87 | `endif | |
88 | ||
89 | endmodule | |
90 | module cl_dp1lvt_add64_fulllvt_8x ( | |
91 | cin, | |
92 | in0, | |
93 | in1, | |
94 | out, | |
95 | cout | |
96 | ); | |
97 | input cin; | |
98 | input [63:0] in0; | |
99 | input [63:0] in1; | |
100 | output [63:0] out; | |
101 | output cout; | |
102 | ||
103 | `ifdef LIB | |
104 | assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin}); | |
105 | `endif | |
106 | ||
107 | endmodule | |
108 | module cl_dp1lvt_add8_fulllvt_8x ( | |
109 | cin, | |
110 | in0, | |
111 | in1, | |
112 | out, | |
113 | cout | |
114 | ); | |
115 | input cin; | |
116 | input [7:0] in0; | |
117 | input [7:0] in1; | |
118 | output [7:0] out; | |
119 | output cout; | |
120 | ||
121 | `ifdef LIB | |
122 | assign {cout, out[7:0]} = ({1'b0, in0[7:0]} + {1'b0, in1[7:0]} + {{8{1'b0}}, cin}); | |
123 | `endif | |
124 | ||
125 | endmodule | |
126 | module cl_dp1lvt_add12_8x ( | |
127 | cin, | |
128 | in0, | |
129 | in1, | |
130 | out, | |
131 | cout | |
132 | ); | |
133 | input cin; | |
134 | input [11:0] in0; | |
135 | input [11:0] in1; | |
136 | output [11:0] out; | |
137 | output cout; | |
138 | ||
139 | `ifdef LIB | |
140 | assign {cout, out[11:0]} = ({1'b0, in0[11:0]} + {1'b0, in1[11:0]} + {{12{1'b0}}, cin}); | |
141 | `endif | |
142 | ||
143 | endmodule | |
144 | module cl_dp1lvt_add16_8x ( | |
145 | cin, | |
146 | in0, | |
147 | in1, | |
148 | out, | |
149 | cout | |
150 | ); | |
151 | input cin; | |
152 | input [15:0] in0; | |
153 | input [15:0] in1; | |
154 | output [15:0] out; | |
155 | output cout; | |
156 | ||
157 | `ifdef LIB | |
158 | assign {cout, out[15:0]} = ({1'b0, in0[15:0]} + {1'b0, in1[15:0]} + {{16{1'b0}}, cin}); | |
159 | `endif | |
160 | ||
161 | endmodule | |
162 | module cl_dp1lvt_add32_8x ( | |
163 | cin, | |
164 | in0, | |
165 | in1, | |
166 | out, | |
167 | cout | |
168 | ); | |
169 | input cin; | |
170 | input [31:0] in0; | |
171 | input [31:0] in1; | |
172 | output [31:0] out; | |
173 | output cout; | |
174 | ||
175 | `ifdef LIB | |
176 | assign {cout, out[31:0]} = ({1'b0, in0[31:0]} + {1'b0, in1[31:0]} + {{32{1'b0}}, cin}); | |
177 | `endif | |
178 | ||
179 | endmodule | |
180 | module cl_dp1lvt_add4_8x ( | |
181 | cin, | |
182 | in0, | |
183 | in1, | |
184 | out, | |
185 | cout | |
186 | ); | |
187 | input cin; | |
188 | input [3:0] in0; | |
189 | input [3:0] in1; | |
190 | output [3:0] out; | |
191 | output cout; | |
192 | ||
193 | `ifdef LIB | |
194 | assign {cout, out[3:0]} = ({1'b0, in0[3:0]} + {1'b0, in1[3:0]} + {{4{1'b0}}, cin}); | |
195 | `endif | |
196 | ||
197 | endmodule | |
198 | module cl_dp1lvt_add64_8x ( | |
199 | cin, | |
200 | in0, | |
201 | in1, | |
202 | out, | |
203 | cout | |
204 | ); | |
205 | input cin; | |
206 | input [63:0] in0; | |
207 | input [63:0] in1; | |
208 | output [63:0] out; | |
209 | output cout; | |
210 | ||
211 | `ifdef LIB | |
212 | assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin}); | |
213 | `endif | |
214 | ||
215 | endmodule | |
216 | ||
217 | ||
218 | module cl_dp1lvt_cmpr12_8x ( | |
219 | in0, | |
220 | in1, | |
221 | out | |
222 | ); | |
223 | input [11:0] in0; | |
224 | input [11:0] in1; | |
225 | output out; | |
226 | ||
227 | `ifdef LIB | |
228 | assign out = (in0[11:0] == in1[11:0]); | |
229 | `endif | |
230 | ||
231 | endmodule | |
232 | module cl_dp1lvt_add8_8x ( | |
233 | cin, | |
234 | in0, | |
235 | in1, | |
236 | out, | |
237 | cout | |
238 | ); | |
239 | input cin; | |
240 | input [7:0] in0; | |
241 | input [7:0] in1; | |
242 | output [7:0] out; | |
243 | output cout; | |
244 | ||
245 | `ifdef LIB | |
246 | assign {cout, out[7:0]} = ({1'b0, in0[7:0]} + {1'b0, in1[7:0]} + {{8{1'b0}}, cin}); | |
247 | `endif | |
248 | ||
249 | endmodule | |
250 | module cl_dp1lvt_cmpr16_8x ( | |
251 | in0, | |
252 | in1, | |
253 | out | |
254 | ); | |
255 | input [15:0] in0; | |
256 | input [15:0] in1; | |
257 | output out; | |
258 | ||
259 | `ifdef LIB | |
260 | assign out = (in0[15:0] == in1[15:0]); | |
261 | `endif | |
262 | ||
263 | endmodule | |
264 | module cl_dp1lvt_cmpr32_8x ( | |
265 | in0, | |
266 | in1, | |
267 | out | |
268 | ); | |
269 | input [31:0] in0; | |
270 | input [31:0] in1; | |
271 | output out; | |
272 | ||
273 | `ifdef LIB | |
274 | assign out = (in0[31:0] == in1[31:0]); | |
275 | `endif | |
276 | ||
277 | endmodule | |
278 | module cl_dp1lvt_cmpr4_8x ( | |
279 | in0, | |
280 | in1, | |
281 | out | |
282 | ); | |
283 | input [3:0] in0; | |
284 | input [3:0] in1; | |
285 | output out; | |
286 | ||
287 | `ifdef LIB | |
288 | assign out = (in0[3:0] == in1[3:0]); | |
289 | `endif | |
290 | ||
291 | endmodule | |
292 | module cl_dp1lvt_cmpr64_8x ( | |
293 | in0, | |
294 | in1, | |
295 | out | |
296 | ); | |
297 | input [63:0] in0; | |
298 | input [63:0] in1; | |
299 | output out; | |
300 | ||
301 | `ifdef LIB | |
302 | assign out = (in0[63:0] == in1[63:0]); | |
303 | `endif | |
304 | ||
305 | endmodule | |
306 | module cl_dp1lvt_cmpr8_8x ( | |
307 | in0, | |
308 | in1, | |
309 | out | |
310 | ); | |
311 | input [7:0] in0; | |
312 | input [7:0] in1; | |
313 | output out; | |
314 | ||
315 | `ifdef LIB | |
316 | assign out = (in0[7:0] == in1[7:0]); | |
317 | `endif | |
318 | ||
319 | endmodule | |
320 | ||
321 | module cl_dp1lvt_prty16_8x ( | |
322 | in, | |
323 | out | |
324 | ); | |
325 | input [15:0] in; | |
326 | output out; | |
327 | ||
328 | ||
329 | `ifdef LIB | |
330 | assign out = ^in[15:0]; | |
331 | `endif | |
332 | ||
333 | endmodule | |
334 | module cl_dp1lvt_prty32_8x ( | |
335 | in, | |
336 | out | |
337 | ); | |
338 | input [31:0] in; | |
339 | output out; | |
340 | ||
341 | `ifdef LIB | |
342 | assign out = ^in[31:0]; | |
343 | `endif | |
344 | ||
345 | endmodule | |
346 | module cl_dp1lvt_prty4_8x ( | |
347 | in, | |
348 | out | |
349 | ); | |
350 | input [3:0] in; | |
351 | output out; | |
352 | ||
353 | `ifdef LIB | |
354 | assign out = ^in[3:0]; | |
355 | `endif | |
356 | ||
357 | endmodule | |
358 | module cl_dp1lvt_prty8_8x ( | |
359 | in, | |
360 | out | |
361 | ); | |
362 | input [7:0] in; | |
363 | output out; | |
364 | ||
365 | `ifdef LIB | |
366 | assign out = ^in[7:0]; | |
367 | `endif | |
368 | ||
369 | endmodule | |
370 | ||
371 | module cl_dp1lvt_aomux2_1x ( | |
372 | in0, | |
373 | in1, | |
374 | sel0, | |
375 | sel1, | |
376 | out | |
377 | ); | |
378 | input in0; | |
379 | input in1; | |
380 | input sel0; | |
381 | input sel1; | |
382 | output out; | |
383 | ||
384 | `ifdef LIB | |
385 | assign out = ((sel0 & in0) | | |
386 | (sel1 & in1)); | |
387 | `endif | |
388 | ||
389 | ||
390 | endmodule | |
391 | module cl_dp1lvt_aomux2_2x ( | |
392 | in0, | |
393 | in1, | |
394 | sel0, | |
395 | sel1, | |
396 | out | |
397 | ); | |
398 | input in0; | |
399 | input in1; | |
400 | input sel0; | |
401 | input sel1; | |
402 | output out; | |
403 | ||
404 | `ifdef LIB | |
405 | assign out = ((sel0 & in0) | | |
406 | (sel1 & in1)); | |
407 | `endif | |
408 | ||
409 | ||
410 | endmodule | |
411 | module cl_dp1lvt_aomux2_4x ( | |
412 | in0, | |
413 | in1, | |
414 | sel0, | |
415 | sel1, | |
416 | out | |
417 | ); | |
418 | input in0; | |
419 | input in1; | |
420 | input sel0; | |
421 | input sel1; | |
422 | output out; | |
423 | ||
424 | `ifdef LIB | |
425 | assign out = ((sel0 & in0) | | |
426 | (sel1 & in1)); | |
427 | `endif | |
428 | ||
429 | ||
430 | endmodule | |
431 | module cl_dp1lvt_aomux2_6x ( | |
432 | in0, | |
433 | in1, | |
434 | sel0, | |
435 | sel1, | |
436 | out | |
437 | ); | |
438 | input in0; | |
439 | input in1; | |
440 | input sel0; | |
441 | input sel1; | |
442 | output out; | |
443 | ||
444 | `ifdef LIB | |
445 | assign out = ((sel0 & in0) | | |
446 | (sel1 & in1)); | |
447 | `endif | |
448 | ||
449 | ||
450 | endmodule | |
451 | module cl_dp1lvt_aomux2_8x ( | |
452 | in0, | |
453 | in1, | |
454 | sel0, | |
455 | sel1, | |
456 | out | |
457 | ); | |
458 | input in0; | |
459 | input in1; | |
460 | input sel0; | |
461 | input sel1; | |
462 | output out; | |
463 | ||
464 | `ifdef LIB | |
465 | assign out = ((sel0 & in0) | | |
466 | (sel1 & in1)); | |
467 | `endif | |
468 | ||
469 | ||
470 | endmodule | |
471 | ||
472 | module cl_dp1lvt_aomux3_1x ( | |
473 | in0, | |
474 | in1, | |
475 | in2, | |
476 | sel0, | |
477 | sel1, | |
478 | sel2, | |
479 | out | |
480 | ); | |
481 | input in0; | |
482 | input in1; | |
483 | input in2; | |
484 | input sel0; | |
485 | input sel1; | |
486 | input sel2; | |
487 | output out; | |
488 | ||
489 | `ifdef LIB | |
490 | assign out = ((sel0 & in0) | | |
491 | (sel1 & in1) | | |
492 | (sel2 & in2)); | |
493 | `endif | |
494 | ||
495 | endmodule | |
496 | module cl_dp1lvt_aomux3_2x ( | |
497 | in0, | |
498 | in1, | |
499 | in2, | |
500 | sel0, | |
501 | sel1, | |
502 | sel2, | |
503 | out | |
504 | ); | |
505 | input in0; | |
506 | input in1; | |
507 | input in2; | |
508 | input sel0; | |
509 | input sel1; | |
510 | input sel2; | |
511 | output out; | |
512 | ||
513 | `ifdef LIB | |
514 | assign out = ((sel0 & in0) | | |
515 | (sel1 & in1) | | |
516 | (sel2 & in2)); | |
517 | `endif | |
518 | ||
519 | endmodule | |
520 | module cl_dp1lvt_aomux3_4x ( | |
521 | in0, | |
522 | in1, | |
523 | in2, | |
524 | sel0, | |
525 | sel1, | |
526 | sel2, | |
527 | out | |
528 | ); | |
529 | input in0; | |
530 | input in1; | |
531 | input in2; | |
532 | input sel0; | |
533 | input sel1; | |
534 | input sel2; | |
535 | output out; | |
536 | ||
537 | `ifdef LIB | |
538 | assign out = ((sel0 & in0) | | |
539 | (sel1 & in1) | | |
540 | (sel2 & in2)); | |
541 | `endif | |
542 | ||
543 | endmodule | |
544 | module cl_dp1lvt_aomux3_6x ( | |
545 | in0, | |
546 | in1, | |
547 | in2, | |
548 | sel0, | |
549 | sel1, | |
550 | sel2, | |
551 | out | |
552 | ); | |
553 | input in0; | |
554 | input in1; | |
555 | input in2; | |
556 | input sel0; | |
557 | input sel1; | |
558 | input sel2; | |
559 | output out; | |
560 | ||
561 | `ifdef LIB | |
562 | assign out = ((sel0 & in0) | | |
563 | (sel1 & in1) | | |
564 | (sel2 & in2)); | |
565 | `endif | |
566 | ||
567 | endmodule | |
568 | module cl_dp1lvt_aomux3_8x ( | |
569 | in0, | |
570 | in1, | |
571 | in2, | |
572 | sel0, | |
573 | sel1, | |
574 | sel2, | |
575 | out | |
576 | ); | |
577 | input in0; | |
578 | input in1; | |
579 | input in2; | |
580 | input sel0; | |
581 | input sel1; | |
582 | input sel2; | |
583 | output out; | |
584 | ||
585 | `ifdef LIB | |
586 | assign out = ((sel0 & in0) | | |
587 | (sel1 & in1) | | |
588 | (sel2 & in2)); | |
589 | `endif | |
590 | ||
591 | endmodule | |
592 | ||
593 | module cl_dp1lvt_aomux4_1x ( | |
594 | in0, | |
595 | in1, | |
596 | in2, | |
597 | in3, | |
598 | sel0, | |
599 | sel1, | |
600 | sel2, | |
601 | sel3, | |
602 | out | |
603 | ); | |
604 | input in0; | |
605 | input in1; | |
606 | input in2; | |
607 | input in3; | |
608 | input sel0; | |
609 | input sel1; | |
610 | input sel2; | |
611 | input sel3; | |
612 | output out; | |
613 | ||
614 | `ifdef LIB | |
615 | assign out = ((sel0 & in0) | | |
616 | (sel1 & in1) | | |
617 | (sel2 & in2) | | |
618 | (sel3 & in3)); | |
619 | `endif | |
620 | ||
621 | endmodule | |
622 | module cl_dp1lvt_aomux4_2x ( | |
623 | in0, | |
624 | in1, | |
625 | in2, | |
626 | in3, | |
627 | sel0, | |
628 | sel1, | |
629 | sel2, | |
630 | sel3, | |
631 | out | |
632 | ); | |
633 | input in0; | |
634 | input in1; | |
635 | input in2; | |
636 | input in3; | |
637 | input sel0; | |
638 | input sel1; | |
639 | input sel2; | |
640 | input sel3; | |
641 | output out; | |
642 | ||
643 | `ifdef LIB | |
644 | assign out = ((sel0 & in0) | | |
645 | (sel1 & in1) | | |
646 | (sel2 & in2) | | |
647 | (sel3 & in3)); | |
648 | `endif | |
649 | ||
650 | endmodule | |
651 | module cl_dp1lvt_aomux4_4x ( | |
652 | in0, | |
653 | in1, | |
654 | in2, | |
655 | in3, | |
656 | sel0, | |
657 | sel1, | |
658 | sel2, | |
659 | sel3, | |
660 | out | |
661 | ); | |
662 | input in0; | |
663 | input in1; | |
664 | input in2; | |
665 | input in3; | |
666 | input sel0; | |
667 | input sel1; | |
668 | input sel2; | |
669 | input sel3; | |
670 | output out; | |
671 | ||
672 | `ifdef LIB | |
673 | assign out = ((sel0 & in0) | | |
674 | (sel1 & in1) | | |
675 | (sel2 & in2) | | |
676 | (sel3 & in3)); | |
677 | `endif | |
678 | ||
679 | endmodule | |
680 | module cl_dp1lvt_aomux4_6x ( | |
681 | in0, | |
682 | in1, | |
683 | in2, | |
684 | in3, | |
685 | sel0, | |
686 | sel1, | |
687 | sel2, | |
688 | sel3, | |
689 | out | |
690 | ); | |
691 | input in0; | |
692 | input in1; | |
693 | input in2; | |
694 | input in3; | |
695 | input sel0; | |
696 | input sel1; | |
697 | input sel2; | |
698 | input sel3; | |
699 | output out; | |
700 | ||
701 | `ifdef LIB | |
702 | assign out = ((sel0 & in0) | | |
703 | (sel1 & in1) | | |
704 | (sel2 & in2) | | |
705 | (sel3 & in3)); | |
706 | `endif | |
707 | ||
708 | endmodule | |
709 | module cl_dp1lvt_aomux4_8x ( | |
710 | in0, | |
711 | in1, | |
712 | in2, | |
713 | in3, | |
714 | sel0, | |
715 | sel1, | |
716 | sel2, | |
717 | sel3, | |
718 | out | |
719 | ); | |
720 | input in0; | |
721 | input in1; | |
722 | input in2; | |
723 | input in3; | |
724 | input sel0; | |
725 | input sel1; | |
726 | input sel2; | |
727 | input sel3; | |
728 | output out; | |
729 | ||
730 | `ifdef LIB | |
731 | assign out = ((sel0 & in0) | | |
732 | (sel1 & in1) | | |
733 | (sel2 & in2) | | |
734 | (sel3 & in3)); | |
735 | `endif | |
736 | ||
737 | endmodule | |
738 | ||
739 | module cl_dp1lvt_aomux5_1x ( | |
740 | in0, | |
741 | in1, | |
742 | in2, | |
743 | in3, | |
744 | in4, | |
745 | sel0, | |
746 | sel1, | |
747 | sel2, | |
748 | sel3, | |
749 | sel4, | |
750 | out | |
751 | ); | |
752 | input in0; | |
753 | input in1; | |
754 | input in2; | |
755 | input in3; | |
756 | input in4; | |
757 | input sel0; | |
758 | input sel1; | |
759 | input sel2; | |
760 | input sel3; | |
761 | input sel4; | |
762 | output out; | |
763 | ||
764 | `ifdef LIB | |
765 | assign out = ((sel0 & in0) | | |
766 | (sel1 & in1) | | |
767 | (sel2 & in2) | | |
768 | (sel3 & in3) | | |
769 | (sel4 & in4)); | |
770 | `endif | |
771 | ||
772 | endmodule | |
773 | module cl_dp1lvt_aomux5_2x ( | |
774 | in0, | |
775 | in1, | |
776 | in2, | |
777 | in3, | |
778 | in4, | |
779 | sel0, | |
780 | sel1, | |
781 | sel2, | |
782 | sel3, | |
783 | sel4, | |
784 | out | |
785 | ); | |
786 | input in0; | |
787 | input in1; | |
788 | input in2; | |
789 | input in3; | |
790 | input in4; | |
791 | input sel0; | |
792 | input sel1; | |
793 | input sel2; | |
794 | input sel3; | |
795 | input sel4; | |
796 | output out; | |
797 | ||
798 | `ifdef LIB | |
799 | assign out = ((sel0 & in0) | | |
800 | (sel1 & in1) | | |
801 | (sel2 & in2) | | |
802 | (sel3 & in3) | | |
803 | (sel4 & in4)); | |
804 | `endif | |
805 | ||
806 | endmodule | |
807 | module cl_dp1lvt_aomux5_4x ( | |
808 | in0, | |
809 | in1, | |
810 | in2, | |
811 | in3, | |
812 | in4, | |
813 | sel0, | |
814 | sel1, | |
815 | sel2, | |
816 | sel3, | |
817 | sel4, | |
818 | out | |
819 | ); | |
820 | input in0; | |
821 | input in1; | |
822 | input in2; | |
823 | input in3; | |
824 | input in4; | |
825 | input sel0; | |
826 | input sel1; | |
827 | input sel2; | |
828 | input sel3; | |
829 | input sel4; | |
830 | output out; | |
831 | ||
832 | `ifdef LIB | |
833 | assign out = ((sel0 & in0) | | |
834 | (sel1 & in1) | | |
835 | (sel2 & in2) | | |
836 | (sel3 & in3) | | |
837 | (sel4 & in4)); | |
838 | `endif | |
839 | ||
840 | endmodule | |
841 | module cl_dp1lvt_aomux5_6x ( | |
842 | in0, | |
843 | in1, | |
844 | in2, | |
845 | in3, | |
846 | in4, | |
847 | sel0, | |
848 | sel1, | |
849 | sel2, | |
850 | sel3, | |
851 | sel4, | |
852 | out | |
853 | ); | |
854 | input in0; | |
855 | input in1; | |
856 | input in2; | |
857 | input in3; | |
858 | input in4; | |
859 | input sel0; | |
860 | input sel1; | |
861 | input sel2; | |
862 | input sel3; | |
863 | input sel4; | |
864 | output out; | |
865 | ||
866 | `ifdef LIB | |
867 | assign out = ((sel0 & in0) | | |
868 | (sel1 & in1) | | |
869 | (sel2 & in2) | | |
870 | (sel3 & in3) | | |
871 | (sel4 & in4)); | |
872 | `endif | |
873 | ||
874 | endmodule | |
875 | module cl_dp1lvt_aomux5_8x ( | |
876 | in0, | |
877 | in1, | |
878 | in2, | |
879 | in3, | |
880 | in4, | |
881 | sel0, | |
882 | sel1, | |
883 | sel2, | |
884 | sel3, | |
885 | sel4, | |
886 | out | |
887 | ); | |
888 | input in0; | |
889 | input in1; | |
890 | input in2; | |
891 | input in3; | |
892 | input in4; | |
893 | input sel0; | |
894 | input sel1; | |
895 | input sel2; | |
896 | input sel3; | |
897 | input sel4; | |
898 | output out; | |
899 | ||
900 | `ifdef LIB | |
901 | assign out = ((sel0 & in0) | | |
902 | (sel1 & in1) | | |
903 | (sel2 & in2) | | |
904 | (sel3 & in3) | | |
905 | (sel4 & in4)); | |
906 | `endif | |
907 | ||
908 | endmodule | |
909 | ||
910 | module cl_dp1lvt_aomux6_1x ( | |
911 | in0, | |
912 | in1, | |
913 | in2, | |
914 | in3, | |
915 | in4, | |
916 | in5, | |
917 | sel0, | |
918 | sel1, | |
919 | sel2, | |
920 | sel3, | |
921 | sel4, | |
922 | sel5, | |
923 | out | |
924 | ); | |
925 | input in0; | |
926 | input in1; | |
927 | input in2; | |
928 | input in3; | |
929 | input in4; | |
930 | input in5; | |
931 | input sel0; | |
932 | input sel1; | |
933 | input sel2; | |
934 | input sel3; | |
935 | input sel4; | |
936 | input sel5; | |
937 | output out; | |
938 | ||
939 | `ifdef LIB | |
940 | assign out = ((sel0 & in0) | | |
941 | (sel1 & in1) | | |
942 | (sel2 & in2) | | |
943 | (sel3 & in3) | | |
944 | (sel4 & in4) | | |
945 | (sel5 & in5)); | |
946 | `endif | |
947 | ||
948 | endmodule | |
949 | module cl_dp1lvt_aomux6_2x ( | |
950 | in0, | |
951 | in1, | |
952 | in2, | |
953 | in3, | |
954 | in4, | |
955 | in5, | |
956 | sel0, | |
957 | sel1, | |
958 | sel2, | |
959 | sel3, | |
960 | sel4, | |
961 | sel5, | |
962 | out | |
963 | ); | |
964 | input in0; | |
965 | input in1; | |
966 | input in2; | |
967 | input in3; | |
968 | input in4; | |
969 | input in5; | |
970 | input sel0; | |
971 | input sel1; | |
972 | input sel2; | |
973 | input sel3; | |
974 | input sel4; | |
975 | input sel5; | |
976 | output out; | |
977 | ||
978 | `ifdef LIB | |
979 | assign out = ((sel0 & in0) | | |
980 | (sel1 & in1) | | |
981 | (sel2 & in2) | | |
982 | (sel3 & in3) | | |
983 | (sel4 & in4) | | |
984 | (sel5 & in5)); | |
985 | `endif | |
986 | ||
987 | endmodule | |
988 | module cl_dp1lvt_aomux6_4x ( | |
989 | in0, | |
990 | in1, | |
991 | in2, | |
992 | in3, | |
993 | in4, | |
994 | in5, | |
995 | sel0, | |
996 | sel1, | |
997 | sel2, | |
998 | sel3, | |
999 | sel4, | |
1000 | sel5, | |
1001 | out | |
1002 | ); | |
1003 | input in0; | |
1004 | input in1; | |
1005 | input in2; | |
1006 | input in3; | |
1007 | input in4; | |
1008 | input in5; | |
1009 | input sel0; | |
1010 | input sel1; | |
1011 | input sel2; | |
1012 | input sel3; | |
1013 | input sel4; | |
1014 | input sel5; | |
1015 | output out; | |
1016 | ||
1017 | `ifdef LIB | |
1018 | assign out = ((sel0 & in0) | | |
1019 | (sel1 & in1) | | |
1020 | (sel2 & in2) | | |
1021 | (sel3 & in3) | | |
1022 | (sel4 & in4) | | |
1023 | (sel5 & in5)); | |
1024 | `endif | |
1025 | ||
1026 | endmodule | |
1027 | module cl_dp1lvt_aomux6_6x ( | |
1028 | in0, | |
1029 | in1, | |
1030 | in2, | |
1031 | in3, | |
1032 | in4, | |
1033 | in5, | |
1034 | sel0, | |
1035 | sel1, | |
1036 | sel2, | |
1037 | sel3, | |
1038 | sel4, | |
1039 | sel5, | |
1040 | out | |
1041 | ); | |
1042 | input in0; | |
1043 | input in1; | |
1044 | input in2; | |
1045 | input in3; | |
1046 | input in4; | |
1047 | input in5; | |
1048 | input sel0; | |
1049 | input sel1; | |
1050 | input sel2; | |
1051 | input sel3; | |
1052 | input sel4; | |
1053 | input sel5; | |
1054 | output out; | |
1055 | ||
1056 | `ifdef LIB | |
1057 | assign out = ((sel0 & in0) | | |
1058 | (sel1 & in1) | | |
1059 | (sel2 & in2) | | |
1060 | (sel3 & in3) | | |
1061 | (sel4 & in4) | | |
1062 | (sel5 & in5)); | |
1063 | `endif | |
1064 | ||
1065 | endmodule | |
1066 | module cl_dp1lvt_aomux6_8x ( | |
1067 | in0, | |
1068 | in1, | |
1069 | in2, | |
1070 | in3, | |
1071 | in4, | |
1072 | in5, | |
1073 | sel0, | |
1074 | sel1, | |
1075 | sel2, | |
1076 | sel3, | |
1077 | sel4, | |
1078 | sel5, | |
1079 | out | |
1080 | ); | |
1081 | input in0; | |
1082 | input in1; | |
1083 | input in2; | |
1084 | input in3; | |
1085 | input in4; | |
1086 | input in5; | |
1087 | input sel0; | |
1088 | input sel1; | |
1089 | input sel2; | |
1090 | input sel3; | |
1091 | input sel4; | |
1092 | input sel5; | |
1093 | output out; | |
1094 | ||
1095 | `ifdef LIB | |
1096 | assign out = ((sel0 & in0) | | |
1097 | (sel1 & in1) | | |
1098 | (sel2 & in2) | | |
1099 | (sel3 & in3) | | |
1100 | (sel4 & in4) | | |
1101 | (sel5 & in5)); | |
1102 | `endif | |
1103 | ||
1104 | endmodule | |
1105 | ||
1106 | module cl_dp1lvt_aomux7_1x ( | |
1107 | in0, | |
1108 | in1, | |
1109 | in2, | |
1110 | in3, | |
1111 | in4, | |
1112 | in5, | |
1113 | in6, | |
1114 | sel0, | |
1115 | sel1, | |
1116 | sel2, | |
1117 | sel3, | |
1118 | sel4, | |
1119 | sel5, | |
1120 | sel6, | |
1121 | out | |
1122 | ); | |
1123 | input in0; | |
1124 | input in1; | |
1125 | input in2; | |
1126 | input in3; | |
1127 | input in4; | |
1128 | input in5; | |
1129 | input in6; | |
1130 | input sel0; | |
1131 | input sel1; | |
1132 | input sel2; | |
1133 | input sel3; | |
1134 | input sel4; | |
1135 | input sel5; | |
1136 | input sel6; | |
1137 | output out; | |
1138 | ||
1139 | `ifdef LIB | |
1140 | assign out = ((sel0 & in0) | | |
1141 | (sel1 & in1) | | |
1142 | (sel2 & in2) | | |
1143 | (sel3 & in3) | | |
1144 | (sel4 & in4) | | |
1145 | (sel5 & in5) | | |
1146 | (sel6 & in6)); | |
1147 | `endif | |
1148 | ||
1149 | endmodule | |
1150 | module cl_dp1lvt_aomux7_2x ( | |
1151 | in0, | |
1152 | in1, | |
1153 | in2, | |
1154 | in3, | |
1155 | in4, | |
1156 | in5, | |
1157 | in6, | |
1158 | sel0, | |
1159 | sel1, | |
1160 | sel2, | |
1161 | sel3, | |
1162 | sel4, | |
1163 | sel5, | |
1164 | sel6, | |
1165 | out | |
1166 | ); | |
1167 | input in0; | |
1168 | input in1; | |
1169 | input in2; | |
1170 | input in3; | |
1171 | input in4; | |
1172 | input in5; | |
1173 | input in6; | |
1174 | input sel0; | |
1175 | input sel1; | |
1176 | input sel2; | |
1177 | input sel3; | |
1178 | input sel4; | |
1179 | input sel5; | |
1180 | input sel6; | |
1181 | output out; | |
1182 | ||
1183 | `ifdef LIB | |
1184 | assign out = ((sel0 & in0) | | |
1185 | (sel1 & in1) | | |
1186 | (sel2 & in2) | | |
1187 | (sel3 & in3) | | |
1188 | (sel4 & in4) | | |
1189 | (sel5 & in5) | | |
1190 | (sel6 & in6)); | |
1191 | `endif | |
1192 | ||
1193 | endmodule | |
1194 | module cl_dp1lvt_aomux7_4x ( | |
1195 | in0, | |
1196 | in1, | |
1197 | in2, | |
1198 | in3, | |
1199 | in4, | |
1200 | in5, | |
1201 | in6, | |
1202 | sel0, | |
1203 | sel1, | |
1204 | sel2, | |
1205 | sel3, | |
1206 | sel4, | |
1207 | sel5, | |
1208 | sel6, | |
1209 | out | |
1210 | ); | |
1211 | input in0; | |
1212 | input in1; | |
1213 | input in2; | |
1214 | input in3; | |
1215 | input in4; | |
1216 | input in5; | |
1217 | input in6; | |
1218 | input sel0; | |
1219 | input sel1; | |
1220 | input sel2; | |
1221 | input sel3; | |
1222 | input sel4; | |
1223 | input sel5; | |
1224 | input sel6; | |
1225 | output out; | |
1226 | ||
1227 | `ifdef LIB | |
1228 | assign out = ((sel0 & in0) | | |
1229 | (sel1 & in1) | | |
1230 | (sel2 & in2) | | |
1231 | (sel3 & in3) | | |
1232 | (sel4 & in4) | | |
1233 | (sel5 & in5) | | |
1234 | (sel6 & in6)); | |
1235 | `endif | |
1236 | ||
1237 | endmodule | |
1238 | module cl_dp1lvt_aomux7_6x ( | |
1239 | in0, | |
1240 | in1, | |
1241 | in2, | |
1242 | in3, | |
1243 | in4, | |
1244 | in5, | |
1245 | in6, | |
1246 | sel0, | |
1247 | sel1, | |
1248 | sel2, | |
1249 | sel3, | |
1250 | sel4, | |
1251 | sel5, | |
1252 | sel6, | |
1253 | out | |
1254 | ); | |
1255 | input in0; | |
1256 | input in1; | |
1257 | input in2; | |
1258 | input in3; | |
1259 | input in4; | |
1260 | input in5; | |
1261 | input in6; | |
1262 | input sel0; | |
1263 | input sel1; | |
1264 | input sel2; | |
1265 | input sel3; | |
1266 | input sel4; | |
1267 | input sel5; | |
1268 | input sel6; | |
1269 | output out; | |
1270 | ||
1271 | `ifdef LIB | |
1272 | assign out = ((sel0 & in0) | | |
1273 | (sel1 & in1) | | |
1274 | (sel2 & in2) | | |
1275 | (sel3 & in3) | | |
1276 | (sel4 & in4) | | |
1277 | (sel5 & in5) | | |
1278 | (sel6 & in6)); | |
1279 | `endif | |
1280 | ||
1281 | endmodule | |
1282 | module cl_dp1lvt_aomux7_8x ( | |
1283 | in0, | |
1284 | in1, | |
1285 | in2, | |
1286 | in3, | |
1287 | in4, | |
1288 | in5, | |
1289 | in6, | |
1290 | sel0, | |
1291 | sel1, | |
1292 | sel2, | |
1293 | sel3, | |
1294 | sel4, | |
1295 | sel5, | |
1296 | sel6, | |
1297 | out | |
1298 | ); | |
1299 | input in0; | |
1300 | input in1; | |
1301 | input in2; | |
1302 | input in3; | |
1303 | input in4; | |
1304 | input in5; | |
1305 | input in6; | |
1306 | input sel0; | |
1307 | input sel1; | |
1308 | input sel2; | |
1309 | input sel3; | |
1310 | input sel4; | |
1311 | input sel5; | |
1312 | input sel6; | |
1313 | output out; | |
1314 | ||
1315 | `ifdef LIB | |
1316 | assign out = ((sel0 & in0) | | |
1317 | (sel1 & in1) | | |
1318 | (sel2 & in2) | | |
1319 | (sel3 & in3) | | |
1320 | (sel4 & in4) | | |
1321 | (sel5 & in5) | | |
1322 | (sel6 & in6)); | |
1323 | `endif | |
1324 | ||
1325 | endmodule | |
1326 | ||
1327 | module cl_dp1lvt_aomux8_1x ( | |
1328 | in0, | |
1329 | in1, | |
1330 | in2, | |
1331 | in3, | |
1332 | in4, | |
1333 | in5, | |
1334 | in6, | |
1335 | in7, | |
1336 | sel0, | |
1337 | sel1, | |
1338 | sel2, | |
1339 | sel3, | |
1340 | sel4, | |
1341 | sel5, | |
1342 | sel6, | |
1343 | sel7, | |
1344 | out | |
1345 | ); | |
1346 | input in0; | |
1347 | input in1; | |
1348 | input in2; | |
1349 | input in3; | |
1350 | input in4; | |
1351 | input in5; | |
1352 | input in6; | |
1353 | input in7; | |
1354 | input sel0; | |
1355 | input sel1; | |
1356 | input sel2; | |
1357 | input sel3; | |
1358 | input sel4; | |
1359 | input sel5; | |
1360 | input sel6; | |
1361 | input sel7; | |
1362 | output out; | |
1363 | ||
1364 | `ifdef LIB | |
1365 | assign out = ((sel0 & in0) | | |
1366 | (sel1 & in1) | | |
1367 | (sel2 & in2) | | |
1368 | (sel3 & in3) | | |
1369 | (sel4 & in4) | | |
1370 | (sel5 & in5) | | |
1371 | (sel6 & in6) | | |
1372 | (sel7 & in7)); | |
1373 | `endif | |
1374 | ||
1375 | ||
1376 | endmodule | |
1377 | module cl_dp1lvt_aomux8_2x ( | |
1378 | in0, | |
1379 | in1, | |
1380 | in2, | |
1381 | in3, | |
1382 | in4, | |
1383 | in5, | |
1384 | in6, | |
1385 | in7, | |
1386 | sel0, | |
1387 | sel1, | |
1388 | sel2, | |
1389 | sel3, | |
1390 | sel4, | |
1391 | sel5, | |
1392 | sel6, | |
1393 | sel7, | |
1394 | out | |
1395 | ); | |
1396 | input in0; | |
1397 | input in1; | |
1398 | input in2; | |
1399 | input in3; | |
1400 | input in4; | |
1401 | input in5; | |
1402 | input in6; | |
1403 | input in7; | |
1404 | input sel0; | |
1405 | input sel1; | |
1406 | input sel2; | |
1407 | input sel3; | |
1408 | input sel4; | |
1409 | input sel5; | |
1410 | input sel6; | |
1411 | input sel7; | |
1412 | output out; | |
1413 | ||
1414 | `ifdef LIB | |
1415 | assign out = ((sel0 & in0) | | |
1416 | (sel1 & in1) | | |
1417 | (sel2 & in2) | | |
1418 | (sel3 & in3) | | |
1419 | (sel4 & in4) | | |
1420 | (sel5 & in5) | | |
1421 | (sel6 & in6) | | |
1422 | (sel7 & in7)); | |
1423 | `endif | |
1424 | ||
1425 | ||
1426 | endmodule | |
1427 | module cl_dp1lvt_aomux8_4x ( | |
1428 | in0, | |
1429 | in1, | |
1430 | in2, | |
1431 | in3, | |
1432 | in4, | |
1433 | in5, | |
1434 | in6, | |
1435 | in7, | |
1436 | sel0, | |
1437 | sel1, | |
1438 | sel2, | |
1439 | sel3, | |
1440 | sel4, | |
1441 | sel5, | |
1442 | sel6, | |
1443 | sel7, | |
1444 | out | |
1445 | ); | |
1446 | input in0; | |
1447 | input in1; | |
1448 | input in2; | |
1449 | input in3; | |
1450 | input in4; | |
1451 | input in5; | |
1452 | input in6; | |
1453 | input in7; | |
1454 | input sel0; | |
1455 | input sel1; | |
1456 | input sel2; | |
1457 | input sel3; | |
1458 | input sel4; | |
1459 | input sel5; | |
1460 | input sel6; | |
1461 | input sel7; | |
1462 | output out; | |
1463 | ||
1464 | `ifdef LIB | |
1465 | assign out = ((sel0 & in0) | | |
1466 | (sel1 & in1) | | |
1467 | (sel2 & in2) | | |
1468 | (sel3 & in3) | | |
1469 | (sel4 & in4) | | |
1470 | (sel5 & in5) | | |
1471 | (sel6 & in6) | | |
1472 | (sel7 & in7)); | |
1473 | `endif | |
1474 | ||
1475 | ||
1476 | endmodule | |
1477 | module cl_dp1lvt_aomux8_6x ( | |
1478 | in0, | |
1479 | in1, | |
1480 | in2, | |
1481 | in3, | |
1482 | in4, | |
1483 | in5, | |
1484 | in6, | |
1485 | in7, | |
1486 | sel0, | |
1487 | sel1, | |
1488 | sel2, | |
1489 | sel3, | |
1490 | sel4, | |
1491 | sel5, | |
1492 | sel6, | |
1493 | sel7, | |
1494 | out | |
1495 | ); | |
1496 | input in0; | |
1497 | input in1; | |
1498 | input in2; | |
1499 | input in3; | |
1500 | input in4; | |
1501 | input in5; | |
1502 | input in6; | |
1503 | input in7; | |
1504 | input sel0; | |
1505 | input sel1; | |
1506 | input sel2; | |
1507 | input sel3; | |
1508 | input sel4; | |
1509 | input sel5; | |
1510 | input sel6; | |
1511 | input sel7; | |
1512 | output out; | |
1513 | ||
1514 | `ifdef LIB | |
1515 | assign out = ((sel0 & in0) | | |
1516 | (sel1 & in1) | | |
1517 | (sel2 & in2) | | |
1518 | (sel3 & in3) | | |
1519 | (sel4 & in4) | | |
1520 | (sel5 & in5) | | |
1521 | (sel6 & in6) | | |
1522 | (sel7 & in7)); | |
1523 | `endif | |
1524 | ||
1525 | ||
1526 | endmodule | |
1527 | module cl_dp1lvt_aomux8_8x ( | |
1528 | in0, | |
1529 | in1, | |
1530 | in2, | |
1531 | in3, | |
1532 | in4, | |
1533 | in5, | |
1534 | in6, | |
1535 | in7, | |
1536 | sel0, | |
1537 | sel1, | |
1538 | sel2, | |
1539 | sel3, | |
1540 | sel4, | |
1541 | sel5, | |
1542 | sel6, | |
1543 | sel7, | |
1544 | out | |
1545 | ); | |
1546 | input in0; | |
1547 | input in1; | |
1548 | input in2; | |
1549 | input in3; | |
1550 | input in4; | |
1551 | input in5; | |
1552 | input in6; | |
1553 | input in7; | |
1554 | input sel0; | |
1555 | input sel1; | |
1556 | input sel2; | |
1557 | input sel3; | |
1558 | input sel4; | |
1559 | input sel5; | |
1560 | input sel6; | |
1561 | input sel7; | |
1562 | output out; | |
1563 | ||
1564 | `ifdef LIB | |
1565 | assign out = ((sel0 & in0) | | |
1566 | (sel1 & in1) | | |
1567 | (sel2 & in2) | | |
1568 | (sel3 & in3) | | |
1569 | (sel4 & in4) | | |
1570 | (sel5 & in5) | | |
1571 | (sel6 & in6) | | |
1572 | (sel7 & in7)); | |
1573 | `endif | |
1574 | ||
1575 | ||
1576 | endmodule | |
1577 | module cl_dp1lvt_incr32_8x ( | |
1578 | cin, | |
1579 | in0, | |
1580 | out, | |
1581 | cout | |
1582 | ); | |
1583 | input cin; | |
1584 | input [31:0] in0; | |
1585 | output [31:0] out; | |
1586 | output cout; | |
1587 | ||
1588 | `ifdef LIB | |
1589 | assign {cout, out[31:0]} = {1'b0, in0[31:0]} + {32'b0, cin}; | |
1590 | `endif | |
1591 | ||
1592 | endmodule | |
1593 | module cl_dp1lvt_incr48_8x ( | |
1594 | cin, | |
1595 | in0, | |
1596 | out, | |
1597 | cout | |
1598 | ); | |
1599 | input cin; | |
1600 | input [47:0] in0; | |
1601 | output [47:0] out; | |
1602 | output cout; | |
1603 | ||
1604 | `ifdef LIB | |
1605 | assign {cout, out[47:0]} = {1'b0, in0[47:0]} + {48'b0, cin}; | |
1606 | `endif | |
1607 | ||
1608 | endmodule | |
1609 | module cl_dp1lvt_incr64_8x ( | |
1610 | cin, | |
1611 | in0, | |
1612 | out, | |
1613 | cout | |
1614 | ); | |
1615 | input cin; | |
1616 | input [63:0] in0; | |
1617 | output [63:0] out; | |
1618 | output cout; | |
1619 | ||
1620 | `ifdef LIB | |
1621 | assign {cout, out[63:0]} = {1'b0, in0[63:0]} + {64'b0, cin}; | |
1622 | `endif | |
1623 | ||
1624 | endmodule |