Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / libs / cl / cl_dp1lvt / cl_dp1lvt.behV
CommitLineData
86530b38
AT
1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: cl_dp1lvt.behV
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module cl_dp1lvt_add12_fulllvt_8x (
36cin,
37in0,
38in1,
39out,
40cout
41);
42input cin;
43input [11:0] in0;
44input [11:0] in1;
45output [11:0] out;
46output cout;
47
48`ifdef LIB
49 assign {cout, out[11:0]} = ({1'b0, in0[11:0]} + {1'b0, in1[11:0]} + {{12{1'b0}}, cin});
50`endif
51
52endmodule
53
54module cl_dp1lvt_add16_fulllvt_8x (
55cin,
56in0,
57in1,
58out,
59cout
60);
61input cin;
62input [15:0] in0;
63input [15:0] in1;
64output [15:0] out;
65output cout;
66
67`ifdef LIB
68 assign {cout, out[15:0]} = ({1'b0, in0[15:0]} + {1'b0, in1[15:0]} + {{16{1'b0}}, cin});
69`endif
70
71endmodule
72module cl_dp1lvt_add4_fulllvt_8x (
73cin,
74in0,
75in1,
76out,
77cout
78);
79input cin;
80input [3:0] in0;
81input [3:0] in1;
82output [3:0] out;
83output cout;
84
85`ifdef LIB
86 assign {cout, out[3:0]} = ({1'b0, in0[3:0]} + {1'b0, in1[3:0]} + {{4{1'b0}}, cin});
87`endif
88
89endmodule
90module cl_dp1lvt_add64_fulllvt_8x (
91cin,
92in0,
93in1,
94out,
95cout
96);
97input cin;
98input [63:0] in0;
99input [63:0] in1;
100output [63:0] out;
101output cout;
102
103`ifdef LIB
104 assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin});
105`endif
106
107endmodule
108module cl_dp1lvt_add8_fulllvt_8x (
109cin,
110in0,
111in1,
112out,
113cout
114);
115input cin;
116input [7:0] in0;
117input [7:0] in1;
118output [7:0] out;
119output cout;
120
121`ifdef LIB
122 assign {cout, out[7:0]} = ({1'b0, in0[7:0]} + {1'b0, in1[7:0]} + {{8{1'b0}}, cin});
123`endif
124
125endmodule
126module cl_dp1lvt_add12_8x (
127cin,
128in0,
129in1,
130out,
131cout
132);
133input cin;
134input [11:0] in0;
135input [11:0] in1;
136output [11:0] out;
137output cout;
138
139`ifdef LIB
140 assign {cout, out[11:0]} = ({1'b0, in0[11:0]} + {1'b0, in1[11:0]} + {{12{1'b0}}, cin});
141`endif
142
143endmodule
144module cl_dp1lvt_add16_8x (
145cin,
146in0,
147in1,
148out,
149cout
150);
151input cin;
152input [15:0] in0;
153input [15:0] in1;
154output [15:0] out;
155output cout;
156
157`ifdef LIB
158 assign {cout, out[15:0]} = ({1'b0, in0[15:0]} + {1'b0, in1[15:0]} + {{16{1'b0}}, cin});
159`endif
160
161endmodule
162module cl_dp1lvt_add32_8x (
163cin,
164in0,
165in1,
166out,
167cout
168);
169input cin;
170input [31:0] in0;
171input [31:0] in1;
172output [31:0] out;
173output cout;
174
175`ifdef LIB
176 assign {cout, out[31:0]} = ({1'b0, in0[31:0]} + {1'b0, in1[31:0]} + {{32{1'b0}}, cin});
177`endif
178
179endmodule
180module cl_dp1lvt_add4_8x (
181cin,
182in0,
183in1,
184out,
185cout
186);
187input cin;
188input [3:0] in0;
189input [3:0] in1;
190output [3:0] out;
191output cout;
192
193`ifdef LIB
194 assign {cout, out[3:0]} = ({1'b0, in0[3:0]} + {1'b0, in1[3:0]} + {{4{1'b0}}, cin});
195`endif
196
197endmodule
198module cl_dp1lvt_add64_8x (
199cin,
200in0,
201in1,
202out,
203cout
204);
205input cin;
206input [63:0] in0;
207input [63:0] in1;
208output [63:0] out;
209output cout;
210
211`ifdef LIB
212 assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin});
213`endif
214
215endmodule
216
217
218module cl_dp1lvt_cmpr12_8x (
219in0,
220in1,
221out
222);
223input [11:0] in0;
224input [11:0] in1;
225output out;
226
227`ifdef LIB
228assign out = (in0[11:0] == in1[11:0]);
229`endif
230
231endmodule
232module cl_dp1lvt_add8_8x (
233cin,
234in0,
235in1,
236out,
237cout
238);
239input cin;
240input [7:0] in0;
241input [7:0] in1;
242output [7:0] out;
243output cout;
244
245`ifdef LIB
246 assign {cout, out[7:0]} = ({1'b0, in0[7:0]} + {1'b0, in1[7:0]} + {{8{1'b0}}, cin});
247`endif
248
249endmodule
250module cl_dp1lvt_cmpr16_8x (
251in0,
252in1,
253out
254);
255input [15:0] in0;
256input [15:0] in1;
257output out;
258
259`ifdef LIB
260assign out = (in0[15:0] == in1[15:0]);
261`endif
262
263endmodule
264module cl_dp1lvt_cmpr32_8x (
265in0,
266in1,
267out
268);
269input [31:0] in0;
270input [31:0] in1;
271output out;
272
273`ifdef LIB
274assign out = (in0[31:0] == in1[31:0]);
275`endif
276
277endmodule
278module cl_dp1lvt_cmpr4_8x (
279in0,
280in1,
281out
282);
283input [3:0] in0;
284input [3:0] in1;
285output out;
286
287`ifdef LIB
288assign out = (in0[3:0] == in1[3:0]);
289`endif
290
291endmodule
292module cl_dp1lvt_cmpr64_8x (
293in0,
294in1,
295out
296);
297input [63:0] in0;
298input [63:0] in1;
299output out;
300
301`ifdef LIB
302assign out = (in0[63:0] == in1[63:0]);
303`endif
304
305endmodule
306module cl_dp1lvt_cmpr8_8x (
307in0,
308in1,
309out
310);
311input [7:0] in0;
312input [7:0] in1;
313output out;
314
315`ifdef LIB
316assign out = (in0[7:0] == in1[7:0]);
317`endif
318
319endmodule
320
321module cl_dp1lvt_prty16_8x (
322in,
323out
324);
325input [15:0] in;
326output out;
327
328
329`ifdef LIB
330assign out = ^in[15:0];
331`endif
332
333endmodule
334module cl_dp1lvt_prty32_8x (
335in,
336out
337);
338input [31:0] in;
339output out;
340
341`ifdef LIB
342assign out = ^in[31:0];
343`endif
344
345endmodule
346module cl_dp1lvt_prty4_8x (
347in,
348out
349);
350input [3:0] in;
351output out;
352
353`ifdef LIB
354assign out = ^in[3:0];
355`endif
356
357endmodule
358module cl_dp1lvt_prty8_8x (
359in,
360out
361);
362input [7:0] in;
363output out;
364
365`ifdef LIB
366assign out = ^in[7:0];
367`endif
368
369endmodule
370
371module cl_dp1lvt_aomux2_1x (
372in0,
373in1,
374sel0,
375sel1,
376out
377);
378input in0;
379input in1;
380input sel0;
381input sel1;
382output out;
383
384`ifdef LIB
385assign out = ((sel0 & in0) |
386 (sel1 & in1));
387`endif
388
389
390endmodule
391module cl_dp1lvt_aomux2_2x (
392in0,
393in1,
394sel0,
395sel1,
396out
397);
398input in0;
399input in1;
400input sel0;
401input sel1;
402output out;
403
404`ifdef LIB
405assign out = ((sel0 & in0) |
406 (sel1 & in1));
407`endif
408
409
410endmodule
411module cl_dp1lvt_aomux2_4x (
412in0,
413in1,
414sel0,
415sel1,
416out
417);
418input in0;
419input in1;
420input sel0;
421input sel1;
422output out;
423
424`ifdef LIB
425assign out = ((sel0 & in0) |
426 (sel1 & in1));
427`endif
428
429
430endmodule
431module cl_dp1lvt_aomux2_6x (
432in0,
433in1,
434sel0,
435sel1,
436out
437);
438input in0;
439input in1;
440input sel0;
441input sel1;
442output out;
443
444`ifdef LIB
445assign out = ((sel0 & in0) |
446 (sel1 & in1));
447`endif
448
449
450endmodule
451module cl_dp1lvt_aomux2_8x (
452in0,
453in1,
454sel0,
455sel1,
456out
457);
458input in0;
459input in1;
460input sel0;
461input sel1;
462output out;
463
464`ifdef LIB
465assign out = ((sel0 & in0) |
466 (sel1 & in1));
467`endif
468
469
470endmodule
471
472module cl_dp1lvt_aomux3_1x (
473in0,
474in1,
475in2,
476sel0,
477sel1,
478sel2,
479out
480);
481input in0;
482input in1;
483input in2;
484input sel0;
485input sel1;
486input sel2;
487output out;
488
489`ifdef LIB
490assign out = ((sel0 & in0) |
491 (sel1 & in1) |
492 (sel2 & in2));
493`endif
494
495endmodule
496module cl_dp1lvt_aomux3_2x (
497in0,
498in1,
499in2,
500sel0,
501sel1,
502sel2,
503out
504);
505input in0;
506input in1;
507input in2;
508input sel0;
509input sel1;
510input sel2;
511output out;
512
513`ifdef LIB
514assign out = ((sel0 & in0) |
515 (sel1 & in1) |
516 (sel2 & in2));
517`endif
518
519endmodule
520module cl_dp1lvt_aomux3_4x (
521in0,
522in1,
523in2,
524sel0,
525sel1,
526sel2,
527out
528);
529input in0;
530input in1;
531input in2;
532input sel0;
533input sel1;
534input sel2;
535output out;
536
537`ifdef LIB
538assign out = ((sel0 & in0) |
539 (sel1 & in1) |
540 (sel2 & in2));
541`endif
542
543endmodule
544module cl_dp1lvt_aomux3_6x (
545in0,
546in1,
547in2,
548sel0,
549sel1,
550sel2,
551out
552);
553input in0;
554input in1;
555input in2;
556input sel0;
557input sel1;
558input sel2;
559output out;
560
561`ifdef LIB
562assign out = ((sel0 & in0) |
563 (sel1 & in1) |
564 (sel2 & in2));
565`endif
566
567endmodule
568module cl_dp1lvt_aomux3_8x (
569in0,
570in1,
571in2,
572sel0,
573sel1,
574sel2,
575out
576);
577input in0;
578input in1;
579input in2;
580input sel0;
581input sel1;
582input sel2;
583output out;
584
585`ifdef LIB
586assign out = ((sel0 & in0) |
587 (sel1 & in1) |
588 (sel2 & in2));
589`endif
590
591endmodule
592
593module cl_dp1lvt_aomux4_1x (
594in0,
595in1,
596in2,
597in3,
598sel0,
599sel1,
600sel2,
601sel3,
602out
603);
604input in0;
605input in1;
606input in2;
607input in3;
608input sel0;
609input sel1;
610input sel2;
611input sel3;
612output out;
613
614`ifdef LIB
615assign out = ((sel0 & in0) |
616 (sel1 & in1) |
617 (sel2 & in2) |
618 (sel3 & in3));
619`endif
620
621endmodule
622module cl_dp1lvt_aomux4_2x (
623in0,
624in1,
625in2,
626in3,
627sel0,
628sel1,
629sel2,
630sel3,
631out
632);
633input in0;
634input in1;
635input in2;
636input in3;
637input sel0;
638input sel1;
639input sel2;
640input sel3;
641output out;
642
643`ifdef LIB
644assign out = ((sel0 & in0) |
645 (sel1 & in1) |
646 (sel2 & in2) |
647 (sel3 & in3));
648`endif
649
650endmodule
651module cl_dp1lvt_aomux4_4x (
652in0,
653in1,
654in2,
655in3,
656sel0,
657sel1,
658sel2,
659sel3,
660out
661);
662input in0;
663input in1;
664input in2;
665input in3;
666input sel0;
667input sel1;
668input sel2;
669input sel3;
670output out;
671
672`ifdef LIB
673assign out = ((sel0 & in0) |
674 (sel1 & in1) |
675 (sel2 & in2) |
676 (sel3 & in3));
677`endif
678
679endmodule
680module cl_dp1lvt_aomux4_6x (
681in0,
682in1,
683in2,
684in3,
685sel0,
686sel1,
687sel2,
688sel3,
689out
690);
691input in0;
692input in1;
693input in2;
694input in3;
695input sel0;
696input sel1;
697input sel2;
698input sel3;
699output out;
700
701`ifdef LIB
702assign out = ((sel0 & in0) |
703 (sel1 & in1) |
704 (sel2 & in2) |
705 (sel3 & in3));
706`endif
707
708endmodule
709module cl_dp1lvt_aomux4_8x (
710in0,
711in1,
712in2,
713in3,
714sel0,
715sel1,
716sel2,
717sel3,
718out
719);
720input in0;
721input in1;
722input in2;
723input in3;
724input sel0;
725input sel1;
726input sel2;
727input sel3;
728output out;
729
730`ifdef LIB
731assign out = ((sel0 & in0) |
732 (sel1 & in1) |
733 (sel2 & in2) |
734 (sel3 & in3));
735`endif
736
737endmodule
738
739module cl_dp1lvt_aomux5_1x (
740in0,
741in1,
742in2,
743in3,
744in4,
745sel0,
746sel1,
747sel2,
748sel3,
749sel4,
750out
751);
752input in0;
753input in1;
754input in2;
755input in3;
756input in4;
757input sel0;
758input sel1;
759input sel2;
760input sel3;
761input sel4;
762output out;
763
764`ifdef LIB
765assign out = ((sel0 & in0) |
766 (sel1 & in1) |
767 (sel2 & in2) |
768 (sel3 & in3) |
769 (sel4 & in4));
770`endif
771
772endmodule
773module cl_dp1lvt_aomux5_2x (
774in0,
775in1,
776in2,
777in3,
778in4,
779sel0,
780sel1,
781sel2,
782sel3,
783sel4,
784out
785);
786input in0;
787input in1;
788input in2;
789input in3;
790input in4;
791input sel0;
792input sel1;
793input sel2;
794input sel3;
795input sel4;
796output out;
797
798`ifdef LIB
799assign out = ((sel0 & in0) |
800 (sel1 & in1) |
801 (sel2 & in2) |
802 (sel3 & in3) |
803 (sel4 & in4));
804`endif
805
806endmodule
807module cl_dp1lvt_aomux5_4x (
808in0,
809in1,
810in2,
811in3,
812in4,
813sel0,
814sel1,
815sel2,
816sel3,
817sel4,
818out
819);
820input in0;
821input in1;
822input in2;
823input in3;
824input in4;
825input sel0;
826input sel1;
827input sel2;
828input sel3;
829input sel4;
830output out;
831
832`ifdef LIB
833assign out = ((sel0 & in0) |
834 (sel1 & in1) |
835 (sel2 & in2) |
836 (sel3 & in3) |
837 (sel4 & in4));
838`endif
839
840endmodule
841module cl_dp1lvt_aomux5_6x (
842in0,
843in1,
844in2,
845in3,
846in4,
847sel0,
848sel1,
849sel2,
850sel3,
851sel4,
852out
853);
854input in0;
855input in1;
856input in2;
857input in3;
858input in4;
859input sel0;
860input sel1;
861input sel2;
862input sel3;
863input sel4;
864output out;
865
866`ifdef LIB
867assign out = ((sel0 & in0) |
868 (sel1 & in1) |
869 (sel2 & in2) |
870 (sel3 & in3) |
871 (sel4 & in4));
872`endif
873
874endmodule
875module cl_dp1lvt_aomux5_8x (
876in0,
877in1,
878in2,
879in3,
880in4,
881sel0,
882sel1,
883sel2,
884sel3,
885sel4,
886out
887);
888input in0;
889input in1;
890input in2;
891input in3;
892input in4;
893input sel0;
894input sel1;
895input sel2;
896input sel3;
897input sel4;
898output out;
899
900`ifdef LIB
901assign out = ((sel0 & in0) |
902 (sel1 & in1) |
903 (sel2 & in2) |
904 (sel3 & in3) |
905 (sel4 & in4));
906`endif
907
908endmodule
909
910module cl_dp1lvt_aomux6_1x (
911in0,
912in1,
913in2,
914in3,
915in4,
916in5,
917sel0,
918sel1,
919sel2,
920sel3,
921sel4,
922sel5,
923out
924);
925input in0;
926input in1;
927input in2;
928input in3;
929input in4;
930input in5;
931input sel0;
932input sel1;
933input sel2;
934input sel3;
935input sel4;
936input sel5;
937output out;
938
939`ifdef LIB
940assign out = ((sel0 & in0) |
941 (sel1 & in1) |
942 (sel2 & in2) |
943 (sel3 & in3) |
944 (sel4 & in4) |
945 (sel5 & in5));
946`endif
947
948endmodule
949module cl_dp1lvt_aomux6_2x (
950in0,
951in1,
952in2,
953in3,
954in4,
955in5,
956sel0,
957sel1,
958sel2,
959sel3,
960sel4,
961sel5,
962out
963);
964input in0;
965input in1;
966input in2;
967input in3;
968input in4;
969input in5;
970input sel0;
971input sel1;
972input sel2;
973input sel3;
974input sel4;
975input sel5;
976output out;
977
978`ifdef LIB
979assign out = ((sel0 & in0) |
980 (sel1 & in1) |
981 (sel2 & in2) |
982 (sel3 & in3) |
983 (sel4 & in4) |
984 (sel5 & in5));
985`endif
986
987endmodule
988module cl_dp1lvt_aomux6_4x (
989in0,
990in1,
991in2,
992in3,
993in4,
994in5,
995sel0,
996sel1,
997sel2,
998sel3,
999sel4,
1000sel5,
1001out
1002);
1003input in0;
1004input in1;
1005input in2;
1006input in3;
1007input in4;
1008input in5;
1009input sel0;
1010input sel1;
1011input sel2;
1012input sel3;
1013input sel4;
1014input sel5;
1015output out;
1016
1017`ifdef LIB
1018assign out = ((sel0 & in0) |
1019 (sel1 & in1) |
1020 (sel2 & in2) |
1021 (sel3 & in3) |
1022 (sel4 & in4) |
1023 (sel5 & in5));
1024`endif
1025
1026endmodule
1027module cl_dp1lvt_aomux6_6x (
1028in0,
1029in1,
1030in2,
1031in3,
1032in4,
1033in5,
1034sel0,
1035sel1,
1036sel2,
1037sel3,
1038sel4,
1039sel5,
1040out
1041);
1042input in0;
1043input in1;
1044input in2;
1045input in3;
1046input in4;
1047input in5;
1048input sel0;
1049input sel1;
1050input sel2;
1051input sel3;
1052input sel4;
1053input sel5;
1054output out;
1055
1056`ifdef LIB
1057assign out = ((sel0 & in0) |
1058 (sel1 & in1) |
1059 (sel2 & in2) |
1060 (sel3 & in3) |
1061 (sel4 & in4) |
1062 (sel5 & in5));
1063`endif
1064
1065endmodule
1066module cl_dp1lvt_aomux6_8x (
1067in0,
1068in1,
1069in2,
1070in3,
1071in4,
1072in5,
1073sel0,
1074sel1,
1075sel2,
1076sel3,
1077sel4,
1078sel5,
1079out
1080);
1081input in0;
1082input in1;
1083input in2;
1084input in3;
1085input in4;
1086input in5;
1087input sel0;
1088input sel1;
1089input sel2;
1090input sel3;
1091input sel4;
1092input sel5;
1093output out;
1094
1095`ifdef LIB
1096assign out = ((sel0 & in0) |
1097 (sel1 & in1) |
1098 (sel2 & in2) |
1099 (sel3 & in3) |
1100 (sel4 & in4) |
1101 (sel5 & in5));
1102`endif
1103
1104endmodule
1105
1106module cl_dp1lvt_aomux7_1x (
1107in0,
1108in1,
1109in2,
1110in3,
1111in4,
1112in5,
1113in6,
1114sel0,
1115sel1,
1116sel2,
1117sel3,
1118sel4,
1119sel5,
1120sel6,
1121out
1122);
1123input in0;
1124input in1;
1125input in2;
1126input in3;
1127input in4;
1128input in5;
1129input in6;
1130input sel0;
1131input sel1;
1132input sel2;
1133input sel3;
1134input sel4;
1135input sel5;
1136input sel6;
1137output out;
1138
1139`ifdef LIB
1140assign out = ((sel0 & in0) |
1141 (sel1 & in1) |
1142 (sel2 & in2) |
1143 (sel3 & in3) |
1144 (sel4 & in4) |
1145 (sel5 & in5) |
1146 (sel6 & in6));
1147`endif
1148
1149endmodule
1150module cl_dp1lvt_aomux7_2x (
1151in0,
1152in1,
1153in2,
1154in3,
1155in4,
1156in5,
1157in6,
1158sel0,
1159sel1,
1160sel2,
1161sel3,
1162sel4,
1163sel5,
1164sel6,
1165out
1166);
1167input in0;
1168input in1;
1169input in2;
1170input in3;
1171input in4;
1172input in5;
1173input in6;
1174input sel0;
1175input sel1;
1176input sel2;
1177input sel3;
1178input sel4;
1179input sel5;
1180input sel6;
1181output out;
1182
1183`ifdef LIB
1184assign out = ((sel0 & in0) |
1185 (sel1 & in1) |
1186 (sel2 & in2) |
1187 (sel3 & in3) |
1188 (sel4 & in4) |
1189 (sel5 & in5) |
1190 (sel6 & in6));
1191`endif
1192
1193endmodule
1194module cl_dp1lvt_aomux7_4x (
1195in0,
1196in1,
1197in2,
1198in3,
1199in4,
1200in5,
1201in6,
1202sel0,
1203sel1,
1204sel2,
1205sel3,
1206sel4,
1207sel5,
1208sel6,
1209out
1210);
1211input in0;
1212input in1;
1213input in2;
1214input in3;
1215input in4;
1216input in5;
1217input in6;
1218input sel0;
1219input sel1;
1220input sel2;
1221input sel3;
1222input sel4;
1223input sel5;
1224input sel6;
1225output out;
1226
1227`ifdef LIB
1228assign out = ((sel0 & in0) |
1229 (sel1 & in1) |
1230 (sel2 & in2) |
1231 (sel3 & in3) |
1232 (sel4 & in4) |
1233 (sel5 & in5) |
1234 (sel6 & in6));
1235`endif
1236
1237endmodule
1238module cl_dp1lvt_aomux7_6x (
1239in0,
1240in1,
1241in2,
1242in3,
1243in4,
1244in5,
1245in6,
1246sel0,
1247sel1,
1248sel2,
1249sel3,
1250sel4,
1251sel5,
1252sel6,
1253out
1254);
1255input in0;
1256input in1;
1257input in2;
1258input in3;
1259input in4;
1260input in5;
1261input in6;
1262input sel0;
1263input sel1;
1264input sel2;
1265input sel3;
1266input sel4;
1267input sel5;
1268input sel6;
1269output out;
1270
1271`ifdef LIB
1272assign out = ((sel0 & in0) |
1273 (sel1 & in1) |
1274 (sel2 & in2) |
1275 (sel3 & in3) |
1276 (sel4 & in4) |
1277 (sel5 & in5) |
1278 (sel6 & in6));
1279`endif
1280
1281endmodule
1282module cl_dp1lvt_aomux7_8x (
1283in0,
1284in1,
1285in2,
1286in3,
1287in4,
1288in5,
1289in6,
1290sel0,
1291sel1,
1292sel2,
1293sel3,
1294sel4,
1295sel5,
1296sel6,
1297out
1298);
1299input in0;
1300input in1;
1301input in2;
1302input in3;
1303input in4;
1304input in5;
1305input in6;
1306input sel0;
1307input sel1;
1308input sel2;
1309input sel3;
1310input sel4;
1311input sel5;
1312input sel6;
1313output out;
1314
1315`ifdef LIB
1316assign out = ((sel0 & in0) |
1317 (sel1 & in1) |
1318 (sel2 & in2) |
1319 (sel3 & in3) |
1320 (sel4 & in4) |
1321 (sel5 & in5) |
1322 (sel6 & in6));
1323`endif
1324
1325endmodule
1326
1327module cl_dp1lvt_aomux8_1x (
1328in0,
1329in1,
1330in2,
1331in3,
1332in4,
1333in5,
1334in6,
1335in7,
1336sel0,
1337sel1,
1338sel2,
1339sel3,
1340sel4,
1341sel5,
1342sel6,
1343sel7,
1344out
1345);
1346input in0;
1347input in1;
1348input in2;
1349input in3;
1350input in4;
1351input in5;
1352input in6;
1353input in7;
1354input sel0;
1355input sel1;
1356input sel2;
1357input sel3;
1358input sel4;
1359input sel5;
1360input sel6;
1361input sel7;
1362output out;
1363
1364`ifdef LIB
1365assign out = ((sel0 & in0) |
1366 (sel1 & in1) |
1367 (sel2 & in2) |
1368 (sel3 & in3) |
1369 (sel4 & in4) |
1370 (sel5 & in5) |
1371 (sel6 & in6) |
1372 (sel7 & in7));
1373`endif
1374
1375
1376endmodule
1377module cl_dp1lvt_aomux8_2x (
1378in0,
1379in1,
1380in2,
1381in3,
1382in4,
1383in5,
1384in6,
1385in7,
1386sel0,
1387sel1,
1388sel2,
1389sel3,
1390sel4,
1391sel5,
1392sel6,
1393sel7,
1394out
1395);
1396input in0;
1397input in1;
1398input in2;
1399input in3;
1400input in4;
1401input in5;
1402input in6;
1403input in7;
1404input sel0;
1405input sel1;
1406input sel2;
1407input sel3;
1408input sel4;
1409input sel5;
1410input sel6;
1411input sel7;
1412output out;
1413
1414`ifdef LIB
1415assign out = ((sel0 & in0) |
1416 (sel1 & in1) |
1417 (sel2 & in2) |
1418 (sel3 & in3) |
1419 (sel4 & in4) |
1420 (sel5 & in5) |
1421 (sel6 & in6) |
1422 (sel7 & in7));
1423`endif
1424
1425
1426endmodule
1427module cl_dp1lvt_aomux8_4x (
1428in0,
1429in1,
1430in2,
1431in3,
1432in4,
1433in5,
1434in6,
1435in7,
1436sel0,
1437sel1,
1438sel2,
1439sel3,
1440sel4,
1441sel5,
1442sel6,
1443sel7,
1444out
1445);
1446input in0;
1447input in1;
1448input in2;
1449input in3;
1450input in4;
1451input in5;
1452input in6;
1453input in7;
1454input sel0;
1455input sel1;
1456input sel2;
1457input sel3;
1458input sel4;
1459input sel5;
1460input sel6;
1461input sel7;
1462output out;
1463
1464`ifdef LIB
1465assign out = ((sel0 & in0) |
1466 (sel1 & in1) |
1467 (sel2 & in2) |
1468 (sel3 & in3) |
1469 (sel4 & in4) |
1470 (sel5 & in5) |
1471 (sel6 & in6) |
1472 (sel7 & in7));
1473`endif
1474
1475
1476endmodule
1477module cl_dp1lvt_aomux8_6x (
1478in0,
1479in1,
1480in2,
1481in3,
1482in4,
1483in5,
1484in6,
1485in7,
1486sel0,
1487sel1,
1488sel2,
1489sel3,
1490sel4,
1491sel5,
1492sel6,
1493sel7,
1494out
1495);
1496input in0;
1497input in1;
1498input in2;
1499input in3;
1500input in4;
1501input in5;
1502input in6;
1503input in7;
1504input sel0;
1505input sel1;
1506input sel2;
1507input sel3;
1508input sel4;
1509input sel5;
1510input sel6;
1511input sel7;
1512output out;
1513
1514`ifdef LIB
1515assign out = ((sel0 & in0) |
1516 (sel1 & in1) |
1517 (sel2 & in2) |
1518 (sel3 & in3) |
1519 (sel4 & in4) |
1520 (sel5 & in5) |
1521 (sel6 & in6) |
1522 (sel7 & in7));
1523`endif
1524
1525
1526endmodule
1527module cl_dp1lvt_aomux8_8x (
1528in0,
1529in1,
1530in2,
1531in3,
1532in4,
1533in5,
1534in6,
1535in7,
1536sel0,
1537sel1,
1538sel2,
1539sel3,
1540sel4,
1541sel5,
1542sel6,
1543sel7,
1544out
1545);
1546input in0;
1547input in1;
1548input in2;
1549input in3;
1550input in4;
1551input in5;
1552input in6;
1553input in7;
1554input sel0;
1555input sel1;
1556input sel2;
1557input sel3;
1558input sel4;
1559input sel5;
1560input sel6;
1561input sel7;
1562output out;
1563
1564`ifdef LIB
1565assign out = ((sel0 & in0) |
1566 (sel1 & in1) |
1567 (sel2 & in2) |
1568 (sel3 & in3) |
1569 (sel4 & in4) |
1570 (sel5 & in5) |
1571 (sel6 & in6) |
1572 (sel7 & in7));
1573`endif
1574
1575
1576endmodule
1577module cl_dp1lvt_incr32_8x (
1578cin,
1579in0,
1580out,
1581cout
1582);
1583input cin;
1584input [31:0] in0;
1585output [31:0] out;
1586output cout;
1587
1588`ifdef LIB
1589 assign {cout, out[31:0]} = {1'b0, in0[31:0]} + {32'b0, cin};
1590`endif
1591
1592endmodule
1593module cl_dp1lvt_incr48_8x (
1594cin,
1595in0,
1596out,
1597cout
1598);
1599input cin;
1600input [47:0] in0;
1601output [47:0] out;
1602output cout;
1603
1604`ifdef LIB
1605 assign {cout, out[47:0]} = {1'b0, in0[47:0]} + {48'b0, cin};
1606`endif
1607
1608endmodule
1609module cl_dp1lvt_incr64_8x (
1610cin,
1611in0,
1612out,
1613cout
1614);
1615input cin;
1616input [63:0] in0;
1617output [63:0] out;
1618output cout;
1619
1620`ifdef LIB
1621 assign {cout, out[63:0]} = {1'b0, in0[63:0]} + {64'b0, cin};
1622`endif
1623
1624endmodule