libs/cl/cl_dp1lvt/cl_dp1lvt.behV

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//
// OpenSPARC T2 Processor File: cl_dp1lvt.behV
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
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// otherwise unspecified.
//
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// ========== Copyright Header End ============================================
module cl_dp1lvt_add12_fulllvt_8x (
cin,
in0,
in1,
out,
cout
);
input          cin;
input   [11:0] in0;
input   [11:0] in1;
output  [11:0] out;
output         cout;

`ifdef LIB
  assign {cout, out[11:0]} = ({1'b0, in0[11:0]} + {1'b0, in1[11:0]} + {{12{1'b0}}, cin});
`endif

endmodule

module cl_dp1lvt_add16_fulllvt_8x (
cin,
in0,
in1,
out,
cout
);
input          cin;
input   [15:0] in0;
input   [15:0] in1;
output  [15:0] out;
output         cout;

`ifdef LIB
  assign {cout, out[15:0]} = ({1'b0, in0[15:0]} + {1'b0, in1[15:0]} + {{16{1'b0}}, cin});
`endif

endmodule
module cl_dp1lvt_add4_fulllvt_8x (
cin,
in0,
in1,
out,
cout
);
input          cin;
input   [3:0]  in0;
input   [3:0]  in1;
output  [3:0]  out;
output         cout;

`ifdef LIB
  assign {cout, out[3:0]} = ({1'b0, in0[3:0]} + {1'b0, in1[3:0]} + {{4{1'b0}}, cin});
`endif

endmodule
module cl_dp1lvt_add64_fulllvt_8x (
cin,
in0,
in1,
out,
cout
);
input          cin;
input   [63:0] in0;
input   [63:0] in1;
output  [63:0] out;
output         cout;

`ifdef LIB
  assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin});
`endif

endmodule
module cl_dp1lvt_add8_fulllvt_8x (
cin,
in0,
in1,
out,
cout
);
input          cin;
input   [7:0] in0;
input   [7:0] in1;
output  [7:0] out;
output         cout;

`ifdef LIB
  assign {cout, out[7:0]} = ({1'b0, in0[7:0]} + {1'b0, in1[7:0]} + {{8{1'b0}}, cin});
`endif

endmodule
module cl_dp1lvt_add12_8x (
cin,
in0,
in1,
out,
cout
);
input          cin;
input   [11:0] in0;
input   [11:0] in1;
output  [11:0] out;
output         cout;

`ifdef LIB
  assign {cout, out[11:0]} = ({1'b0, in0[11:0]} + {1'b0, in1[11:0]} + {{12{1'b0}}, cin});
`endif

endmodule
module cl_dp1lvt_add16_8x (
cin,
in0,
in1,
out,
cout
);
input          cin;
input   [15:0] in0;
input   [15:0] in1;
output  [15:0] out;
output         cout;

`ifdef LIB
  assign {cout, out[15:0]} = ({1'b0, in0[15:0]} + {1'b0, in1[15:0]} + {{16{1'b0}}, cin});
`endif

endmodule
module cl_dp1lvt_add32_8x (
cin,
in0,
in1,
out,
cout
);
input          cin;
input   [31:0] in0;
input   [31:0] in1;
output  [31:0] out;
output         cout;

`ifdef LIB
  assign {cout, out[31:0]} = ({1'b0, in0[31:0]} + {1'b0, in1[31:0]} + {{32{1'b0}}, cin});
`endif

endmodule
module cl_dp1lvt_add4_8x (
cin,
in0,
in1,
out,
cout
);
input          cin;
input   [3:0]  in0;
input   [3:0]  in1;
output  [3:0]  out;
output         cout;

`ifdef LIB
  assign {cout, out[3:0]} = ({1'b0, in0[3:0]} + {1'b0, in1[3:0]} + {{4{1'b0}}, cin});
`endif

endmodule
module cl_dp1lvt_add64_8x (
cin,
in0,
in1,
out,
cout
);
input          cin;
input   [63:0] in0;
input   [63:0] in1;
output  [63:0] out;
output         cout;

`ifdef LIB
  assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin});
`endif

endmodule


module cl_dp1lvt_cmpr12_8x (
in0,
in1,
out
);
input   [11:0] in0;
input   [11:0] in1;
output  out;

`ifdef LIB
assign out = (in0[11:0] == in1[11:0]);
`endif

endmodule
module cl_dp1lvt_add8_8x (
cin,
in0,
in1,
out,
cout
);
input          cin;
input   [7:0] in0;
input   [7:0] in1;
output  [7:0] out;
output         cout;

`ifdef LIB
  assign {cout, out[7:0]} = ({1'b0, in0[7:0]} + {1'b0, in1[7:0]} + {{8{1'b0}}, cin});
`endif

endmodule
module cl_dp1lvt_cmpr16_8x (
in0,
in1,
out
);
input   [15:0] in0;
input   [15:0] in1;
output  out;

`ifdef LIB
assign out = (in0[15:0] == in1[15:0]);
`endif

endmodule
module cl_dp1lvt_cmpr32_8x (
in0,
in1,
out
);
input   [31:0] in0;
input   [31:0] in1;
output  out;

`ifdef LIB
assign out = (in0[31:0] == in1[31:0]);
`endif

endmodule
module cl_dp1lvt_cmpr4_8x (
in0,
in1,
out
);
input   [3:0] in0;
input   [3:0] in1;
output  out;

`ifdef LIB
assign out = (in0[3:0] == in1[3:0]);
`endif

endmodule
module cl_dp1lvt_cmpr64_8x (
in0,
in1,
out
);
input   [63:0] in0;
input   [63:0] in1;
output  out;

`ifdef LIB
assign out = (in0[63:0] == in1[63:0]);
`endif

endmodule
module cl_dp1lvt_cmpr8_8x (
in0,
in1,
out
);
input   [7:0] in0;
input   [7:0] in1;
output  out;

`ifdef LIB
assign out = (in0[7:0] == in1[7:0]);
`endif

endmodule

module cl_dp1lvt_prty16_8x (
in,
out
);
input   [15:0] in;
output  out;


`ifdef LIB
assign out = ^in[15:0];
`endif

endmodule
module cl_dp1lvt_prty32_8x (
in,
out
);
input   [31:0] in;
output  out;

`ifdef LIB
assign out = ^in[31:0];
`endif

endmodule
module cl_dp1lvt_prty4_8x (
in,
out
);
input   [3:0] in;
output  out;

`ifdef LIB
assign out = ^in[3:0];
`endif

endmodule
module cl_dp1lvt_prty8_8x (
in,
out
);
input   [7:0] in;
output  out;

`ifdef LIB
assign out = ^in[7:0];
`endif

endmodule

module cl_dp1lvt_aomux2_1x (
in0,
in1,
sel0,
sel1,
out
);
input   in0;
input   in1;
input   sel0;
input   sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1));
`endif


endmodule
module cl_dp1lvt_aomux2_2x (
in0,
in1,
sel0,
sel1,
out
);
input   in0;
input   in1;
input   sel0;
input   sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1));
`endif


endmodule
module cl_dp1lvt_aomux2_4x (
in0,
in1,
sel0,
sel1,
out
);
input   in0;
input   in1;
input   sel0;
input   sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1));
`endif


endmodule
module cl_dp1lvt_aomux2_6x (
in0,
in1,
sel0,
sel1,
out
);
input   in0;
input   in1;
input   sel0;
input   sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1));
`endif


endmodule
module cl_dp1lvt_aomux2_8x (
in0,
in1,
sel0,
sel1,
out
);
input   in0;
input   in1;
input   sel0;
input   sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1));
`endif


endmodule

module cl_dp1lvt_aomux3_1x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input   in0;
input   in1;
input   in2;
input   sel0;
input   sel1;
input   sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2));
`endif

endmodule
module cl_dp1lvt_aomux3_2x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input   in0;
input   in1;
input   in2;
input   sel0;
input   sel1;
input   sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2));
`endif

endmodule
module cl_dp1lvt_aomux3_4x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input   in0;
input   in1;
input   in2;
input   sel0;
input   sel1;
input   sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2));
`endif

endmodule
module cl_dp1lvt_aomux3_6x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input   in0;
input   in1;
input   in2;
input   sel0;
input   sel1;
input   sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2));
`endif

endmodule
module cl_dp1lvt_aomux3_8x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input   in0;
input   in1;
input   in2;
input   sel0;
input   sel1;
input   sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2));
`endif

endmodule

module cl_dp1lvt_aomux4_1x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3));
`endif

endmodule
module cl_dp1lvt_aomux4_2x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3));
`endif

endmodule
module cl_dp1lvt_aomux4_4x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3));
`endif

endmodule
module cl_dp1lvt_aomux4_6x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3));
`endif

endmodule
module cl_dp1lvt_aomux4_8x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3));
`endif

endmodule

module cl_dp1lvt_aomux5_1x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4));
`endif

endmodule
module cl_dp1lvt_aomux5_2x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4));
`endif

endmodule
module cl_dp1lvt_aomux5_4x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4));
`endif

endmodule
module cl_dp1lvt_aomux5_6x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4));
`endif

endmodule
module cl_dp1lvt_aomux5_8x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4));
`endif

endmodule

module cl_dp1lvt_aomux6_1x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5));
`endif

endmodule
module cl_dp1lvt_aomux6_2x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5));
`endif

endmodule
module cl_dp1lvt_aomux6_4x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5));
`endif

endmodule
module cl_dp1lvt_aomux6_6x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5));
`endif

endmodule
module cl_dp1lvt_aomux6_8x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5));
`endif

endmodule

module cl_dp1lvt_aomux7_1x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   in6;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
input   sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5) |
              (sel6 & in6));
`endif

endmodule
module cl_dp1lvt_aomux7_2x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   in6;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
input   sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5) |
              (sel6 & in6));
`endif

endmodule
module cl_dp1lvt_aomux7_4x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   in6;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
input   sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5) |
              (sel6 & in6));
`endif

endmodule
module cl_dp1lvt_aomux7_6x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   in6;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
input   sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5) |
              (sel6 & in6));
`endif

endmodule
module cl_dp1lvt_aomux7_8x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   in6;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
input   sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5) |
              (sel6 & in6));
`endif

endmodule

module cl_dp1lvt_aomux8_1x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   in6;
input   in7;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
input   sel6;
input   sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5) |
              (sel6 & in6) |
              (sel7 & in7));
`endif


endmodule
module cl_dp1lvt_aomux8_2x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   in6;
input   in7;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
input   sel6;
input   sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5) |
              (sel6 & in6) |
              (sel7 & in7));
`endif


endmodule
module cl_dp1lvt_aomux8_4x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   in6;
input   in7;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
input   sel6;
input   sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5) |
              (sel6 & in6) |
              (sel7 & in7));
`endif


endmodule
module cl_dp1lvt_aomux8_6x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   in6;
input   in7;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
input   sel6;
input   sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5) |
              (sel6 & in6) |
              (sel7 & in7));
`endif


endmodule
module cl_dp1lvt_aomux8_8x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input   in0;
input   in1;
input   in2;
input   in3;
input   in4;
input   in5;
input   in6;
input   in7;
input   sel0;
input   sel1;
input   sel2;
input   sel3;
input   sel4;
input   sel5;
input   sel6;
input   sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
              (sel1 & in1) |
              (sel2 & in2) |
              (sel3 & in3) |
              (sel4 & in4) |
              (sel5 & in5) |
              (sel6 & in6) |
              (sel7 & in7));
`endif


endmodule
module cl_dp1lvt_incr32_8x (
cin,
in0,
out,
cout
);
input           cin;
input [31:0]    in0;
output [31:0]   out;
output          cout;

`ifdef LIB
  assign {cout, out[31:0]} = {1'b0, in0[31:0]} + {32'b0, cin};
`endif

endmodule
module cl_dp1lvt_incr48_8x (
cin,
in0,
out,
cout
);
input           cin;
input [47:0]    in0;
output [47:0]   out;
output          cout;

`ifdef LIB
  assign {cout, out[47:0]} = {1'b0, in0[47:0]} + {48'b0, cin};
`endif

endmodule
module cl_dp1lvt_incr64_8x (
cin,
in0,
out,
cout
);
input           cin;
input [63:0]    in0;
output [63:0]   out;
output          cout;

`ifdef LIB
  assign {cout, out[63:0]} = {1'b0, in0[63:0]} + {64'b0, cin};
`endif

endmodule