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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: cl_sc1.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module cl_sc1_msffmin_fp_16x ( q, so, d, l1clk, si, siclk, soclk ); | |
36 | // RFM 05-14-2004 | |
37 | // Level sensitive in SCAN_MODE | |
38 | // Edge triggered when not in SCAN_MODE | |
39 | ||
40 | ||
41 | parameter SIZE = 1; | |
42 | ||
43 | output q; | |
44 | output so; | |
45 | ||
46 | input d; | |
47 | input l1clk; | |
48 | input si; | |
49 | input siclk; | |
50 | input soclk; | |
51 | ||
52 | reg q; | |
53 | wire so; | |
54 | wire l1clk, siclk, soclk; | |
55 | ||
56 | `ifdef SCAN_MODE | |
57 | ||
58 | reg l1; | |
59 | `ifdef FAST_FLUSH | |
60 | always @(posedge l1clk or posedge siclk ) begin | |
61 | if (siclk) begin | |
62 | q <= 1'b0; //pseudo flush reset | |
63 | end else begin | |
64 | q <= d; | |
65 | end | |
66 | end | |
67 | `else | |
68 | always @(l1clk or siclk or soclk or d or si) | |
69 | begin | |
70 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
71 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
72 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
73 | ||
74 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
75 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
76 | end | |
77 | `endif | |
78 | `else | |
79 | wire si_unused; | |
80 | wire siclk_unused; | |
81 | wire soclk_unused; | |
82 | assign si_unused = si; | |
83 | assign siclk_unused = siclk; | |
84 | assign soclk_unused = soclk; | |
85 | ||
86 | ||
87 | `ifdef INITLATZERO | |
88 | initial q = 1'b0; | |
89 | `endif | |
90 | ||
91 | always @(posedge l1clk) | |
92 | begin | |
93 | if (!siclk && !soclk) q <= d; | |
94 | else q <= 1'bx; | |
95 | end | |
96 | `endif | |
97 | ||
98 | assign so = q; | |
99 | ||
100 | endmodule // dff | |
101 | ||
102 | ||
103 | ||
104 | ||
105 | module cl_sc1_msffmin_fp_8x ( q, so, d, l1clk, si, siclk, soclk ); | |
106 | // RFM 05-14-2004 | |
107 | // Level sensitive in SCAN_MODE | |
108 | // Edge triggered when not in SCAN_MODE | |
109 | ||
110 | ||
111 | parameter SIZE = 1; | |
112 | ||
113 | output q; | |
114 | output so; | |
115 | ||
116 | input d; | |
117 | input l1clk; | |
118 | input si; | |
119 | input siclk; | |
120 | input soclk; | |
121 | ||
122 | reg q; | |
123 | wire so; | |
124 | wire l1clk, siclk, soclk; | |
125 | ||
126 | `ifdef SCAN_MODE | |
127 | `ifdef FAST_FLUSH | |
128 | always @(posedge l1clk or posedge siclk ) begin | |
129 | if (siclk) begin | |
130 | q <= 1'b0; //pseudo flush reset | |
131 | end else begin | |
132 | q <= d; | |
133 | end | |
134 | end | |
135 | `else | |
136 | reg l1; | |
137 | ||
138 | always @(l1clk or siclk or soclk or d or si) | |
139 | begin | |
140 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
141 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
142 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
143 | ||
144 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
145 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
146 | end | |
147 | `endif | |
148 | `else | |
149 | wire si_unused; | |
150 | wire siclk_unused; | |
151 | wire soclk_unused; | |
152 | assign si_unused = si; | |
153 | assign siclk_unused = siclk; | |
154 | assign soclk_unused = soclk; | |
155 | ||
156 | ||
157 | `ifdef INITLATZERO | |
158 | initial q = 1'b0; | |
159 | `endif | |
160 | ||
161 | always @(posedge l1clk) | |
162 | begin | |
163 | if (!siclk && !soclk) q <= d; | |
164 | else q <= 1'bx; | |
165 | end | |
166 | `endif | |
167 | ||
168 | assign so = q; | |
169 | ||
170 | endmodule // dff | |
171 | module cl_sc1_msffmin_fp_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
172 | // RFM 05-14-2004 | |
173 | // Level sensitive in SCAN_MODE | |
174 | // Edge triggered when not in SCAN_MODE | |
175 | ||
176 | ||
177 | parameter SIZE = 1; | |
178 | ||
179 | output q; | |
180 | output so; | |
181 | ||
182 | input d; | |
183 | input l1clk; | |
184 | input si; | |
185 | input siclk; | |
186 | input soclk; | |
187 | ||
188 | reg q; | |
189 | wire so; | |
190 | wire l1clk, siclk, soclk; | |
191 | ||
192 | `ifdef SCAN_MODE | |
193 | ||
194 | reg l1; | |
195 | `ifdef FAST_FLUSH | |
196 | always @(posedge l1clk or posedge siclk ) begin | |
197 | if (siclk) begin | |
198 | q <= 1'b0; //pseudo flush reset | |
199 | end else begin | |
200 | q <= d; | |
201 | end | |
202 | end | |
203 | `else | |
204 | always @(l1clk or siclk or soclk or d or si) | |
205 | begin | |
206 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
207 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
208 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
209 | ||
210 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
211 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
212 | end | |
213 | `endif | |
214 | `else | |
215 | wire si_unused; | |
216 | wire siclk_unused; | |
217 | wire soclk_unused; | |
218 | assign si_unused = si; | |
219 | assign siclk_unused = siclk; | |
220 | assign soclk_unused = soclk; | |
221 | ||
222 | ||
223 | `ifdef INITLATZERO | |
224 | initial q = 1'b0; | |
225 | `endif | |
226 | ||
227 | always @(posedge l1clk) | |
228 | begin | |
229 | if (!siclk && !soclk) q <= d; | |
230 | else q <= 1'bx; | |
231 | end | |
232 | `endif | |
233 | ||
234 | assign so = q; | |
235 | ||
236 | endmodule // dff | |
237 | module cl_sc1_msffmin_fp_32x ( q, so, d, l1clk, si, siclk, soclk ); | |
238 | // RFM 05-14-2004 | |
239 | // Level sensitive in SCAN_MODE | |
240 | // Edge triggered when not in SCAN_MODE | |
241 | ||
242 | ||
243 | parameter SIZE = 1; | |
244 | ||
245 | output q; | |
246 | output so; | |
247 | ||
248 | input d; | |
249 | input l1clk; | |
250 | input si; | |
251 | input siclk; | |
252 | input soclk; | |
253 | ||
254 | reg q; | |
255 | wire so; | |
256 | wire l1clk, siclk, soclk; | |
257 | ||
258 | `ifdef SCAN_MODE | |
259 | ||
260 | reg l1; | |
261 | `ifdef FAST_FLUSH | |
262 | always @(posedge l1clk or posedge siclk ) begin | |
263 | if (siclk) begin | |
264 | q <= 1'b0; //pseudo flush reset | |
265 | end else begin | |
266 | q <= d; | |
267 | end | |
268 | end | |
269 | `else | |
270 | always @(l1clk or siclk or soclk or d or si) | |
271 | begin | |
272 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
273 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
274 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
275 | ||
276 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
277 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
278 | end | |
279 | `endif | |
280 | `else | |
281 | wire si_unused; | |
282 | wire siclk_unused; | |
283 | wire soclk_unused; | |
284 | assign si_unused = si; | |
285 | assign siclk_unused = siclk; | |
286 | assign soclk_unused = soclk; | |
287 | ||
288 | ||
289 | `ifdef INITLATZERO | |
290 | initial q = 1'b0; | |
291 | `endif | |
292 | ||
293 | always @(posedge l1clk) | |
294 | begin | |
295 | if (!siclk && !soclk) q <= d; | |
296 | else q <= 1'bx; | |
297 | end | |
298 | `endif | |
299 | ||
300 | assign so = q; | |
301 | ||
302 | endmodule // dff | |
303 | module cl_sc1_msffmin_fp_1x ( q, so, d, l1clk, si, siclk, soclk ); | |
304 | // RFM 05-14-2004 | |
305 | // Level sensitive in SCAN_MODE | |
306 | // Edge triggered when not in SCAN_MODE | |
307 | ||
308 | ||
309 | parameter SIZE = 1; | |
310 | ||
311 | output q; | |
312 | output so; | |
313 | ||
314 | input d; | |
315 | input l1clk; | |
316 | input si; | |
317 | input siclk; | |
318 | input soclk; | |
319 | ||
320 | reg q; | |
321 | wire so; | |
322 | wire l1clk, siclk, soclk; | |
323 | ||
324 | `ifdef SCAN_MODE | |
325 | ||
326 | reg l1; | |
327 | `ifdef FAST_FLUSH | |
328 | always @(posedge l1clk or posedge siclk ) begin | |
329 | if (siclk) begin | |
330 | q <= 1'b0; //pseudo flush reset | |
331 | end else begin | |
332 | q <= d; | |
333 | end | |
334 | end | |
335 | `else | |
336 | always @(l1clk or siclk or soclk or d or si) | |
337 | begin | |
338 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
339 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
340 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
341 | ||
342 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
343 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
344 | end | |
345 | `endif | |
346 | `else | |
347 | wire si_unused; | |
348 | wire siclk_unused; | |
349 | wire soclk_unused; | |
350 | assign si_unused = si; | |
351 | assign siclk_unused = siclk; | |
352 | assign soclk_unused = soclk; | |
353 | ||
354 | ||
355 | `ifdef INITLATZERO | |
356 | initial q = 1'b0; | |
357 | `endif | |
358 | ||
359 | always @(posedge l1clk) | |
360 | begin | |
361 | if (!siclk && !soclk) q <= d; | |
362 | else q <= 1'bx; | |
363 | end | |
364 | `endif | |
365 | ||
366 | assign so = q; | |
367 | ||
368 | endmodule // dff | |
369 | module cl_sc1_msffmin_fp_30ps_16x ( q, so, d, l1clk, si, siclk, soclk ); | |
370 | // RFM 05-14-2004 | |
371 | // Level sensitive in SCAN_MODE | |
372 | // Edge triggered when not in SCAN_MODE | |
373 | ||
374 | ||
375 | parameter SIZE = 1; | |
376 | ||
377 | output q; | |
378 | output so; | |
379 | ||
380 | input d; | |
381 | input l1clk; | |
382 | input si; | |
383 | input siclk; | |
384 | input soclk; | |
385 | ||
386 | reg q; | |
387 | wire so; | |
388 | wire l1clk, siclk, soclk; | |
389 | ||
390 | `ifdef SCAN_MODE | |
391 | ||
392 | reg l1; | |
393 | `ifdef FAST_FLUSH | |
394 | always @(posedge l1clk or posedge siclk ) begin | |
395 | if (siclk) begin | |
396 | q <= 1'b0; //pseudo flush reset | |
397 | end else begin | |
398 | q <= d; | |
399 | end | |
400 | end | |
401 | `else | |
402 | ||
403 | always @(l1clk or siclk or soclk or d or si) | |
404 | begin | |
405 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
406 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
407 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
408 | ||
409 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
410 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
411 | end | |
412 | `endif | |
413 | `else | |
414 | wire si_unused; | |
415 | wire siclk_unused; | |
416 | wire soclk_unused; | |
417 | assign si_unused = si; | |
418 | assign siclk_unused = siclk; | |
419 | assign soclk_unused = soclk; | |
420 | ||
421 | ||
422 | `ifdef INITLATZERO | |
423 | initial q = 1'b0; | |
424 | `endif | |
425 | ||
426 | always @(posedge l1clk) | |
427 | begin | |
428 | if (!siclk && !soclk) q <= d; | |
429 | else q <= 1'bx; | |
430 | end | |
431 | `endif | |
432 | ||
433 | assign so = q; | |
434 | ||
435 | endmodule // dff | |
436 | ||
437 | ||
438 | ||
439 | ||
440 | module cl_sc1_msffmin_fp_30ps_8x ( q, so, d, l1clk, si, siclk, soclk ); | |
441 | // RFM 05-14-2004 | |
442 | // Level sensitive in SCAN_MODE | |
443 | // Edge triggered when not in SCAN_MODE | |
444 | ||
445 | ||
446 | parameter SIZE = 1; | |
447 | ||
448 | output q; | |
449 | output so; | |
450 | ||
451 | input d; | |
452 | input l1clk; | |
453 | input si; | |
454 | input siclk; | |
455 | input soclk; | |
456 | ||
457 | reg q; | |
458 | wire so; | |
459 | wire l1clk, siclk, soclk; | |
460 | ||
461 | `ifdef SCAN_MODE | |
462 | ||
463 | reg l1; | |
464 | `ifdef FAST_FLUSH | |
465 | always @(posedge l1clk or posedge siclk ) begin | |
466 | if (siclk) begin | |
467 | q <= 1'b0; //pseudo flush reset | |
468 | end else begin | |
469 | q <= d; | |
470 | end | |
471 | end | |
472 | `else | |
473 | always @(l1clk or siclk or soclk or d or si) | |
474 | begin | |
475 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
476 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
477 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
478 | ||
479 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
480 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
481 | end | |
482 | `endif | |
483 | `else | |
484 | wire si_unused; | |
485 | wire siclk_unused; | |
486 | wire soclk_unused; | |
487 | assign si_unused = si; | |
488 | assign siclk_unused = siclk; | |
489 | assign soclk_unused = soclk; | |
490 | ||
491 | ||
492 | `ifdef INITLATZERO | |
493 | initial q = 1'b0; | |
494 | `endif | |
495 | ||
496 | always @(posedge l1clk) | |
497 | begin | |
498 | if (!siclk && !soclk) q <= d; | |
499 | else q <= 1'bx; | |
500 | end | |
501 | `endif | |
502 | ||
503 | assign so = q; | |
504 | ||
505 | endmodule // dff | |
506 | module cl_sc1_msffmin_fp_30ps_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
507 | // RFM 05-14-2004 | |
508 | // Level sensitive in SCAN_MODE | |
509 | // Edge triggered when not in SCAN_MODE | |
510 | ||
511 | ||
512 | parameter SIZE = 1; | |
513 | ||
514 | output q; | |
515 | output so; | |
516 | ||
517 | input d; | |
518 | input l1clk; | |
519 | input si; | |
520 | input siclk; | |
521 | input soclk; | |
522 | ||
523 | reg q; | |
524 | wire so; | |
525 | wire l1clk, siclk, soclk; | |
526 | ||
527 | `ifdef SCAN_MODE | |
528 | ||
529 | reg l1; | |
530 | `ifdef FAST_FLUSH | |
531 | always @(posedge l1clk or posedge siclk ) begin | |
532 | if (siclk) begin | |
533 | q <= 1'b0; //pseudo flush reset | |
534 | end else begin | |
535 | q <= d; | |
536 | end | |
537 | end | |
538 | `else | |
539 | always @(l1clk or siclk or soclk or d or si) | |
540 | begin | |
541 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
542 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
543 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
544 | ||
545 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
546 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
547 | end | |
548 | `endif | |
549 | `else | |
550 | wire si_unused; | |
551 | wire siclk_unused; | |
552 | wire soclk_unused; | |
553 | assign si_unused = si; | |
554 | assign siclk_unused = siclk; | |
555 | assign soclk_unused = soclk; | |
556 | ||
557 | ||
558 | `ifdef INITLATZERO | |
559 | initial q = 1'b0; | |
560 | `endif | |
561 | ||
562 | always @(posedge l1clk) | |
563 | begin | |
564 | if (!siclk && !soclk) q <= d; | |
565 | else q <= 1'bx; | |
566 | end | |
567 | `endif | |
568 | ||
569 | assign so = q; | |
570 | ||
571 | endmodule // dff | |
572 | module cl_sc1_msffmin_fp_30ps_32x ( q, so, d, l1clk, si, siclk, soclk ); | |
573 | // RFM 05-14-2004 | |
574 | // Level sensitive in SCAN_MODE | |
575 | // Edge triggered when not in SCAN_MODE | |
576 | ||
577 | ||
578 | parameter SIZE = 1; | |
579 | ||
580 | output q; | |
581 | output so; | |
582 | ||
583 | input d; | |
584 | input l1clk; | |
585 | input si; | |
586 | input siclk; | |
587 | input soclk; | |
588 | ||
589 | reg q; | |
590 | wire so; | |
591 | wire l1clk, siclk, soclk; | |
592 | ||
593 | `ifdef SCAN_MODE | |
594 | ||
595 | reg l1; | |
596 | `ifdef FAST_FLUSH | |
597 | always @(posedge l1clk or posedge siclk ) begin | |
598 | if (siclk) begin | |
599 | q <= 1'b0; //pseudo flush reset | |
600 | end else begin | |
601 | q <= d; | |
602 | end | |
603 | end | |
604 | `else | |
605 | always @(l1clk or siclk or soclk or d or si) | |
606 | begin | |
607 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
608 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
609 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
610 | ||
611 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
612 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
613 | end | |
614 | `endif | |
615 | `else | |
616 | wire si_unused; | |
617 | wire siclk_unused; | |
618 | wire soclk_unused; | |
619 | assign si_unused = si; | |
620 | assign siclk_unused = siclk; | |
621 | assign soclk_unused = soclk; | |
622 | ||
623 | ||
624 | `ifdef INITLATZERO | |
625 | initial q = 1'b0; | |
626 | `endif | |
627 | ||
628 | always @(posedge l1clk) | |
629 | begin | |
630 | if (!siclk && !soclk) q <= d; | |
631 | else q <= 1'bx; | |
632 | end | |
633 | `endif | |
634 | ||
635 | assign so = q; | |
636 | ||
637 | endmodule // dff | |
638 | module cl_sc1_msffmin_fp_30ps_1x ( q, so, d, l1clk, si, siclk, soclk ); | |
639 | // RFM 05-14-2004 | |
640 | // Level sensitive in SCAN_MODE | |
641 | // Edge triggered when not in SCAN_MODE | |
642 | ||
643 | ||
644 | parameter SIZE = 1; | |
645 | ||
646 | output q; | |
647 | output so; | |
648 | ||
649 | input d; | |
650 | input l1clk; | |
651 | input si; | |
652 | input siclk; | |
653 | input soclk; | |
654 | ||
655 | reg q; | |
656 | wire so; | |
657 | wire l1clk, siclk, soclk; | |
658 | ||
659 | `ifdef SCAN_MODE | |
660 | ||
661 | reg l1; | |
662 | `ifdef FAST_FLUSH | |
663 | always @(posedge l1clk or posedge siclk ) begin | |
664 | if (siclk) begin | |
665 | q <= 1'b0; //pseudo flush reset | |
666 | end else begin | |
667 | q <= d; | |
668 | end | |
669 | end | |
670 | `else | |
671 | always @(l1clk or siclk or soclk or d or si) | |
672 | begin | |
673 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
674 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
675 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
676 | ||
677 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
678 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
679 | end | |
680 | `endif | |
681 | `else | |
682 | wire si_unused; | |
683 | wire siclk_unused; | |
684 | wire soclk_unused; | |
685 | assign si_unused = si; | |
686 | assign siclk_unused = siclk; | |
687 | assign soclk_unused = soclk; | |
688 | ||
689 | ||
690 | `ifdef INITLATZERO | |
691 | initial q = 1'b0; | |
692 | `endif | |
693 | ||
694 | always @(posedge l1clk) | |
695 | begin | |
696 | if (!siclk && !soclk) q <= d; | |
697 | else q <= 1'bx; | |
698 | end | |
699 | `endif | |
700 | ||
701 | assign so = q; | |
702 | ||
703 | endmodule // dff | |
704 | ||
705 | module cl_sc1_msffmin_fp_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
706 | // RFM 05-14-2004 | |
707 | // Level sensitive in SCAN_MODE | |
708 | // Edge triggered when not in SCAN_MODE | |
709 | ||
710 | ||
711 | parameter SIZE = 1; | |
712 | ||
713 | output q; | |
714 | output so; | |
715 | ||
716 | input d; | |
717 | input l1clk; | |
718 | input si; | |
719 | input siclk; | |
720 | input soclk; | |
721 | input reset; | |
722 | reg q; | |
723 | wire so; | |
724 | wire l1clk, siclk, soclk; | |
725 | ||
726 | `ifdef SCAN_MODE | |
727 | ||
728 | reg l1; | |
729 | `ifdef FAST_FLUSH | |
730 | always @(l1clk or siclk or d ) // vcs optimized code | |
731 | begin | |
732 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
733 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
734 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
735 | l1 <= 1'b0; | |
736 | q <= 1'b0; | |
737 | end | |
738 | end | |
739 | `else | |
740 | always @(l1clk or siclk or soclk or d or si) | |
741 | begin | |
742 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
743 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
744 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
745 | ||
746 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
747 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
748 | end | |
749 | `endif | |
750 | `else | |
751 | wire si_unused; | |
752 | wire siclk_unused; | |
753 | wire soclk_unused; | |
754 | assign si_unused = si; | |
755 | assign siclk_unused = siclk; | |
756 | assign soclk_unused = soclk; | |
757 | ||
758 | ||
759 | `ifdef INITLATZERO | |
760 | initial q = 1'b0; | |
761 | `endif | |
762 | ||
763 | always @(posedge l1clk) | |
764 | begin | |
765 | if (!siclk && !soclk) q <= (d&reset); | |
766 | else q <= 1'bx; | |
767 | end | |
768 | `endif | |
769 | ||
770 | assign so = q; | |
771 | ||
772 | endmodule // dff | |
773 | module cl_sc1_msffmin_fp_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
774 | // RFM 05-14-2004 | |
775 | // Level sensitive in SCAN_MODE | |
776 | // Edge triggered when not in SCAN_MODE | |
777 | ||
778 | ||
779 | parameter SIZE = 1; | |
780 | ||
781 | output q; | |
782 | output so; | |
783 | ||
784 | input d; | |
785 | input l1clk; | |
786 | input si; | |
787 | input siclk; | |
788 | input soclk; | |
789 | input reset; | |
790 | reg q; | |
791 | wire so; | |
792 | wire l1clk, siclk, soclk; | |
793 | ||
794 | `ifdef SCAN_MODE | |
795 | ||
796 | reg l1; | |
797 | `ifdef FAST_FLUSH | |
798 | always @(l1clk or siclk or d ) // vcs optimized code | |
799 | begin | |
800 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
801 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
802 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
803 | l1 <= 1'b0; | |
804 | q <= 1'b0; | |
805 | end | |
806 | end | |
807 | `else | |
808 | always @(l1clk or siclk or soclk or d or si) | |
809 | begin | |
810 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
811 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
812 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
813 | ||
814 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
815 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
816 | end | |
817 | `endif | |
818 | `else | |
819 | wire si_unused; | |
820 | wire siclk_unused; | |
821 | wire soclk_unused; | |
822 | assign si_unused = si; | |
823 | assign siclk_unused = siclk; | |
824 | assign soclk_unused = soclk; | |
825 | ||
826 | ||
827 | `ifdef INITLATZERO | |
828 | initial q = 1'b0; | |
829 | `endif | |
830 | ||
831 | always @(posedge l1clk) | |
832 | begin | |
833 | if (!siclk && !soclk) q <= (d&reset); | |
834 | else q <= 1'bx; | |
835 | end | |
836 | `endif | |
837 | ||
838 | assign so = q; | |
839 | ||
840 | endmodule // dff | |
841 | module cl_sc1_msffmin_fp_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
842 | // RFM 05-14-2004 | |
843 | // Level sensitive in SCAN_MODE | |
844 | // Edge triggered when not in SCAN_MODE | |
845 | ||
846 | ||
847 | parameter SIZE = 1; | |
848 | ||
849 | output q; | |
850 | output so; | |
851 | ||
852 | input d; | |
853 | input l1clk; | |
854 | input si; | |
855 | input siclk; | |
856 | input soclk; | |
857 | input reset; | |
858 | reg q; | |
859 | wire so; | |
860 | wire l1clk, siclk, soclk; | |
861 | ||
862 | `ifdef SCAN_MODE | |
863 | ||
864 | reg l1; | |
865 | `ifdef FAST_FLUSH | |
866 | always @(l1clk or siclk or d ) // vcs optimized code | |
867 | begin | |
868 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
869 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
870 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
871 | l1 <= 1'b0; | |
872 | q <= 1'b0; | |
873 | end | |
874 | end | |
875 | `else | |
876 | always @(l1clk or siclk or soclk or d or si) | |
877 | begin | |
878 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
879 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
880 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
881 | ||
882 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
883 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
884 | end | |
885 | `endif | |
886 | `else | |
887 | wire si_unused; | |
888 | wire siclk_unused; | |
889 | wire soclk_unused; | |
890 | assign si_unused = si; | |
891 | assign siclk_unused = siclk; | |
892 | assign soclk_unused = soclk; | |
893 | ||
894 | ||
895 | `ifdef INITLATZERO | |
896 | initial q = 1'b0; | |
897 | `endif | |
898 | ||
899 | always @(posedge l1clk) | |
900 | begin | |
901 | if (!siclk && !soclk) q <= (d&reset); | |
902 | else q <= 1'bx; | |
903 | end | |
904 | `endif | |
905 | ||
906 | assign so = q; | |
907 | ||
908 | endmodule // dff | |
909 | module cl_sc1_msffmin_fp_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
910 | // RFM 05-14-2004 | |
911 | // Level sensitive in SCAN_MODE | |
912 | // Edge triggered when not in SCAN_MODE | |
913 | ||
914 | ||
915 | parameter SIZE = 1; | |
916 | ||
917 | output q; | |
918 | output so; | |
919 | ||
920 | input d; | |
921 | input l1clk; | |
922 | input si; | |
923 | input siclk; | |
924 | input soclk; | |
925 | input reset; | |
926 | reg q; | |
927 | wire so; | |
928 | wire l1clk, siclk, soclk; | |
929 | ||
930 | `ifdef SCAN_MODE | |
931 | ||
932 | reg l1; | |
933 | `ifdef FAST_FLUSH | |
934 | always @(l1clk or siclk or d ) // vcs optimized code | |
935 | begin | |
936 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
937 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
938 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
939 | l1 <= 1'b0; | |
940 | q <= 1'b0; | |
941 | end | |
942 | end | |
943 | `else | |
944 | always @(l1clk or siclk or soclk or d or si) | |
945 | begin | |
946 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
947 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
948 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
949 | ||
950 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
951 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
952 | end | |
953 | `endif | |
954 | `else | |
955 | wire si_unused; | |
956 | wire siclk_unused; | |
957 | wire soclk_unused; | |
958 | assign si_unused = si; | |
959 | assign siclk_unused = siclk; | |
960 | assign soclk_unused = soclk; | |
961 | ||
962 | ||
963 | `ifdef INITLATZERO | |
964 | initial q = 1'b0; | |
965 | `endif | |
966 | ||
967 | always @(posedge l1clk) | |
968 | begin | |
969 | if (!siclk && !soclk) q <= (d&reset); | |
970 | else q <= 1'bx; | |
971 | end | |
972 | `endif | |
973 | ||
974 | assign so = q; | |
975 | ||
976 | endmodule // dff | |
977 | module cl_sc1_msffmin_fp_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
978 | // RFM 05-14-2004 | |
979 | // Level sensitive in SCAN_MODE | |
980 | // Edge triggered when not in SCAN_MODE | |
981 | ||
982 | ||
983 | parameter SIZE = 1; | |
984 | ||
985 | output q; | |
986 | output so; | |
987 | ||
988 | input d; | |
989 | input l1clk; | |
990 | input si; | |
991 | input siclk; | |
992 | input soclk; | |
993 | input reset; | |
994 | reg q; | |
995 | wire so; | |
996 | wire l1clk, siclk, soclk; | |
997 | ||
998 | `ifdef SCAN_MODE | |
999 | ||
1000 | reg l1; | |
1001 | `ifdef FAST_FLUSH | |
1002 | always @(l1clk or siclk or d ) // vcs optimized code | |
1003 | begin | |
1004 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1005 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
1006 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
1007 | l1 <= 1'b0; | |
1008 | q <= 1'b0; | |
1009 | end | |
1010 | end | |
1011 | `else | |
1012 | always @(l1clk or siclk or soclk or d or si) | |
1013 | begin | |
1014 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1015 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1016 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1017 | ||
1018 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1019 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1020 | end | |
1021 | `endif | |
1022 | `else | |
1023 | wire si_unused; | |
1024 | wire siclk_unused; | |
1025 | wire soclk_unused; | |
1026 | assign si_unused = si; | |
1027 | assign siclk_unused = siclk; | |
1028 | assign soclk_unused = soclk; | |
1029 | ||
1030 | ||
1031 | `ifdef INITLATZERO | |
1032 | initial q = 1'b0; | |
1033 | `endif | |
1034 | ||
1035 | always @(posedge l1clk) | |
1036 | begin | |
1037 | if (!siclk && !soclk) q <= (d&reset); | |
1038 | else q <= 1'bx; | |
1039 | end | |
1040 | `endif | |
1041 | ||
1042 | assign so = q; | |
1043 | ||
1044 | endmodule // dff | |
1045 | module cl_sc1_msffmin_30ps_16x ( q, so, d, l1clk, si, siclk, soclk ); | |
1046 | // RFM 05-14-2004 | |
1047 | // Level sensitive in SCAN_MODE | |
1048 | // Edge triggered when not in SCAN_MODE | |
1049 | ||
1050 | ||
1051 | parameter SIZE = 1; | |
1052 | ||
1053 | output q; | |
1054 | output so; | |
1055 | ||
1056 | input d; | |
1057 | input l1clk; | |
1058 | input si; | |
1059 | input siclk; | |
1060 | input soclk; | |
1061 | ||
1062 | reg q; | |
1063 | wire so; | |
1064 | wire l1clk, siclk, soclk; | |
1065 | ||
1066 | `ifdef SCAN_MODE | |
1067 | ||
1068 | reg l1; | |
1069 | `ifdef FAST_FLUSH | |
1070 | always @(posedge l1clk or posedge siclk ) begin | |
1071 | if (siclk) begin | |
1072 | q <= 1'b0; //pseudo flush reset | |
1073 | end else begin | |
1074 | q <= d; | |
1075 | end | |
1076 | end | |
1077 | `else | |
1078 | ||
1079 | always @(l1clk or siclk or soclk or d or si) | |
1080 | begin | |
1081 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
1082 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1083 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1084 | ||
1085 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1086 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1087 | end | |
1088 | `endif | |
1089 | `else | |
1090 | wire si_unused; | |
1091 | wire siclk_unused; | |
1092 | wire soclk_unused; | |
1093 | assign si_unused = si; | |
1094 | assign siclk_unused = siclk; | |
1095 | assign soclk_unused = soclk; | |
1096 | ||
1097 | ||
1098 | `ifdef INITLATZERO | |
1099 | initial q = 1'b0; | |
1100 | `endif | |
1101 | ||
1102 | always @(posedge l1clk) | |
1103 | begin | |
1104 | if (!siclk && !soclk) q <= d; | |
1105 | else q <= 1'bx; | |
1106 | end | |
1107 | `endif | |
1108 | ||
1109 | assign so = q; | |
1110 | ||
1111 | endmodule // dff | |
1112 | ||
1113 | ||
1114 | ||
1115 | ||
1116 | module cl_sc1_msffmin_30ps_8x ( q, so, d, l1clk, si, siclk, soclk ); | |
1117 | // RFM 05-14-2004 | |
1118 | // Level sensitive in SCAN_MODE | |
1119 | // Edge triggered when not in SCAN_MODE | |
1120 | ||
1121 | ||
1122 | parameter SIZE = 1; | |
1123 | ||
1124 | output q; | |
1125 | output so; | |
1126 | ||
1127 | input d; | |
1128 | input l1clk; | |
1129 | input si; | |
1130 | input siclk; | |
1131 | input soclk; | |
1132 | ||
1133 | reg q; | |
1134 | wire so; | |
1135 | wire l1clk, siclk, soclk; | |
1136 | ||
1137 | `ifdef SCAN_MODE | |
1138 | ||
1139 | reg l1; | |
1140 | `ifdef FAST_FLUSH | |
1141 | always @(posedge l1clk or posedge siclk ) begin | |
1142 | if (siclk) begin | |
1143 | q <= 1'b0; //pseudo flush reset | |
1144 | end else begin | |
1145 | q <= d; | |
1146 | end | |
1147 | end | |
1148 | `else | |
1149 | always @(l1clk or siclk or soclk or d or si) | |
1150 | begin | |
1151 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
1152 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1153 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1154 | ||
1155 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1156 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1157 | end | |
1158 | `endif | |
1159 | `else | |
1160 | wire si_unused; | |
1161 | wire siclk_unused; | |
1162 | wire soclk_unused; | |
1163 | assign si_unused = si; | |
1164 | assign siclk_unused = siclk; | |
1165 | assign soclk_unused = soclk; | |
1166 | ||
1167 | ||
1168 | `ifdef INITLATZERO | |
1169 | initial q = 1'b0; | |
1170 | `endif | |
1171 | ||
1172 | always @(posedge l1clk) | |
1173 | begin | |
1174 | if (!siclk && !soclk) q <= d; | |
1175 | else q <= 1'bx; | |
1176 | end | |
1177 | `endif | |
1178 | ||
1179 | assign so = q; | |
1180 | ||
1181 | endmodule // dff | |
1182 | module cl_sc1_msffmin_30ps_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
1183 | // RFM 05-14-2004 | |
1184 | // Level sensitive in SCAN_MODE | |
1185 | // Edge triggered when not in SCAN_MODE | |
1186 | ||
1187 | ||
1188 | parameter SIZE = 1; | |
1189 | ||
1190 | output q; | |
1191 | output so; | |
1192 | ||
1193 | input d; | |
1194 | input l1clk; | |
1195 | input si; | |
1196 | input siclk; | |
1197 | input soclk; | |
1198 | ||
1199 | reg q; | |
1200 | wire so; | |
1201 | wire l1clk, siclk, soclk; | |
1202 | ||
1203 | `ifdef SCAN_MODE | |
1204 | ||
1205 | reg l1; | |
1206 | `ifdef FAST_FLUSH | |
1207 | always @(posedge l1clk or posedge siclk ) begin | |
1208 | if (siclk) begin | |
1209 | q <= 1'b0; //pseudo flush reset | |
1210 | end else begin | |
1211 | q <= d; | |
1212 | end | |
1213 | end | |
1214 | `else | |
1215 | always @(l1clk or siclk or soclk or d or si) | |
1216 | begin | |
1217 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
1218 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1219 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1220 | ||
1221 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1222 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1223 | end | |
1224 | `endif | |
1225 | `else | |
1226 | wire si_unused; | |
1227 | wire siclk_unused; | |
1228 | wire soclk_unused; | |
1229 | assign si_unused = si; | |
1230 | assign siclk_unused = siclk; | |
1231 | assign soclk_unused = soclk; | |
1232 | ||
1233 | ||
1234 | `ifdef INITLATZERO | |
1235 | initial q = 1'b0; | |
1236 | `endif | |
1237 | ||
1238 | always @(posedge l1clk) | |
1239 | begin | |
1240 | if (!siclk && !soclk) q <= d; | |
1241 | else q <= 1'bx; | |
1242 | end | |
1243 | `endif | |
1244 | ||
1245 | assign so = q; | |
1246 | ||
1247 | endmodule // dff | |
1248 | module cl_sc1_msffmin_30ps_32x ( q, so, d, l1clk, si, siclk, soclk ); | |
1249 | // RFM 05-14-2004 | |
1250 | // Level sensitive in SCAN_MODE | |
1251 | // Edge triggered when not in SCAN_MODE | |
1252 | ||
1253 | ||
1254 | parameter SIZE = 1; | |
1255 | ||
1256 | output q; | |
1257 | output so; | |
1258 | ||
1259 | input d; | |
1260 | input l1clk; | |
1261 | input si; | |
1262 | input siclk; | |
1263 | input soclk; | |
1264 | ||
1265 | reg q; | |
1266 | wire so; | |
1267 | wire l1clk, siclk, soclk; | |
1268 | ||
1269 | `ifdef SCAN_MODE | |
1270 | ||
1271 | reg l1; | |
1272 | `ifdef FAST_FLUSH | |
1273 | always @(posedge l1clk or posedge siclk ) begin | |
1274 | if (siclk) begin | |
1275 | q <= 1'b0; //pseudo flush reset | |
1276 | end else begin | |
1277 | q <= d; | |
1278 | end | |
1279 | end | |
1280 | `else | |
1281 | always @(l1clk or siclk or soclk or d or si) | |
1282 | begin | |
1283 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
1284 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1285 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1286 | ||
1287 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1288 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1289 | end | |
1290 | `endif | |
1291 | `else | |
1292 | wire si_unused; | |
1293 | wire siclk_unused; | |
1294 | wire soclk_unused; | |
1295 | assign si_unused = si; | |
1296 | assign siclk_unused = siclk; | |
1297 | assign soclk_unused = soclk; | |
1298 | ||
1299 | ||
1300 | `ifdef INITLATZERO | |
1301 | initial q = 1'b0; | |
1302 | `endif | |
1303 | ||
1304 | always @(posedge l1clk) | |
1305 | begin | |
1306 | if (!siclk && !soclk) q <= d; | |
1307 | else q <= 1'bx; | |
1308 | end | |
1309 | `endif | |
1310 | ||
1311 | assign so = q; | |
1312 | ||
1313 | endmodule // dff | |
1314 | module cl_sc1_msffmin_30ps_1x ( q, so, d, l1clk, si, siclk, soclk ); | |
1315 | // RFM 05-14-2004 | |
1316 | // Level sensitive in SCAN_MODE | |
1317 | // Edge triggered when not in SCAN_MODE | |
1318 | ||
1319 | ||
1320 | parameter SIZE = 1; | |
1321 | ||
1322 | output q; | |
1323 | output so; | |
1324 | ||
1325 | input d; | |
1326 | input l1clk; | |
1327 | input si; | |
1328 | input siclk; | |
1329 | input soclk; | |
1330 | ||
1331 | reg q; | |
1332 | wire so; | |
1333 | wire l1clk, siclk, soclk; | |
1334 | ||
1335 | `ifdef SCAN_MODE | |
1336 | ||
1337 | reg l1; | |
1338 | `ifdef FAST_FLUSH | |
1339 | always @(posedge l1clk or posedge siclk ) begin | |
1340 | if (siclk) begin | |
1341 | q <= 1'b0; //pseudo flush reset | |
1342 | end else begin | |
1343 | q <= d; | |
1344 | end | |
1345 | end | |
1346 | `else | |
1347 | always @(l1clk or siclk or soclk or d or si) | |
1348 | begin | |
1349 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
1350 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1351 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1352 | ||
1353 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1354 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1355 | end | |
1356 | `endif | |
1357 | `else | |
1358 | wire si_unused; | |
1359 | wire siclk_unused; | |
1360 | wire soclk_unused; | |
1361 | assign si_unused = si; | |
1362 | assign siclk_unused = siclk; | |
1363 | assign soclk_unused = soclk; | |
1364 | ||
1365 | ||
1366 | `ifdef INITLATZERO | |
1367 | initial q = 1'b0; | |
1368 | `endif | |
1369 | ||
1370 | always @(posedge l1clk) | |
1371 | begin | |
1372 | if (!siclk && !soclk) q <= d; | |
1373 | else q <= 1'bx; | |
1374 | end | |
1375 | `endif | |
1376 | ||
1377 | assign so = q; | |
1378 | ||
1379 | endmodule // dff | |
1380 | module cl_sc1_clken_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk, clken); | |
1381 | // Level sensitive in SCAN_MODE | |
1382 | // Edge triggered when not in SCAN_MODE | |
1383 | // created by xl on 3/18 | |
1384 | ||
1385 | ||
1386 | ||
1387 | output q; | |
1388 | output so; | |
1389 | ||
1390 | input d; | |
1391 | input l1clk; | |
1392 | input si; | |
1393 | input siclk; | |
1394 | input soclk; | |
1395 | input clken; | |
1396 | reg q; | |
1397 | wire so; | |
1398 | wire l1clk, siclk, soclk; | |
1399 | ||
1400 | `ifdef SCAN_MODE | |
1401 | ||
1402 | reg l1; | |
1403 | ||
1404 | always @(l1clk or siclk or soclk or d or si) | |
1405 | begin | |
1406 | if (!l1clk && !siclk) l1 <= (d & clken ) | (q & !clken); // Load master with data | |
1407 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1408 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1409 | ||
1410 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1411 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1412 | end | |
1413 | ||
1414 | ||
1415 | `else | |
1416 | wire si_unused; | |
1417 | wire siclk_unused; | |
1418 | wire soclk_unused; | |
1419 | assign si_unused = si; | |
1420 | assign siclk_unused = siclk; | |
1421 | assign soclk_unused = soclk; | |
1422 | ||
1423 | ||
1424 | `ifdef INITLATZERO | |
1425 | ||
1426 | initial q = 1'b0; | |
1427 | `endif | |
1428 | ||
1429 | always @(posedge l1clk) | |
1430 | begin | |
1431 | if (!siclk && !soclk) q <= (d & clken ) | (q & !clken); | |
1432 | else q <= 1'bx; | |
1433 | end | |
1434 | `endif | |
1435 | ||
1436 | assign so = q; | |
1437 | ||
1438 | endmodule | |
1439 | module cl_sc1_msffmin_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
1440 | // RFM 05-14-2004 | |
1441 | // Level sensitive in SCAN_MODE | |
1442 | // Edge triggered when not in SCAN_MODE | |
1443 | ||
1444 | ||
1445 | parameter SIZE = 1; | |
1446 | ||
1447 | output q; | |
1448 | output so; | |
1449 | ||
1450 | input d; | |
1451 | input l1clk; | |
1452 | input si; | |
1453 | input siclk; | |
1454 | input soclk; | |
1455 | input reset; | |
1456 | reg q; | |
1457 | wire so; | |
1458 | wire l1clk, siclk, soclk; | |
1459 | ||
1460 | `ifdef SCAN_MODE | |
1461 | ||
1462 | reg l1; | |
1463 | `ifdef FAST_FLUSH | |
1464 | always @(l1clk or siclk or d ) // vcs optimized code | |
1465 | begin | |
1466 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1467 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
1468 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
1469 | l1 <= 1'b0; | |
1470 | q <= 1'b0; | |
1471 | end | |
1472 | end | |
1473 | `else | |
1474 | always @(l1clk or siclk or soclk or d or si) | |
1475 | begin | |
1476 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1477 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1478 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1479 | ||
1480 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1481 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1482 | end | |
1483 | `endif | |
1484 | `else | |
1485 | wire si_unused; | |
1486 | wire siclk_unused; | |
1487 | wire soclk_unused; | |
1488 | assign si_unused = si; | |
1489 | assign siclk_unused = siclk; | |
1490 | assign soclk_unused = soclk; | |
1491 | ||
1492 | ||
1493 | `ifdef INITLATZERO | |
1494 | initial q = 1'b0; | |
1495 | `endif | |
1496 | ||
1497 | always @(posedge l1clk) | |
1498 | begin | |
1499 | if (!siclk && !soclk) q <= (d&reset); | |
1500 | else q <= 1'bx; | |
1501 | end | |
1502 | `endif | |
1503 | ||
1504 | assign so = q; | |
1505 | ||
1506 | endmodule // dff | |
1507 | module cl_sc1_msffmin_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
1508 | // RFM 05-14-2004 | |
1509 | // Level sensitive in SCAN_MODE | |
1510 | // Edge triggered when not in SCAN_MODE | |
1511 | ||
1512 | ||
1513 | parameter SIZE = 1; | |
1514 | ||
1515 | output q; | |
1516 | output so; | |
1517 | ||
1518 | input d; | |
1519 | input l1clk; | |
1520 | input si; | |
1521 | input siclk; | |
1522 | input soclk; | |
1523 | input reset; | |
1524 | reg q; | |
1525 | wire so; | |
1526 | wire l1clk, siclk, soclk; | |
1527 | ||
1528 | `ifdef SCAN_MODE | |
1529 | ||
1530 | reg l1; | |
1531 | `ifdef FAST_FLUSH | |
1532 | always @(l1clk or siclk or d ) // vcs optimized code | |
1533 | begin | |
1534 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1535 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
1536 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
1537 | l1 <= 1'b0; | |
1538 | q <= 1'b0; | |
1539 | end | |
1540 | end | |
1541 | `else | |
1542 | always @(l1clk or siclk or soclk or d or si) | |
1543 | begin | |
1544 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1545 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1546 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1547 | ||
1548 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1549 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1550 | end | |
1551 | `endif | |
1552 | `else | |
1553 | wire si_unused; | |
1554 | wire siclk_unused; | |
1555 | wire soclk_unused; | |
1556 | assign si_unused = si; | |
1557 | assign siclk_unused = siclk; | |
1558 | assign soclk_unused = soclk; | |
1559 | ||
1560 | ||
1561 | `ifdef INITLATZERO | |
1562 | initial q = 1'b0; | |
1563 | `endif | |
1564 | ||
1565 | always @(posedge l1clk) | |
1566 | begin | |
1567 | if (!siclk && !soclk) q <= (d&reset); | |
1568 | else q <= 1'bx; | |
1569 | end | |
1570 | `endif | |
1571 | ||
1572 | assign so = q; | |
1573 | ||
1574 | endmodule // dff | |
1575 | module cl_sc1_msffmin_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
1576 | // RFM 05-14-2004 | |
1577 | // Level sensitive in SCAN_MODE | |
1578 | // Edge triggered when not in SCAN_MODE | |
1579 | ||
1580 | ||
1581 | parameter SIZE = 1; | |
1582 | ||
1583 | output q; | |
1584 | output so; | |
1585 | ||
1586 | input d; | |
1587 | input l1clk; | |
1588 | input si; | |
1589 | input siclk; | |
1590 | input soclk; | |
1591 | input reset; | |
1592 | reg q; | |
1593 | wire so; | |
1594 | wire l1clk, siclk, soclk; | |
1595 | ||
1596 | `ifdef SCAN_MODE | |
1597 | ||
1598 | reg l1; | |
1599 | `ifdef FAST_FLUSH | |
1600 | always @(l1clk or siclk or d ) // vcs optimized code | |
1601 | begin | |
1602 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1603 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
1604 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
1605 | l1 <= 1'b0; | |
1606 | q <= 1'b0; | |
1607 | end | |
1608 | end | |
1609 | `else | |
1610 | always @(l1clk or siclk or soclk or d or si) | |
1611 | begin | |
1612 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1613 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1614 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1615 | ||
1616 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1617 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1618 | end | |
1619 | `endif | |
1620 | `else | |
1621 | wire si_unused; | |
1622 | wire siclk_unused; | |
1623 | wire soclk_unused; | |
1624 | assign si_unused = si; | |
1625 | assign siclk_unused = siclk; | |
1626 | assign soclk_unused = soclk; | |
1627 | ||
1628 | ||
1629 | `ifdef INITLATZERO | |
1630 | initial q = 1'b0; | |
1631 | `endif | |
1632 | ||
1633 | always @(posedge l1clk) | |
1634 | begin | |
1635 | if (!siclk && !soclk) q <= (d&reset); | |
1636 | else q <= 1'bx; | |
1637 | end | |
1638 | `endif | |
1639 | ||
1640 | assign so = q; | |
1641 | ||
1642 | endmodule // dff | |
1643 | module cl_sc1_msffmin_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
1644 | // RFM 05-14-2004 | |
1645 | // Level sensitive in SCAN_MODE | |
1646 | // Edge triggered when not in SCAN_MODE | |
1647 | ||
1648 | ||
1649 | parameter SIZE = 1; | |
1650 | ||
1651 | output q; | |
1652 | output so; | |
1653 | ||
1654 | input d; | |
1655 | input l1clk; | |
1656 | input si; | |
1657 | input siclk; | |
1658 | input soclk; | |
1659 | input reset; | |
1660 | reg q; | |
1661 | wire so; | |
1662 | wire l1clk, siclk, soclk; | |
1663 | ||
1664 | `ifdef SCAN_MODE | |
1665 | ||
1666 | reg l1; | |
1667 | `ifdef FAST_FLUSH | |
1668 | always @(l1clk or siclk or d ) // vcs optimized code | |
1669 | begin | |
1670 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1671 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
1672 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
1673 | l1 <= 1'b0; | |
1674 | q <= 1'b0; | |
1675 | end | |
1676 | end | |
1677 | `else | |
1678 | always @(l1clk or siclk or soclk or d or si) | |
1679 | begin | |
1680 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1681 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1682 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1683 | ||
1684 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1685 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1686 | end | |
1687 | `endif | |
1688 | `else | |
1689 | wire si_unused; | |
1690 | wire siclk_unused; | |
1691 | wire soclk_unused; | |
1692 | assign si_unused = si; | |
1693 | assign siclk_unused = siclk; | |
1694 | assign soclk_unused = soclk; | |
1695 | ||
1696 | ||
1697 | `ifdef INITLATZERO | |
1698 | initial q = 1'b0; | |
1699 | `endif | |
1700 | ||
1701 | always @(posedge l1clk) | |
1702 | begin | |
1703 | if (!siclk && !soclk) q <= (d&reset); | |
1704 | else q <= 1'bx; | |
1705 | end | |
1706 | `endif | |
1707 | ||
1708 | assign so = q; | |
1709 | ||
1710 | endmodule // dff | |
1711 | module cl_sc1_msffmin_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
1712 | // RFM 05-14-2004 | |
1713 | // Level sensitive in SCAN_MODE | |
1714 | // Edge triggered when not in SCAN_MODE | |
1715 | ||
1716 | ||
1717 | parameter SIZE = 1; | |
1718 | ||
1719 | output q; | |
1720 | output so; | |
1721 | ||
1722 | input d; | |
1723 | input l1clk; | |
1724 | input si; | |
1725 | input siclk; | |
1726 | input soclk; | |
1727 | input reset; | |
1728 | reg q; | |
1729 | wire so; | |
1730 | wire l1clk, siclk, soclk; | |
1731 | ||
1732 | `ifdef SCAN_MODE | |
1733 | ||
1734 | reg l1; | |
1735 | `ifdef FAST_FLUSH | |
1736 | always @(l1clk or siclk or d ) // vcs optimized code | |
1737 | begin | |
1738 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1739 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
1740 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
1741 | l1 <= 1'b0; | |
1742 | q <= 1'b0; | |
1743 | end | |
1744 | end | |
1745 | `else | |
1746 | always @(l1clk or siclk or soclk or d or si) | |
1747 | begin | |
1748 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1749 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1750 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1751 | ||
1752 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1753 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1754 | end | |
1755 | `endif | |
1756 | `else | |
1757 | wire si_unused; | |
1758 | wire siclk_unused; | |
1759 | wire soclk_unused; | |
1760 | assign si_unused = si; | |
1761 | assign siclk_unused = siclk; | |
1762 | assign soclk_unused = soclk; | |
1763 | ||
1764 | ||
1765 | `ifdef INITLATZERO | |
1766 | initial q = 1'b0; | |
1767 | `endif | |
1768 | ||
1769 | always @(posedge l1clk) | |
1770 | begin | |
1771 | if (!siclk && !soclk) q <= (d&reset); | |
1772 | else q <= 1'bx; | |
1773 | end | |
1774 | `endif | |
1775 | ||
1776 | assign so = q; | |
1777 | ||
1778 | endmodule // dff | |
1779 | module cl_sc1_bsac_cell_4x(q, so, d, l1clk, si, siclk, soclk, updateclk, | |
1780 | ac_mode, ac_test_signal); | |
1781 | output q; | |
1782 | output so; | |
1783 | ||
1784 | input d, ac_test_signal; | |
1785 | input l1clk; | |
1786 | input si; | |
1787 | input siclk; | |
1788 | input soclk; | |
1789 | input updateclk, ac_mode; | |
1790 | ||
1791 | reg q; | |
1792 | reg so; | |
1793 | wire l1clk, siclk, soclk, updateclk; | |
1794 | ||
1795 | ||
1796 | reg l1, qm; | |
1797 | ||
1798 | always @(l1clk or siclk or soclk or d or si) | |
1799 | begin | |
1800 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
1801 | if ( l1clk && siclk) l1 <= si; // Load master with | |
1802 | // scan or flush | |
1803 | if (!l1clk && siclk) l1 <= 1'bx; // Conflict between | |
1804 | // data and scan | |
1805 | if ( l1clk && !soclk) so <= l1; // Load slave with | |
1806 | // master data | |
1807 | if ( l1clk && siclk && !soclk) so <= si; // Flush | |
1808 | end | |
1809 | ||
1810 | initial qm = 1'b0; | |
1811 | ||
1812 | always@(updateclk or l1) | |
1813 | begin | |
1814 | if(updateclk) qm <=l1; | |
1815 | end | |
1816 | always@(ac_mode or qm or ac_test_signal) | |
1817 | begin | |
1818 | if(ac_mode==0) q=qm; | |
1819 | else q=qm ^ ac_test_signal; | |
1820 | end | |
1821 | endmodule | |
1822 | module cl_sc1_blatch_4x ( latout, so, d, l1clk, si, siclk, soclk); | |
1823 | ||
1824 | output latout; | |
1825 | output so; | |
1826 | input d; | |
1827 | input l1clk; | |
1828 | input si; | |
1829 | input siclk; | |
1830 | input soclk; | |
1831 | ||
1832 | ||
1833 | wire so; | |
1834 | reg s, m; | |
1835 | ||
1836 | `ifdef SCAN_MODE | |
1837 | ||
1838 | always @(l1clk or siclk or soclk or d or si) begin | |
1839 | ||
1840 | if (!l1clk && !siclk) m <= d; // Load master with data | |
1841 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush | |
1842 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan | |
1843 | ||
1844 | if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data | |
1845 | else if (l1clk && siclk && !soclk) s <= si; // Flush | |
1846 | end | |
1847 | ||
1848 | `else | |
1849 | wire si_unused = si; | |
1850 | `ifdef INITLATZERO | |
1851 | ||
1852 | ||
1853 | initial m = 1'b0; | |
1854 | `endif | |
1855 | ||
1856 | ||
1857 | always @(l1clk or d or si or siclk) begin | |
1858 | if(siclk==0 && l1clk==0) m = d; | |
1859 | else if(siclk && !l1clk) m = 1'bx; | |
1860 | if(siclk && l1clk) m = si; | |
1861 | if(l1clk && !soclk) s = m; | |
1862 | end | |
1863 | ||
1864 | `endif | |
1865 | ||
1866 | assign latout = m; | |
1867 | assign so = s; | |
1868 | ||
1869 | ||
1870 | endmodule | |
1871 | ||
1872 | ||
1873 | ||
1874 | ||
1875 | ||
1876 | module cl_sc1_alatch_4x ( q, so, d, l1clk, si, siclk, soclk, se ); | |
1877 | ||
1878 | ||
1879 | ||
1880 | ||
1881 | ||
1882 | output q; | |
1883 | output so; | |
1884 | ||
1885 | input d; | |
1886 | input l1clk; | |
1887 | input si; | |
1888 | input siclk; | |
1889 | input soclk; | |
1890 | input se; | |
1891 | ||
1892 | reg q; | |
1893 | wire so; | |
1894 | wire l1clk, siclk, soclk; | |
1895 | ||
1896 | ||
1897 | ||
1898 | reg l1; | |
1899 | ||
1900 | always @(l1clk or siclk or soclk or d or si or se) | |
1901 | begin | |
1902 | ||
1903 | if (siclk) l1 <= si; // Load master with scan or flush | |
1904 | ||
1905 | if(se && !soclk && l1clk && siclk) q <= si; | |
1906 | else if ( se && !soclk && l1clk) q <= l1; | |
1907 | else if ( !soclk && l1clk) q <= d; | |
1908 | end | |
1909 | ||
1910 | ||
1911 | ||
1912 | ||
1913 | `ifdef INITLATZERO | |
1914 | initial q = 1'b0; | |
1915 | `endif | |
1916 | ||
1917 | ||
1918 | ||
1919 | assign so = q; | |
1920 | ||
1921 | endmodule // dff | |
1922 | module cl_sc1_clken_msff_4x ( q, so, d, l1clk, si, siclk, soclk, clken); | |
1923 | // Level sensitive in SCAN_MODE | |
1924 | // Edge triggered when not in SCAN_MODE | |
1925 | // created by xl on 3/18 | |
1926 | ||
1927 | ||
1928 | ||
1929 | output q; | |
1930 | output so; | |
1931 | ||
1932 | input d; | |
1933 | input l1clk; | |
1934 | input si; | |
1935 | input siclk; | |
1936 | input soclk; | |
1937 | input clken; | |
1938 | reg q; | |
1939 | wire so; | |
1940 | wire l1clk, siclk, soclk; | |
1941 | ||
1942 | `ifdef SCAN_MODE | |
1943 | ||
1944 | reg l1; | |
1945 | ||
1946 | always @(l1clk or siclk or soclk or d or si) | |
1947 | begin | |
1948 | if (!l1clk && !siclk) l1 <= (d & clken ) | (q & !clken); // Load master with data | |
1949 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1950 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1951 | ||
1952 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1953 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1954 | end | |
1955 | ||
1956 | ||
1957 | `else | |
1958 | wire si_unused; | |
1959 | wire siclk_unused; | |
1960 | wire soclk_unused; | |
1961 | assign si_unused = si; | |
1962 | assign siclk_unused = siclk; | |
1963 | assign soclk_unused = soclk; | |
1964 | ||
1965 | ||
1966 | `ifdef INITLATZERO | |
1967 | ||
1968 | initial q = 1'b0; | |
1969 | `endif | |
1970 | ||
1971 | always @(posedge l1clk) | |
1972 | begin | |
1973 | if (!siclk && !soclk) q <= (d & clken ) | (q & !clken); | |
1974 | else q <= 1'bx; | |
1975 | end | |
1976 | `endif | |
1977 | ||
1978 | assign so = q; | |
1979 | ||
1980 | endmodule | |
1981 | ||
1982 | module cl_sc1_msff_arst_4x ( q, so, d, l1clk, si, siclk, soclk, reset ); | |
1983 | // RFM 05-14-2004 | |
1984 | // Level sensitive in SCAN_MODE | |
1985 | // Edge triggered when not in SCAN_MODE | |
1986 | ||
1987 | ||
1988 | parameter SIZE = 1; | |
1989 | ||
1990 | output q; | |
1991 | output so; | |
1992 | ||
1993 | input d; | |
1994 | input l1clk; | |
1995 | input si; | |
1996 | input siclk; | |
1997 | input soclk; | |
1998 | input reset; | |
1999 | ||
2000 | reg q; | |
2001 | wire so; | |
2002 | wire l1clk, siclk, soclk; | |
2003 | ||
2004 | `ifdef SCAN_MODE | |
2005 | ||
2006 | reg l1; | |
2007 | ||
2008 | always @(l1clk or siclk or soclk or d or si or reset) | |
2009 | begin | |
2010 | if (reset ) l1 <= 1'b0; | |
2011 | else if (!l1clk && !siclk) l1 <= d; | |
2012 | else if ( l1clk && siclk) l1 <= si; | |
2013 | else if (!l1clk && siclk) l1 <= 1'bx; | |
2014 | ||
2015 | if (reset) q <= 1'b0; | |
2016 | else if ( l1clk && !siclk && !soclk) q <= l1; | |
2017 | else if ( l1clk && siclk && !soclk) q <= si; | |
2018 | ||
2019 | end | |
2020 | ||
2021 | ||
2022 | `else | |
2023 | wire si_unused; | |
2024 | wire siclk_unused; | |
2025 | wire soclk_unused; | |
2026 | assign si_unused = si; | |
2027 | assign siclk_unused = siclk; | |
2028 | assign soclk_unused = soclk; | |
2029 | ||
2030 | ||
2031 | `ifdef INITLATZERO | |
2032 | initial q = 1'b0; | |
2033 | `endif | |
2034 | ||
2035 | always @(posedge l1clk or posedge reset) | |
2036 | begin | |
2037 | ||
2038 | if ( reset) q <= 1'b0; | |
2039 | else if (!siclk && !soclk ) q <= d; | |
2040 | else q <= 1'bx; | |
2041 | end | |
2042 | `endif | |
2043 | ||
2044 | assign so = q; | |
2045 | ||
2046 | endmodule // dff | |
2047 | ||
2048 | ||
2049 | ||
2050 | ||
2051 | module cl_sc1_aomux2_12x ( | |
2052 | in0, | |
2053 | in1, | |
2054 | sel0, | |
2055 | sel1, | |
2056 | out | |
2057 | ); | |
2058 | input in0; | |
2059 | input in1; | |
2060 | input sel0; | |
2061 | input sel1; | |
2062 | output out; | |
2063 | ||
2064 | `ifdef LIB | |
2065 | assign out = ((sel0 & in0) | | |
2066 | (sel1 & in1)); | |
2067 | `endif | |
2068 | ||
2069 | ||
2070 | endmodule | |
2071 | module cl_sc1_aomux2_16x ( | |
2072 | in0, | |
2073 | in1, | |
2074 | sel0, | |
2075 | sel1, | |
2076 | out | |
2077 | ); | |
2078 | input in0; | |
2079 | input in1; | |
2080 | input sel0; | |
2081 | input sel1; | |
2082 | output out; | |
2083 | ||
2084 | `ifdef LIB | |
2085 | assign out = ((sel0 & in0) | | |
2086 | (sel1 & in1)); | |
2087 | `endif | |
2088 | ||
2089 | ||
2090 | endmodule | |
2091 | module cl_sc1_aomux2_1x ( | |
2092 | in0, | |
2093 | in1, | |
2094 | sel0, | |
2095 | sel1, | |
2096 | out | |
2097 | ); | |
2098 | input in0; | |
2099 | input in1; | |
2100 | input sel0; | |
2101 | input sel1; | |
2102 | output out; | |
2103 | ||
2104 | `ifdef LIB | |
2105 | assign out = ((sel0 & in0) | | |
2106 | (sel1 & in1)); | |
2107 | `endif | |
2108 | ||
2109 | ||
2110 | endmodule | |
2111 | module cl_sc1_aomux2_2x ( | |
2112 | in0, | |
2113 | in1, | |
2114 | sel0, | |
2115 | sel1, | |
2116 | out | |
2117 | ); | |
2118 | input in0; | |
2119 | input in1; | |
2120 | input sel0; | |
2121 | input sel1; | |
2122 | output out; | |
2123 | ||
2124 | `ifdef LIB | |
2125 | assign out = ((sel0 & in0) | | |
2126 | (sel1 & in1)); | |
2127 | `endif | |
2128 | ||
2129 | ||
2130 | endmodule | |
2131 | module cl_sc1_aomux2_4x ( | |
2132 | in0, | |
2133 | in1, | |
2134 | sel0, | |
2135 | sel1, | |
2136 | out | |
2137 | ); | |
2138 | input in0; | |
2139 | input in1; | |
2140 | input sel0; | |
2141 | input sel1; | |
2142 | output out; | |
2143 | ||
2144 | `ifdef LIB | |
2145 | assign out = ((sel0 & in0) | | |
2146 | (sel1 & in1)); | |
2147 | `endif | |
2148 | ||
2149 | ||
2150 | endmodule | |
2151 | module cl_sc1_aomux2_6x ( | |
2152 | in0, | |
2153 | in1, | |
2154 | sel0, | |
2155 | sel1, | |
2156 | out | |
2157 | ); | |
2158 | input in0; | |
2159 | input in1; | |
2160 | input sel0; | |
2161 | input sel1; | |
2162 | output out; | |
2163 | ||
2164 | `ifdef LIB | |
2165 | assign out = ((sel0 & in0) | | |
2166 | (sel1 & in1)); | |
2167 | `endif | |
2168 | ||
2169 | ||
2170 | endmodule | |
2171 | module cl_sc1_aomux2_8x ( | |
2172 | in0, | |
2173 | in1, | |
2174 | sel0, | |
2175 | sel1, | |
2176 | out | |
2177 | ); | |
2178 | input in0; | |
2179 | input in1; | |
2180 | input sel0; | |
2181 | input sel1; | |
2182 | output out; | |
2183 | ||
2184 | `ifdef LIB | |
2185 | assign out = ((sel0 & in0) | | |
2186 | (sel1 & in1)); | |
2187 | `endif | |
2188 | ||
2189 | ||
2190 | endmodule | |
2191 | module cl_sc1_aomux3_12x ( | |
2192 | in0, | |
2193 | in1, | |
2194 | in2, | |
2195 | sel0, | |
2196 | sel1, | |
2197 | sel2, | |
2198 | out | |
2199 | ); | |
2200 | input in0; | |
2201 | input in1; | |
2202 | input in2; | |
2203 | input sel0; | |
2204 | input sel1; | |
2205 | input sel2; | |
2206 | output out; | |
2207 | ||
2208 | `ifdef LIB | |
2209 | assign out = ((sel0 & in0) | | |
2210 | (sel1 & in1) | | |
2211 | (sel2 & in2)); | |
2212 | `endif | |
2213 | ||
2214 | endmodule | |
2215 | module cl_sc1_aomux3_16x ( | |
2216 | in0, | |
2217 | in1, | |
2218 | in2, | |
2219 | sel0, | |
2220 | sel1, | |
2221 | sel2, | |
2222 | out | |
2223 | ); | |
2224 | input in0; | |
2225 | input in1; | |
2226 | input in2; | |
2227 | input sel0; | |
2228 | input sel1; | |
2229 | input sel2; | |
2230 | output out; | |
2231 | ||
2232 | `ifdef LIB | |
2233 | assign out = ((sel0 & in0) | | |
2234 | (sel1 & in1) | | |
2235 | (sel2 & in2)); | |
2236 | `endif | |
2237 | ||
2238 | endmodule | |
2239 | module cl_sc1_aomux3_1x ( | |
2240 | in0, | |
2241 | in1, | |
2242 | in2, | |
2243 | sel0, | |
2244 | sel1, | |
2245 | sel2, | |
2246 | out | |
2247 | ); | |
2248 | input in0; | |
2249 | input in1; | |
2250 | input in2; | |
2251 | input sel0; | |
2252 | input sel1; | |
2253 | input sel2; | |
2254 | output out; | |
2255 | ||
2256 | `ifdef LIB | |
2257 | assign out = ((sel0 & in0) | | |
2258 | (sel1 & in1) | | |
2259 | (sel2 & in2)); | |
2260 | `endif | |
2261 | ||
2262 | endmodule | |
2263 | module cl_sc1_aomux3_2x ( | |
2264 | in0, | |
2265 | in1, | |
2266 | in2, | |
2267 | sel0, | |
2268 | sel1, | |
2269 | sel2, | |
2270 | out | |
2271 | ); | |
2272 | input in0; | |
2273 | input in1; | |
2274 | input in2; | |
2275 | input sel0; | |
2276 | input sel1; | |
2277 | input sel2; | |
2278 | output out; | |
2279 | ||
2280 | `ifdef LIB | |
2281 | assign out = ((sel0 & in0) | | |
2282 | (sel1 & in1) | | |
2283 | (sel2 & in2)); | |
2284 | `endif | |
2285 | ||
2286 | endmodule | |
2287 | module cl_sc1_aomux3_4x ( | |
2288 | in0, | |
2289 | in1, | |
2290 | in2, | |
2291 | sel0, | |
2292 | sel1, | |
2293 | sel2, | |
2294 | out | |
2295 | ); | |
2296 | input in0; | |
2297 | input in1; | |
2298 | input in2; | |
2299 | input sel0; | |
2300 | input sel1; | |
2301 | input sel2; | |
2302 | output out; | |
2303 | ||
2304 | `ifdef LIB | |
2305 | assign out = ((sel0 & in0) | | |
2306 | (sel1 & in1) | | |
2307 | (sel2 & in2)); | |
2308 | `endif | |
2309 | ||
2310 | endmodule | |
2311 | module cl_sc1_aomux3_6x ( | |
2312 | in0, | |
2313 | in1, | |
2314 | in2, | |
2315 | sel0, | |
2316 | sel1, | |
2317 | sel2, | |
2318 | out | |
2319 | ); | |
2320 | input in0; | |
2321 | input in1; | |
2322 | input in2; | |
2323 | input sel0; | |
2324 | input sel1; | |
2325 | input sel2; | |
2326 | output out; | |
2327 | ||
2328 | `ifdef LIB | |
2329 | assign out = ((sel0 & in0) | | |
2330 | (sel1 & in1) | | |
2331 | (sel2 & in2)); | |
2332 | `endif | |
2333 | ||
2334 | endmodule | |
2335 | module cl_sc1_aomux3_8x ( | |
2336 | in0, | |
2337 | in1, | |
2338 | in2, | |
2339 | sel0, | |
2340 | sel1, | |
2341 | sel2, | |
2342 | out | |
2343 | ); | |
2344 | input in0; | |
2345 | input in1; | |
2346 | input in2; | |
2347 | input sel0; | |
2348 | input sel1; | |
2349 | input sel2; | |
2350 | output out; | |
2351 | ||
2352 | `ifdef LIB | |
2353 | assign out = ((sel0 & in0) | | |
2354 | (sel1 & in1) | | |
2355 | (sel2 & in2)); | |
2356 | `endif | |
2357 | ||
2358 | endmodule | |
2359 | module cl_sc1_aomux4_12x ( | |
2360 | in0, | |
2361 | in1, | |
2362 | in2, | |
2363 | in3, | |
2364 | sel0, | |
2365 | sel1, | |
2366 | sel2, | |
2367 | sel3, | |
2368 | out | |
2369 | ); | |
2370 | input in0; | |
2371 | input in1; | |
2372 | input in2; | |
2373 | input in3; | |
2374 | input sel0; | |
2375 | input sel1; | |
2376 | input sel2; | |
2377 | input sel3; | |
2378 | output out; | |
2379 | ||
2380 | `ifdef LIB | |
2381 | assign out = ((sel0 & in0) | | |
2382 | (sel1 & in1) | | |
2383 | (sel2 & in2) | | |
2384 | (sel3 & in3)); | |
2385 | `endif | |
2386 | ||
2387 | endmodule | |
2388 | module cl_sc1_aomux4_16x ( | |
2389 | in0, | |
2390 | in1, | |
2391 | in2, | |
2392 | in3, | |
2393 | sel0, | |
2394 | sel1, | |
2395 | sel2, | |
2396 | sel3, | |
2397 | out | |
2398 | ); | |
2399 | input in0; | |
2400 | input in1; | |
2401 | input in2; | |
2402 | input in3; | |
2403 | input sel0; | |
2404 | input sel1; | |
2405 | input sel2; | |
2406 | input sel3; | |
2407 | output out; | |
2408 | ||
2409 | `ifdef LIB | |
2410 | assign out = ((sel0 & in0) | | |
2411 | (sel1 & in1) | | |
2412 | (sel2 & in2) | | |
2413 | (sel3 & in3)); | |
2414 | `endif | |
2415 | ||
2416 | endmodule | |
2417 | module cl_sc1_aomux4_1x ( | |
2418 | in0, | |
2419 | in1, | |
2420 | in2, | |
2421 | in3, | |
2422 | sel0, | |
2423 | sel1, | |
2424 | sel2, | |
2425 | sel3, | |
2426 | out | |
2427 | ); | |
2428 | input in0; | |
2429 | input in1; | |
2430 | input in2; | |
2431 | input in3; | |
2432 | input sel0; | |
2433 | input sel1; | |
2434 | input sel2; | |
2435 | input sel3; | |
2436 | output out; | |
2437 | ||
2438 | `ifdef LIB | |
2439 | assign out = ((sel0 & in0) | | |
2440 | (sel1 & in1) | | |
2441 | (sel2 & in2) | | |
2442 | (sel3 & in3)); | |
2443 | `endif | |
2444 | ||
2445 | endmodule | |
2446 | module cl_sc1_aomux4_2x ( | |
2447 | in0, | |
2448 | in1, | |
2449 | in2, | |
2450 | in3, | |
2451 | sel0, | |
2452 | sel1, | |
2453 | sel2, | |
2454 | sel3, | |
2455 | out | |
2456 | ); | |
2457 | input in0; | |
2458 | input in1; | |
2459 | input in2; | |
2460 | input in3; | |
2461 | input sel0; | |
2462 | input sel1; | |
2463 | input sel2; | |
2464 | input sel3; | |
2465 | output out; | |
2466 | ||
2467 | `ifdef LIB | |
2468 | assign out = ((sel0 & in0) | | |
2469 | (sel1 & in1) | | |
2470 | (sel2 & in2) | | |
2471 | (sel3 & in3)); | |
2472 | `endif | |
2473 | ||
2474 | endmodule | |
2475 | module cl_sc1_aomux4_4x ( | |
2476 | in0, | |
2477 | in1, | |
2478 | in2, | |
2479 | in3, | |
2480 | sel0, | |
2481 | sel1, | |
2482 | sel2, | |
2483 | sel3, | |
2484 | out | |
2485 | ); | |
2486 | input in0; | |
2487 | input in1; | |
2488 | input in2; | |
2489 | input in3; | |
2490 | input sel0; | |
2491 | input sel1; | |
2492 | input sel2; | |
2493 | input sel3; | |
2494 | output out; | |
2495 | ||
2496 | `ifdef LIB | |
2497 | assign out = ((sel0 & in0) | | |
2498 | (sel1 & in1) | | |
2499 | (sel2 & in2) | | |
2500 | (sel3 & in3)); | |
2501 | `endif | |
2502 | ||
2503 | endmodule | |
2504 | module cl_sc1_aomux4_6x ( | |
2505 | in0, | |
2506 | in1, | |
2507 | in2, | |
2508 | in3, | |
2509 | sel0, | |
2510 | sel1, | |
2511 | sel2, | |
2512 | sel3, | |
2513 | out | |
2514 | ); | |
2515 | input in0; | |
2516 | input in1; | |
2517 | input in2; | |
2518 | input in3; | |
2519 | input sel0; | |
2520 | input sel1; | |
2521 | input sel2; | |
2522 | input sel3; | |
2523 | output out; | |
2524 | ||
2525 | `ifdef LIB | |
2526 | assign out = ((sel0 & in0) | | |
2527 | (sel1 & in1) | | |
2528 | (sel2 & in2) | | |
2529 | (sel3 & in3)); | |
2530 | `endif | |
2531 | ||
2532 | endmodule | |
2533 | module cl_sc1_aomux4_8x ( | |
2534 | in0, | |
2535 | in1, | |
2536 | in2, | |
2537 | in3, | |
2538 | sel0, | |
2539 | sel1, | |
2540 | sel2, | |
2541 | sel3, | |
2542 | out | |
2543 | ); | |
2544 | input in0; | |
2545 | input in1; | |
2546 | input in2; | |
2547 | input in3; | |
2548 | input sel0; | |
2549 | input sel1; | |
2550 | input sel2; | |
2551 | input sel3; | |
2552 | output out; | |
2553 | ||
2554 | `ifdef LIB | |
2555 | assign out = ((sel0 & in0) | | |
2556 | (sel1 & in1) | | |
2557 | (sel2 & in2) | | |
2558 | (sel3 & in3)); | |
2559 | `endif | |
2560 | ||
2561 | endmodule | |
2562 | module cl_sc1_aomux5_12x ( | |
2563 | in0, | |
2564 | in1, | |
2565 | in2, | |
2566 | in3, | |
2567 | in4, | |
2568 | sel0, | |
2569 | sel1, | |
2570 | sel2, | |
2571 | sel3, | |
2572 | sel4, | |
2573 | out | |
2574 | ); | |
2575 | input in0; | |
2576 | input in1; | |
2577 | input in2; | |
2578 | input in3; | |
2579 | input in4; | |
2580 | input sel0; | |
2581 | input sel1; | |
2582 | input sel2; | |
2583 | input sel3; | |
2584 | input sel4; | |
2585 | output out; | |
2586 | ||
2587 | `ifdef LIB | |
2588 | assign out = ((sel0 & in0) | | |
2589 | (sel1 & in1) | | |
2590 | (sel2 & in2) | | |
2591 | (sel3 & in3) | | |
2592 | (sel4 & in4)); | |
2593 | `endif | |
2594 | ||
2595 | endmodule | |
2596 | module cl_sc1_aomux5_16x ( | |
2597 | in0, | |
2598 | in1, | |
2599 | in2, | |
2600 | in3, | |
2601 | in4, | |
2602 | sel0, | |
2603 | sel1, | |
2604 | sel2, | |
2605 | sel3, | |
2606 | sel4, | |
2607 | out | |
2608 | ); | |
2609 | input in0; | |
2610 | input in1; | |
2611 | input in2; | |
2612 | input in3; | |
2613 | input in4; | |
2614 | input sel0; | |
2615 | input sel1; | |
2616 | input sel2; | |
2617 | input sel3; | |
2618 | input sel4; | |
2619 | output out; | |
2620 | ||
2621 | `ifdef LIB | |
2622 | assign out = ((sel0 & in0) | | |
2623 | (sel1 & in1) | | |
2624 | (sel2 & in2) | | |
2625 | (sel3 & in3) | | |
2626 | (sel4 & in4)); | |
2627 | `endif | |
2628 | ||
2629 | endmodule | |
2630 | module cl_sc1_aomux5_1x ( | |
2631 | in0, | |
2632 | in1, | |
2633 | in2, | |
2634 | in3, | |
2635 | in4, | |
2636 | sel0, | |
2637 | sel1, | |
2638 | sel2, | |
2639 | sel3, | |
2640 | sel4, | |
2641 | out | |
2642 | ); | |
2643 | input in0; | |
2644 | input in1; | |
2645 | input in2; | |
2646 | input in3; | |
2647 | input in4; | |
2648 | input sel0; | |
2649 | input sel1; | |
2650 | input sel2; | |
2651 | input sel3; | |
2652 | input sel4; | |
2653 | output out; | |
2654 | ||
2655 | `ifdef LIB | |
2656 | assign out = ((sel0 & in0) | | |
2657 | (sel1 & in1) | | |
2658 | (sel2 & in2) | | |
2659 | (sel3 & in3) | | |
2660 | (sel4 & in4)); | |
2661 | `endif | |
2662 | ||
2663 | endmodule | |
2664 | module cl_sc1_aomux5_2x ( | |
2665 | in0, | |
2666 | in1, | |
2667 | in2, | |
2668 | in3, | |
2669 | in4, | |
2670 | sel0, | |
2671 | sel1, | |
2672 | sel2, | |
2673 | sel3, | |
2674 | sel4, | |
2675 | out | |
2676 | ); | |
2677 | input in0; | |
2678 | input in1; | |
2679 | input in2; | |
2680 | input in3; | |
2681 | input in4; | |
2682 | input sel0; | |
2683 | input sel1; | |
2684 | input sel2; | |
2685 | input sel3; | |
2686 | input sel4; | |
2687 | output out; | |
2688 | ||
2689 | `ifdef LIB | |
2690 | assign out = ((sel0 & in0) | | |
2691 | (sel1 & in1) | | |
2692 | (sel2 & in2) | | |
2693 | (sel3 & in3) | | |
2694 | (sel4 & in4)); | |
2695 | `endif | |
2696 | ||
2697 | endmodule | |
2698 | module cl_sc1_aomux5_4x ( | |
2699 | in0, | |
2700 | in1, | |
2701 | in2, | |
2702 | in3, | |
2703 | in4, | |
2704 | sel0, | |
2705 | sel1, | |
2706 | sel2, | |
2707 | sel3, | |
2708 | sel4, | |
2709 | out | |
2710 | ); | |
2711 | input in0; | |
2712 | input in1; | |
2713 | input in2; | |
2714 | input in3; | |
2715 | input in4; | |
2716 | input sel0; | |
2717 | input sel1; | |
2718 | input sel2; | |
2719 | input sel3; | |
2720 | input sel4; | |
2721 | output out; | |
2722 | ||
2723 | `ifdef LIB | |
2724 | assign out = ((sel0 & in0) | | |
2725 | (sel1 & in1) | | |
2726 | (sel2 & in2) | | |
2727 | (sel3 & in3) | | |
2728 | (sel4 & in4)); | |
2729 | `endif | |
2730 | ||
2731 | endmodule | |
2732 | module cl_sc1_aomux5_6x ( | |
2733 | in0, | |
2734 | in1, | |
2735 | in2, | |
2736 | in3, | |
2737 | in4, | |
2738 | sel0, | |
2739 | sel1, | |
2740 | sel2, | |
2741 | sel3, | |
2742 | sel4, | |
2743 | out | |
2744 | ); | |
2745 | input in0; | |
2746 | input in1; | |
2747 | input in2; | |
2748 | input in3; | |
2749 | input in4; | |
2750 | input sel0; | |
2751 | input sel1; | |
2752 | input sel2; | |
2753 | input sel3; | |
2754 | input sel4; | |
2755 | output out; | |
2756 | ||
2757 | `ifdef LIB | |
2758 | assign out = ((sel0 & in0) | | |
2759 | (sel1 & in1) | | |
2760 | (sel2 & in2) | | |
2761 | (sel3 & in3) | | |
2762 | (sel4 & in4)); | |
2763 | `endif | |
2764 | ||
2765 | endmodule | |
2766 | module cl_sc1_aomux5_8x ( | |
2767 | in0, | |
2768 | in1, | |
2769 | in2, | |
2770 | in3, | |
2771 | in4, | |
2772 | sel0, | |
2773 | sel1, | |
2774 | sel2, | |
2775 | sel3, | |
2776 | sel4, | |
2777 | out | |
2778 | ); | |
2779 | input in0; | |
2780 | input in1; | |
2781 | input in2; | |
2782 | input in3; | |
2783 | input in4; | |
2784 | input sel0; | |
2785 | input sel1; | |
2786 | input sel2; | |
2787 | input sel3; | |
2788 | input sel4; | |
2789 | output out; | |
2790 | ||
2791 | `ifdef LIB | |
2792 | assign out = ((sel0 & in0) | | |
2793 | (sel1 & in1) | | |
2794 | (sel2 & in2) | | |
2795 | (sel3 & in3) | | |
2796 | (sel4 & in4)); | |
2797 | `endif | |
2798 | ||
2799 | endmodule | |
2800 | module cl_sc1_aomux6_12x ( | |
2801 | in0, | |
2802 | in1, | |
2803 | in2, | |
2804 | in3, | |
2805 | in4, | |
2806 | in5, | |
2807 | sel0, | |
2808 | sel1, | |
2809 | sel2, | |
2810 | sel3, | |
2811 | sel4, | |
2812 | sel5, | |
2813 | out | |
2814 | ); | |
2815 | input in0; | |
2816 | input in1; | |
2817 | input in2; | |
2818 | input in3; | |
2819 | input in4; | |
2820 | input in5; | |
2821 | input sel0; | |
2822 | input sel1; | |
2823 | input sel2; | |
2824 | input sel3; | |
2825 | input sel4; | |
2826 | input sel5; | |
2827 | output out; | |
2828 | ||
2829 | `ifdef LIB | |
2830 | assign out = ((sel0 & in0) | | |
2831 | (sel1 & in1) | | |
2832 | (sel2 & in2) | | |
2833 | (sel3 & in3) | | |
2834 | (sel4 & in4) | | |
2835 | (sel5 & in5)); | |
2836 | `endif | |
2837 | ||
2838 | endmodule | |
2839 | module cl_sc1_aomux6_16x ( | |
2840 | in0, | |
2841 | in1, | |
2842 | in2, | |
2843 | in3, | |
2844 | in4, | |
2845 | in5, | |
2846 | sel0, | |
2847 | sel1, | |
2848 | sel2, | |
2849 | sel3, | |
2850 | sel4, | |
2851 | sel5, | |
2852 | out | |
2853 | ); | |
2854 | input in0; | |
2855 | input in1; | |
2856 | input in2; | |
2857 | input in3; | |
2858 | input in4; | |
2859 | input in5; | |
2860 | input sel0; | |
2861 | input sel1; | |
2862 | input sel2; | |
2863 | input sel3; | |
2864 | input sel4; | |
2865 | input sel5; | |
2866 | output out; | |
2867 | ||
2868 | `ifdef LIB | |
2869 | assign out = ((sel0 & in0) | | |
2870 | (sel1 & in1) | | |
2871 | (sel2 & in2) | | |
2872 | (sel3 & in3) | | |
2873 | (sel4 & in4) | | |
2874 | (sel5 & in5)); | |
2875 | `endif | |
2876 | ||
2877 | endmodule | |
2878 | module cl_sc1_aomux6_1x ( | |
2879 | in0, | |
2880 | in1, | |
2881 | in2, | |
2882 | in3, | |
2883 | in4, | |
2884 | in5, | |
2885 | sel0, | |
2886 | sel1, | |
2887 | sel2, | |
2888 | sel3, | |
2889 | sel4, | |
2890 | sel5, | |
2891 | out | |
2892 | ); | |
2893 | input in0; | |
2894 | input in1; | |
2895 | input in2; | |
2896 | input in3; | |
2897 | input in4; | |
2898 | input in5; | |
2899 | input sel0; | |
2900 | input sel1; | |
2901 | input sel2; | |
2902 | input sel3; | |
2903 | input sel4; | |
2904 | input sel5; | |
2905 | output out; | |
2906 | ||
2907 | `ifdef LIB | |
2908 | assign out = ((sel0 & in0) | | |
2909 | (sel1 & in1) | | |
2910 | (sel2 & in2) | | |
2911 | (sel3 & in3) | | |
2912 | (sel4 & in4) | | |
2913 | (sel5 & in5)); | |
2914 | `endif | |
2915 | ||
2916 | endmodule | |
2917 | module cl_sc1_aomux6_2x ( | |
2918 | in0, | |
2919 | in1, | |
2920 | in2, | |
2921 | in3, | |
2922 | in4, | |
2923 | in5, | |
2924 | sel0, | |
2925 | sel1, | |
2926 | sel2, | |
2927 | sel3, | |
2928 | sel4, | |
2929 | sel5, | |
2930 | out | |
2931 | ); | |
2932 | input in0; | |
2933 | input in1; | |
2934 | input in2; | |
2935 | input in3; | |
2936 | input in4; | |
2937 | input in5; | |
2938 | input sel0; | |
2939 | input sel1; | |
2940 | input sel2; | |
2941 | input sel3; | |
2942 | input sel4; | |
2943 | input sel5; | |
2944 | output out; | |
2945 | ||
2946 | `ifdef LIB | |
2947 | assign out = ((sel0 & in0) | | |
2948 | (sel1 & in1) | | |
2949 | (sel2 & in2) | | |
2950 | (sel3 & in3) | | |
2951 | (sel4 & in4) | | |
2952 | (sel5 & in5)); | |
2953 | `endif | |
2954 | ||
2955 | endmodule | |
2956 | module cl_sc1_aomux6_4x ( | |
2957 | in0, | |
2958 | in1, | |
2959 | in2, | |
2960 | in3, | |
2961 | in4, | |
2962 | in5, | |
2963 | sel0, | |
2964 | sel1, | |
2965 | sel2, | |
2966 | sel3, | |
2967 | sel4, | |
2968 | sel5, | |
2969 | out | |
2970 | ); | |
2971 | input in0; | |
2972 | input in1; | |
2973 | input in2; | |
2974 | input in3; | |
2975 | input in4; | |
2976 | input in5; | |
2977 | input sel0; | |
2978 | input sel1; | |
2979 | input sel2; | |
2980 | input sel3; | |
2981 | input sel4; | |
2982 | input sel5; | |
2983 | output out; | |
2984 | ||
2985 | `ifdef LIB | |
2986 | assign out = ((sel0 & in0) | | |
2987 | (sel1 & in1) | | |
2988 | (sel2 & in2) | | |
2989 | (sel3 & in3) | | |
2990 | (sel4 & in4) | | |
2991 | (sel5 & in5)); | |
2992 | `endif | |
2993 | ||
2994 | endmodule | |
2995 | module cl_sc1_aomux6_6x ( | |
2996 | in0, | |
2997 | in1, | |
2998 | in2, | |
2999 | in3, | |
3000 | in4, | |
3001 | in5, | |
3002 | sel0, | |
3003 | sel1, | |
3004 | sel2, | |
3005 | sel3, | |
3006 | sel4, | |
3007 | sel5, | |
3008 | out | |
3009 | ); | |
3010 | input in0; | |
3011 | input in1; | |
3012 | input in2; | |
3013 | input in3; | |
3014 | input in4; | |
3015 | input in5; | |
3016 | input sel0; | |
3017 | input sel1; | |
3018 | input sel2; | |
3019 | input sel3; | |
3020 | input sel4; | |
3021 | input sel5; | |
3022 | output out; | |
3023 | ||
3024 | `ifdef LIB | |
3025 | assign out = ((sel0 & in0) | | |
3026 | (sel1 & in1) | | |
3027 | (sel2 & in2) | | |
3028 | (sel3 & in3) | | |
3029 | (sel4 & in4) | | |
3030 | (sel5 & in5)); | |
3031 | `endif | |
3032 | ||
3033 | endmodule | |
3034 | module cl_sc1_aomux6_8x ( | |
3035 | in0, | |
3036 | in1, | |
3037 | in2, | |
3038 | in3, | |
3039 | in4, | |
3040 | in5, | |
3041 | sel0, | |
3042 | sel1, | |
3043 | sel2, | |
3044 | sel3, | |
3045 | sel4, | |
3046 | sel5, | |
3047 | out | |
3048 | ); | |
3049 | input in0; | |
3050 | input in1; | |
3051 | input in2; | |
3052 | input in3; | |
3053 | input in4; | |
3054 | input in5; | |
3055 | input sel0; | |
3056 | input sel1; | |
3057 | input sel2; | |
3058 | input sel3; | |
3059 | input sel4; | |
3060 | input sel5; | |
3061 | output out; | |
3062 | ||
3063 | `ifdef LIB | |
3064 | assign out = ((sel0 & in0) | | |
3065 | (sel1 & in1) | | |
3066 | (sel2 & in2) | | |
3067 | (sel3 & in3) | | |
3068 | (sel4 & in4) | | |
3069 | (sel5 & in5)); | |
3070 | `endif | |
3071 | ||
3072 | endmodule | |
3073 | module cl_sc1_aomux6_by2_1x ( | |
3074 | in0, | |
3075 | in1, | |
3076 | in2, | |
3077 | in3, | |
3078 | in4, | |
3079 | in5, | |
3080 | sel0, | |
3081 | sel1, | |
3082 | sel2, | |
3083 | sel3, | |
3084 | sel4, | |
3085 | sel5, | |
3086 | out | |
3087 | ); | |
3088 | input in0; | |
3089 | input in1; | |
3090 | input in2; | |
3091 | input in3; | |
3092 | input in4; | |
3093 | input in5; | |
3094 | input sel0; | |
3095 | input sel1; | |
3096 | input sel2; | |
3097 | input sel3; | |
3098 | input sel4; | |
3099 | input sel5; | |
3100 | output out; | |
3101 | ||
3102 | `ifdef LIB | |
3103 | assign out = ((sel0 & in0) | | |
3104 | (sel1 & in1) | | |
3105 | (sel2 & in2) | | |
3106 | (sel3 & in3) | | |
3107 | (sel4 & in4) | | |
3108 | (sel5 & in5)); | |
3109 | `endif | |
3110 | ||
3111 | endmodule | |
3112 | module cl_sc1_aomux6_by2_2x ( | |
3113 | in0, | |
3114 | in1, | |
3115 | in2, | |
3116 | in3, | |
3117 | in4, | |
3118 | in5, | |
3119 | sel0, | |
3120 | sel1, | |
3121 | sel2, | |
3122 | sel3, | |
3123 | sel4, | |
3124 | sel5, | |
3125 | out | |
3126 | ); | |
3127 | input in0; | |
3128 | input in1; | |
3129 | input in2; | |
3130 | input in3; | |
3131 | input in4; | |
3132 | input in5; | |
3133 | input sel0; | |
3134 | input sel1; | |
3135 | input sel2; | |
3136 | input sel3; | |
3137 | input sel4; | |
3138 | input sel5; | |
3139 | output out; | |
3140 | ||
3141 | `ifdef LIB | |
3142 | assign out = ((sel0 & in0) | | |
3143 | (sel1 & in1) | | |
3144 | (sel2 & in2) | | |
3145 | (sel3 & in3) | | |
3146 | (sel4 & in4) | | |
3147 | (sel5 & in5)); | |
3148 | `endif | |
3149 | ||
3150 | endmodule | |
3151 | module cl_sc1_aomux7_12x ( | |
3152 | in0, | |
3153 | in1, | |
3154 | in2, | |
3155 | in3, | |
3156 | in4, | |
3157 | in5, | |
3158 | in6, | |
3159 | sel0, | |
3160 | sel1, | |
3161 | sel2, | |
3162 | sel3, | |
3163 | sel4, | |
3164 | sel5, | |
3165 | sel6, | |
3166 | out | |
3167 | ); | |
3168 | input in0; | |
3169 | input in1; | |
3170 | input in2; | |
3171 | input in3; | |
3172 | input in4; | |
3173 | input in5; | |
3174 | input in6; | |
3175 | input sel0; | |
3176 | input sel1; | |
3177 | input sel2; | |
3178 | input sel3; | |
3179 | input sel4; | |
3180 | input sel5; | |
3181 | input sel6; | |
3182 | output out; | |
3183 | ||
3184 | `ifdef LIB | |
3185 | assign out = ((sel0 & in0) | | |
3186 | (sel1 & in1) | | |
3187 | (sel2 & in2) | | |
3188 | (sel3 & in3) | | |
3189 | (sel4 & in4) | | |
3190 | (sel5 & in5) | | |
3191 | (sel6 & in6)); | |
3192 | `endif | |
3193 | ||
3194 | endmodule | |
3195 | module cl_sc1_aomux7_16x ( | |
3196 | in0, | |
3197 | in1, | |
3198 | in2, | |
3199 | in3, | |
3200 | in4, | |
3201 | in5, | |
3202 | in6, | |
3203 | sel0, | |
3204 | sel1, | |
3205 | sel2, | |
3206 | sel3, | |
3207 | sel4, | |
3208 | sel5, | |
3209 | sel6, | |
3210 | out | |
3211 | ); | |
3212 | input in0; | |
3213 | input in1; | |
3214 | input in2; | |
3215 | input in3; | |
3216 | input in4; | |
3217 | input in5; | |
3218 | input in6; | |
3219 | input sel0; | |
3220 | input sel1; | |
3221 | input sel2; | |
3222 | input sel3; | |
3223 | input sel4; | |
3224 | input sel5; | |
3225 | input sel6; | |
3226 | output out; | |
3227 | ||
3228 | `ifdef LIB | |
3229 | assign out = ((sel0 & in0) | | |
3230 | (sel1 & in1) | | |
3231 | (sel2 & in2) | | |
3232 | (sel3 & in3) | | |
3233 | (sel4 & in4) | | |
3234 | (sel5 & in5) | | |
3235 | (sel6 & in6)); | |
3236 | `endif | |
3237 | ||
3238 | endmodule | |
3239 | module cl_sc1_aomux7_1x ( | |
3240 | in0, | |
3241 | in1, | |
3242 | in2, | |
3243 | in3, | |
3244 | in4, | |
3245 | in5, | |
3246 | in6, | |
3247 | sel0, | |
3248 | sel1, | |
3249 | sel2, | |
3250 | sel3, | |
3251 | sel4, | |
3252 | sel5, | |
3253 | sel6, | |
3254 | out | |
3255 | ); | |
3256 | input in0; | |
3257 | input in1; | |
3258 | input in2; | |
3259 | input in3; | |
3260 | input in4; | |
3261 | input in5; | |
3262 | input in6; | |
3263 | input sel0; | |
3264 | input sel1; | |
3265 | input sel2; | |
3266 | input sel3; | |
3267 | input sel4; | |
3268 | input sel5; | |
3269 | input sel6; | |
3270 | output out; | |
3271 | ||
3272 | `ifdef LIB | |
3273 | assign out = ((sel0 & in0) | | |
3274 | (sel1 & in1) | | |
3275 | (sel2 & in2) | | |
3276 | (sel3 & in3) | | |
3277 | (sel4 & in4) | | |
3278 | (sel5 & in5) | | |
3279 | (sel6 & in6)); | |
3280 | `endif | |
3281 | ||
3282 | endmodule | |
3283 | module cl_sc1_aomux7_2x ( | |
3284 | in0, | |
3285 | in1, | |
3286 | in2, | |
3287 | in3, | |
3288 | in4, | |
3289 | in5, | |
3290 | in6, | |
3291 | sel0, | |
3292 | sel1, | |
3293 | sel2, | |
3294 | sel3, | |
3295 | sel4, | |
3296 | sel5, | |
3297 | sel6, | |
3298 | out | |
3299 | ); | |
3300 | input in0; | |
3301 | input in1; | |
3302 | input in2; | |
3303 | input in3; | |
3304 | input in4; | |
3305 | input in5; | |
3306 | input in6; | |
3307 | input sel0; | |
3308 | input sel1; | |
3309 | input sel2; | |
3310 | input sel3; | |
3311 | input sel4; | |
3312 | input sel5; | |
3313 | input sel6; | |
3314 | output out; | |
3315 | ||
3316 | `ifdef LIB | |
3317 | assign out = ((sel0 & in0) | | |
3318 | (sel1 & in1) | | |
3319 | (sel2 & in2) | | |
3320 | (sel3 & in3) | | |
3321 | (sel4 & in4) | | |
3322 | (sel5 & in5) | | |
3323 | (sel6 & in6)); | |
3324 | `endif | |
3325 | ||
3326 | endmodule | |
3327 | module cl_sc1_aomux7_4x ( | |
3328 | in0, | |
3329 | in1, | |
3330 | in2, | |
3331 | in3, | |
3332 | in4, | |
3333 | in5, | |
3334 | in6, | |
3335 | sel0, | |
3336 | sel1, | |
3337 | sel2, | |
3338 | sel3, | |
3339 | sel4, | |
3340 | sel5, | |
3341 | sel6, | |
3342 | out | |
3343 | ); | |
3344 | input in0; | |
3345 | input in1; | |
3346 | input in2; | |
3347 | input in3; | |
3348 | input in4; | |
3349 | input in5; | |
3350 | input in6; | |
3351 | input sel0; | |
3352 | input sel1; | |
3353 | input sel2; | |
3354 | input sel3; | |
3355 | input sel4; | |
3356 | input sel5; | |
3357 | input sel6; | |
3358 | output out; | |
3359 | ||
3360 | `ifdef LIB | |
3361 | assign out = ((sel0 & in0) | | |
3362 | (sel1 & in1) | | |
3363 | (sel2 & in2) | | |
3364 | (sel3 & in3) | | |
3365 | (sel4 & in4) | | |
3366 | (sel5 & in5) | | |
3367 | (sel6 & in6)); | |
3368 | `endif | |
3369 | ||
3370 | endmodule | |
3371 | module cl_sc1_aomux7_6x ( | |
3372 | in0, | |
3373 | in1, | |
3374 | in2, | |
3375 | in3, | |
3376 | in4, | |
3377 | in5, | |
3378 | in6, | |
3379 | sel0, | |
3380 | sel1, | |
3381 | sel2, | |
3382 | sel3, | |
3383 | sel4, | |
3384 | sel5, | |
3385 | sel6, | |
3386 | out | |
3387 | ); | |
3388 | input in0; | |
3389 | input in1; | |
3390 | input in2; | |
3391 | input in3; | |
3392 | input in4; | |
3393 | input in5; | |
3394 | input in6; | |
3395 | input sel0; | |
3396 | input sel1; | |
3397 | input sel2; | |
3398 | input sel3; | |
3399 | input sel4; | |
3400 | input sel5; | |
3401 | input sel6; | |
3402 | output out; | |
3403 | ||
3404 | `ifdef LIB | |
3405 | assign out = ((sel0 & in0) | | |
3406 | (sel1 & in1) | | |
3407 | (sel2 & in2) | | |
3408 | (sel3 & in3) | | |
3409 | (sel4 & in4) | | |
3410 | (sel5 & in5) | | |
3411 | (sel6 & in6)); | |
3412 | `endif | |
3413 | ||
3414 | endmodule | |
3415 | module cl_sc1_aomux7_8x ( | |
3416 | in0, | |
3417 | in1, | |
3418 | in2, | |
3419 | in3, | |
3420 | in4, | |
3421 | in5, | |
3422 | in6, | |
3423 | sel0, | |
3424 | sel1, | |
3425 | sel2, | |
3426 | sel3, | |
3427 | sel4, | |
3428 | sel5, | |
3429 | sel6, | |
3430 | out | |
3431 | ); | |
3432 | input in0; | |
3433 | input in1; | |
3434 | input in2; | |
3435 | input in3; | |
3436 | input in4; | |
3437 | input in5; | |
3438 | input in6; | |
3439 | input sel0; | |
3440 | input sel1; | |
3441 | input sel2; | |
3442 | input sel3; | |
3443 | input sel4; | |
3444 | input sel5; | |
3445 | input sel6; | |
3446 | output out; | |
3447 | ||
3448 | `ifdef LIB | |
3449 | assign out = ((sel0 & in0) | | |
3450 | (sel1 & in1) | | |
3451 | (sel2 & in2) | | |
3452 | (sel3 & in3) | | |
3453 | (sel4 & in4) | | |
3454 | (sel5 & in5) | | |
3455 | (sel6 & in6)); | |
3456 | `endif | |
3457 | ||
3458 | endmodule | |
3459 | module cl_sc1_aomux7_by2_1x ( | |
3460 | in0, | |
3461 | in1, | |
3462 | in2, | |
3463 | in3, | |
3464 | in4, | |
3465 | in5, | |
3466 | in6, | |
3467 | sel0, | |
3468 | sel1, | |
3469 | sel2, | |
3470 | sel3, | |
3471 | sel4, | |
3472 | sel5, | |
3473 | sel6, | |
3474 | out | |
3475 | ); | |
3476 | input in0; | |
3477 | input in1; | |
3478 | input in2; | |
3479 | input in3; | |
3480 | input in4; | |
3481 | input in5; | |
3482 | input in6; | |
3483 | input sel0; | |
3484 | input sel1; | |
3485 | input sel2; | |
3486 | input sel3; | |
3487 | input sel4; | |
3488 | input sel5; | |
3489 | input sel6; | |
3490 | output out; | |
3491 | ||
3492 | `ifdef LIB | |
3493 | assign out = ((sel0 & in0) | | |
3494 | (sel1 & in1) | | |
3495 | (sel2 & in2) | | |
3496 | (sel3 & in3) | | |
3497 | (sel4 & in4) | | |
3498 | (sel5 & in5) | | |
3499 | (sel6 & in6)); | |
3500 | `endif | |
3501 | ||
3502 | endmodule | |
3503 | module cl_sc1_aomux7_by2_2x ( | |
3504 | in0, | |
3505 | in1, | |
3506 | in2, | |
3507 | in3, | |
3508 | in4, | |
3509 | in5, | |
3510 | in6, | |
3511 | sel0, | |
3512 | sel1, | |
3513 | sel2, | |
3514 | sel3, | |
3515 | sel4, | |
3516 | sel5, | |
3517 | sel6, | |
3518 | out | |
3519 | ); | |
3520 | input in0; | |
3521 | input in1; | |
3522 | input in2; | |
3523 | input in3; | |
3524 | input in4; | |
3525 | input in5; | |
3526 | input in6; | |
3527 | input sel0; | |
3528 | input sel1; | |
3529 | input sel2; | |
3530 | input sel3; | |
3531 | input sel4; | |
3532 | input sel5; | |
3533 | input sel6; | |
3534 | output out; | |
3535 | ||
3536 | `ifdef LIB | |
3537 | assign out = ((sel0 & in0) | | |
3538 | (sel1 & in1) | | |
3539 | (sel2 & in2) | | |
3540 | (sel3 & in3) | | |
3541 | (sel4 & in4) | | |
3542 | (sel5 & in5) | | |
3543 | (sel6 & in6)); | |
3544 | `endif | |
3545 | ||
3546 | endmodule | |
3547 | module cl_sc1_aomux8_12x ( | |
3548 | in0, | |
3549 | in1, | |
3550 | in2, | |
3551 | in3, | |
3552 | in4, | |
3553 | in5, | |
3554 | in6, | |
3555 | in7, | |
3556 | sel0, | |
3557 | sel1, | |
3558 | sel2, | |
3559 | sel3, | |
3560 | sel4, | |
3561 | sel5, | |
3562 | sel6, | |
3563 | sel7, | |
3564 | out | |
3565 | ); | |
3566 | input in0; | |
3567 | input in1; | |
3568 | input in2; | |
3569 | input in3; | |
3570 | input in4; | |
3571 | input in5; | |
3572 | input in6; | |
3573 | input in7; | |
3574 | input sel0; | |
3575 | input sel1; | |
3576 | input sel2; | |
3577 | input sel3; | |
3578 | input sel4; | |
3579 | input sel5; | |
3580 | input sel6; | |
3581 | input sel7; | |
3582 | output out; | |
3583 | ||
3584 | `ifdef LIB | |
3585 | assign out = ((sel0 & in0) | | |
3586 | (sel1 & in1) | | |
3587 | (sel2 & in2) | | |
3588 | (sel3 & in3) | | |
3589 | (sel4 & in4) | | |
3590 | (sel5 & in5) | | |
3591 | (sel6 & in6) | | |
3592 | (sel7 & in7)); | |
3593 | `endif | |
3594 | ||
3595 | ||
3596 | endmodule | |
3597 | module cl_sc1_aomux8_16x ( | |
3598 | in0, | |
3599 | in1, | |
3600 | in2, | |
3601 | in3, | |
3602 | in4, | |
3603 | in5, | |
3604 | in6, | |
3605 | in7, | |
3606 | sel0, | |
3607 | sel1, | |
3608 | sel2, | |
3609 | sel3, | |
3610 | sel4, | |
3611 | sel5, | |
3612 | sel6, | |
3613 | sel7, | |
3614 | out | |
3615 | ); | |
3616 | input in0; | |
3617 | input in1; | |
3618 | input in2; | |
3619 | input in3; | |
3620 | input in4; | |
3621 | input in5; | |
3622 | input in6; | |
3623 | input in7; | |
3624 | input sel0; | |
3625 | input sel1; | |
3626 | input sel2; | |
3627 | input sel3; | |
3628 | input sel4; | |
3629 | input sel5; | |
3630 | input sel6; | |
3631 | input sel7; | |
3632 | output out; | |
3633 | ||
3634 | `ifdef LIB | |
3635 | assign out = ((sel0 & in0) | | |
3636 | (sel1 & in1) | | |
3637 | (sel2 & in2) | | |
3638 | (sel3 & in3) | | |
3639 | (sel4 & in4) | | |
3640 | (sel5 & in5) | | |
3641 | (sel6 & in6) | | |
3642 | (sel7 & in7)); | |
3643 | `endif | |
3644 | ||
3645 | ||
3646 | endmodule | |
3647 | module cl_sc1_aomux8_1x ( | |
3648 | in0, | |
3649 | in1, | |
3650 | in2, | |
3651 | in3, | |
3652 | in4, | |
3653 | in5, | |
3654 | in6, | |
3655 | in7, | |
3656 | sel0, | |
3657 | sel1, | |
3658 | sel2, | |
3659 | sel3, | |
3660 | sel4, | |
3661 | sel5, | |
3662 | sel6, | |
3663 | sel7, | |
3664 | out | |
3665 | ); | |
3666 | input in0; | |
3667 | input in1; | |
3668 | input in2; | |
3669 | input in3; | |
3670 | input in4; | |
3671 | input in5; | |
3672 | input in6; | |
3673 | input in7; | |
3674 | input sel0; | |
3675 | input sel1; | |
3676 | input sel2; | |
3677 | input sel3; | |
3678 | input sel4; | |
3679 | input sel5; | |
3680 | input sel6; | |
3681 | input sel7; | |
3682 | output out; | |
3683 | ||
3684 | `ifdef LIB | |
3685 | assign out = ((sel0 & in0) | | |
3686 | (sel1 & in1) | | |
3687 | (sel2 & in2) | | |
3688 | (sel3 & in3) | | |
3689 | (sel4 & in4) | | |
3690 | (sel5 & in5) | | |
3691 | (sel6 & in6) | | |
3692 | (sel7 & in7)); | |
3693 | `endif | |
3694 | ||
3695 | ||
3696 | endmodule | |
3697 | module cl_sc1_aomux8_2x ( | |
3698 | in0, | |
3699 | in1, | |
3700 | in2, | |
3701 | in3, | |
3702 | in4, | |
3703 | in5, | |
3704 | in6, | |
3705 | in7, | |
3706 | sel0, | |
3707 | sel1, | |
3708 | sel2, | |
3709 | sel3, | |
3710 | sel4, | |
3711 | sel5, | |
3712 | sel6, | |
3713 | sel7, | |
3714 | out | |
3715 | ); | |
3716 | input in0; | |
3717 | input in1; | |
3718 | input in2; | |
3719 | input in3; | |
3720 | input in4; | |
3721 | input in5; | |
3722 | input in6; | |
3723 | input in7; | |
3724 | input sel0; | |
3725 | input sel1; | |
3726 | input sel2; | |
3727 | input sel3; | |
3728 | input sel4; | |
3729 | input sel5; | |
3730 | input sel6; | |
3731 | input sel7; | |
3732 | output out; | |
3733 | ||
3734 | `ifdef LIB | |
3735 | assign out = ((sel0 & in0) | | |
3736 | (sel1 & in1) | | |
3737 | (sel2 & in2) | | |
3738 | (sel3 & in3) | | |
3739 | (sel4 & in4) | | |
3740 | (sel5 & in5) | | |
3741 | (sel6 & in6) | | |
3742 | (sel7 & in7)); | |
3743 | `endif | |
3744 | ||
3745 | ||
3746 | endmodule | |
3747 | module cl_sc1_aomux8_4x ( | |
3748 | in0, | |
3749 | in1, | |
3750 | in2, | |
3751 | in3, | |
3752 | in4, | |
3753 | in5, | |
3754 | in6, | |
3755 | in7, | |
3756 | sel0, | |
3757 | sel1, | |
3758 | sel2, | |
3759 | sel3, | |
3760 | sel4, | |
3761 | sel5, | |
3762 | sel6, | |
3763 | sel7, | |
3764 | out | |
3765 | ); | |
3766 | input in0; | |
3767 | input in1; | |
3768 | input in2; | |
3769 | input in3; | |
3770 | input in4; | |
3771 | input in5; | |
3772 | input in6; | |
3773 | input in7; | |
3774 | input sel0; | |
3775 | input sel1; | |
3776 | input sel2; | |
3777 | input sel3; | |
3778 | input sel4; | |
3779 | input sel5; | |
3780 | input sel6; | |
3781 | input sel7; | |
3782 | output out; | |
3783 | ||
3784 | `ifdef LIB | |
3785 | assign out = ((sel0 & in0) | | |
3786 | (sel1 & in1) | | |
3787 | (sel2 & in2) | | |
3788 | (sel3 & in3) | | |
3789 | (sel4 & in4) | | |
3790 | (sel5 & in5) | | |
3791 | (sel6 & in6) | | |
3792 | (sel7 & in7)); | |
3793 | `endif | |
3794 | ||
3795 | ||
3796 | endmodule | |
3797 | module cl_sc1_aomux8_6x ( | |
3798 | in0, | |
3799 | in1, | |
3800 | in2, | |
3801 | in3, | |
3802 | in4, | |
3803 | in5, | |
3804 | in6, | |
3805 | in7, | |
3806 | sel0, | |
3807 | sel1, | |
3808 | sel2, | |
3809 | sel3, | |
3810 | sel4, | |
3811 | sel5, | |
3812 | sel6, | |
3813 | sel7, | |
3814 | out | |
3815 | ); | |
3816 | input in0; | |
3817 | input in1; | |
3818 | input in2; | |
3819 | input in3; | |
3820 | input in4; | |
3821 | input in5; | |
3822 | input in6; | |
3823 | input in7; | |
3824 | input sel0; | |
3825 | input sel1; | |
3826 | input sel2; | |
3827 | input sel3; | |
3828 | input sel4; | |
3829 | input sel5; | |
3830 | input sel6; | |
3831 | input sel7; | |
3832 | output out; | |
3833 | ||
3834 | `ifdef LIB | |
3835 | assign out = ((sel0 & in0) | | |
3836 | (sel1 & in1) | | |
3837 | (sel2 & in2) | | |
3838 | (sel3 & in3) | | |
3839 | (sel4 & in4) | | |
3840 | (sel5 & in5) | | |
3841 | (sel6 & in6) | | |
3842 | (sel7 & in7)); | |
3843 | `endif | |
3844 | ||
3845 | ||
3846 | endmodule | |
3847 | module cl_sc1_aomux8_8x ( | |
3848 | in0, | |
3849 | in1, | |
3850 | in2, | |
3851 | in3, | |
3852 | in4, | |
3853 | in5, | |
3854 | in6, | |
3855 | in7, | |
3856 | sel0, | |
3857 | sel1, | |
3858 | sel2, | |
3859 | sel3, | |
3860 | sel4, | |
3861 | sel5, | |
3862 | sel6, | |
3863 | sel7, | |
3864 | out | |
3865 | ); | |
3866 | input in0; | |
3867 | input in1; | |
3868 | input in2; | |
3869 | input in3; | |
3870 | input in4; | |
3871 | input in5; | |
3872 | input in6; | |
3873 | input in7; | |
3874 | input sel0; | |
3875 | input sel1; | |
3876 | input sel2; | |
3877 | input sel3; | |
3878 | input sel4; | |
3879 | input sel5; | |
3880 | input sel6; | |
3881 | input sel7; | |
3882 | output out; | |
3883 | ||
3884 | `ifdef LIB | |
3885 | assign out = ((sel0 & in0) | | |
3886 | (sel1 & in1) | | |
3887 | (sel2 & in2) | | |
3888 | (sel3 & in3) | | |
3889 | (sel4 & in4) | | |
3890 | (sel5 & in5) | | |
3891 | (sel6 & in6) | | |
3892 | (sel7 & in7)); | |
3893 | `endif | |
3894 | ||
3895 | ||
3896 | endmodule | |
3897 | module cl_sc1_aomux8_by2_1x ( | |
3898 | in0, | |
3899 | in1, | |
3900 | in2, | |
3901 | in3, | |
3902 | in4, | |
3903 | in5, | |
3904 | in6, | |
3905 | in7, | |
3906 | sel0, | |
3907 | sel1, | |
3908 | sel2, | |
3909 | sel3, | |
3910 | sel4, | |
3911 | sel5, | |
3912 | sel6, | |
3913 | sel7, | |
3914 | out | |
3915 | ); | |
3916 | input in0; | |
3917 | input in1; | |
3918 | input in2; | |
3919 | input in3; | |
3920 | input in4; | |
3921 | input in5; | |
3922 | input in6; | |
3923 | input in7; | |
3924 | input sel0; | |
3925 | input sel1; | |
3926 | input sel2; | |
3927 | input sel3; | |
3928 | input sel4; | |
3929 | input sel5; | |
3930 | input sel6; | |
3931 | input sel7; | |
3932 | output out; | |
3933 | ||
3934 | `ifdef LIB | |
3935 | assign out = ((sel0 & in0) | | |
3936 | (sel1 & in1) | | |
3937 | (sel2 & in2) | | |
3938 | (sel3 & in3) | | |
3939 | (sel4 & in4) | | |
3940 | (sel5 & in5) | | |
3941 | (sel6 & in6) | | |
3942 | (sel7 & in7)); | |
3943 | `endif | |
3944 | ||
3945 | ||
3946 | endmodule | |
3947 | module cl_sc1_aomux8_by2_2x ( | |
3948 | in0, | |
3949 | in1, | |
3950 | in2, | |
3951 | in3, | |
3952 | in4, | |
3953 | in5, | |
3954 | in6, | |
3955 | in7, | |
3956 | sel0, | |
3957 | sel1, | |
3958 | sel2, | |
3959 | sel3, | |
3960 | sel4, | |
3961 | sel5, | |
3962 | sel6, | |
3963 | sel7, | |
3964 | out | |
3965 | ); | |
3966 | input in0; | |
3967 | input in1; | |
3968 | input in2; | |
3969 | input in3; | |
3970 | input in4; | |
3971 | input in5; | |
3972 | input in6; | |
3973 | input in7; | |
3974 | input sel0; | |
3975 | input sel1; | |
3976 | input sel2; | |
3977 | input sel3; | |
3978 | input sel4; | |
3979 | input sel5; | |
3980 | input sel6; | |
3981 | input sel7; | |
3982 | output out; | |
3983 | ||
3984 | `ifdef LIB | |
3985 | assign out = ((sel0 & in0) | | |
3986 | (sel1 & in1) | | |
3987 | (sel2 & in2) | | |
3988 | (sel3 & in3) | | |
3989 | (sel4 & in4) | | |
3990 | (sel5 & in5) | | |
3991 | (sel6 & in6) | | |
3992 | (sel7 & in7)); | |
3993 | `endif | |
3994 | ||
3995 | ||
3996 | endmodule | |
3997 | module cl_sc1_l1hdr_12x ( | |
3998 | l2clk, | |
3999 | se, | |
4000 | pce, | |
4001 | pce_ov, | |
4002 | stop, | |
4003 | l1clk | |
4004 | ||
4005 | ); | |
4006 | ||
4007 | ||
4008 | ||
4009 | ||
4010 | input l2clk; // level 2 clock, from clock grid | |
4011 | input se; // Scan Enable | |
4012 | input pce; // Clock enable for local power savings | |
4013 | input pce_ov; // TCU sourced clock enable override for testing | |
4014 | input stop; // TCU/CCU sourced clock stop for debug | |
4015 | output l1clk; | |
4016 | `ifdef FORMAL_TOOL | |
4017 | wire l1en = (~stop & ( pce | pce_ov )); | |
4018 | assign l1clk = (l2clk & l1en) | se; | |
4019 | `else | |
4020 | `ifdef LIB | |
4021 | reg l1en; | |
4022 | ||
4023 | `ifdef SCAN_MODE | |
4024 | always @ (l2clk or stop or pce or pce_ov) | |
4025 | begin | |
4026 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4027 | end | |
4028 | `else | |
4029 | always @ (negedge l2clk ) | |
4030 | begin | |
4031 | l1en <= (~stop & ( pce | pce_ov )); | |
4032 | end | |
4033 | `endif | |
4034 | ||
4035 | ||
4036 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4037 | ||
4038 | ||
4039 | ||
4040 | `endif | |
4041 | `endif | |
4042 | ||
4043 | endmodule | |
4044 | ||
4045 | module cl_sc1_l1hdr_16x ( | |
4046 | l2clk, | |
4047 | se, | |
4048 | pce, | |
4049 | pce_ov, | |
4050 | stop, | |
4051 | l1clk | |
4052 | ); | |
4053 | // RFM 05/21/2004 | |
4054 | ||
4055 | ||
4056 | ||
4057 | input l2clk; // level 2 clock, from clock grid | |
4058 | input se; // Scan Enable | |
4059 | input pce; // Clock enable for local power savings | |
4060 | input pce_ov; // TCU sourced clock enable override for testing | |
4061 | input stop; // TCU/CCU sourced clock stop for debug | |
4062 | output l1clk; | |
4063 | `ifdef FORMAL_TOOL | |
4064 | wire l1en = (~stop & ( pce | pce_ov )); | |
4065 | assign l1clk = (l2clk & l1en) | se; | |
4066 | `else | |
4067 | `ifdef LIB | |
4068 | reg l1en; | |
4069 | ||
4070 | `ifdef SCAN_MODE | |
4071 | always @ (l2clk or stop or pce or pce_ov) | |
4072 | begin | |
4073 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4074 | end | |
4075 | `else | |
4076 | always @ (negedge l2clk ) | |
4077 | begin | |
4078 | l1en <= (~stop & ( pce | pce_ov )); | |
4079 | end | |
4080 | `endif | |
4081 | ||
4082 | ||
4083 | ||
4084 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4085 | ||
4086 | ||
4087 | ||
4088 | `endif | |
4089 | `endif | |
4090 | ||
4091 | endmodule | |
4092 | module cl_sc1_l1hdr_24x ( | |
4093 | l2clk, | |
4094 | se, | |
4095 | pce, | |
4096 | pce_ov, | |
4097 | stop, | |
4098 | l1clk | |
4099 | ); | |
4100 | // RFM 05/21/2004 | |
4101 | ||
4102 | ||
4103 | ||
4104 | input l2clk; // level 2 clock, from clock grid | |
4105 | input se; // Scan Enable | |
4106 | input pce; // Clock enable for local power savings | |
4107 | input pce_ov; // TCU sourced clock enable override for testing | |
4108 | input stop; // TCU/CCU sourced clock stop for debug | |
4109 | output l1clk; | |
4110 | `ifdef FORMAL_TOOL | |
4111 | wire l1en = (~stop & ( pce | pce_ov )); | |
4112 | assign l1clk = (l2clk & l1en) | se; | |
4113 | `else | |
4114 | `ifdef LIB | |
4115 | reg l1en; | |
4116 | ||
4117 | ||
4118 | ||
4119 | `ifdef SCAN_MODE | |
4120 | always @ (l2clk or stop or pce or pce_ov) | |
4121 | begin | |
4122 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4123 | end | |
4124 | `else | |
4125 | always @ (negedge l2clk ) | |
4126 | begin | |
4127 | l1en <= (~stop & ( pce | pce_ov )); | |
4128 | end | |
4129 | `endif | |
4130 | ||
4131 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4132 | ||
4133 | ||
4134 | `endif | |
4135 | `endif | |
4136 | ||
4137 | endmodule | |
4138 | module cl_sc1_l1hdr_32x ( | |
4139 | l2clk, | |
4140 | se, | |
4141 | pce, | |
4142 | pce_ov, | |
4143 | stop, | |
4144 | l1clk | |
4145 | ); | |
4146 | // RFM 05/21/2004 | |
4147 | ||
4148 | ||
4149 | ||
4150 | input l2clk; // level 2 clock, from clock grid | |
4151 | input se; // Scan Enable | |
4152 | input pce; // Clock enable for local power savings | |
4153 | input pce_ov; // TCU sourced clock enable override for testing | |
4154 | input stop; // TCU/CCU sourced clock stop for debug | |
4155 | output l1clk; | |
4156 | `ifdef FORMAL_TOOL | |
4157 | wire l1en = (~stop & ( pce | pce_ov )); | |
4158 | assign l1clk = (l2clk & l1en) | se; | |
4159 | `else | |
4160 | `ifdef LIB | |
4161 | reg l1en; | |
4162 | ||
4163 | `ifdef SCAN_MODE | |
4164 | always @ (l2clk or stop or pce or pce_ov) | |
4165 | begin | |
4166 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4167 | end | |
4168 | `else | |
4169 | always @ (negedge l2clk ) | |
4170 | begin | |
4171 | l1en <= (~stop & ( pce | pce_ov )); | |
4172 | end | |
4173 | `endif | |
4174 | ||
4175 | ||
4176 | ||
4177 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4178 | ||
4179 | ||
4180 | ||
4181 | `endif | |
4182 | `endif | |
4183 | ||
4184 | endmodule | |
4185 | ||
4186 | module cl_sc1_l1hdr_4x ( | |
4187 | l2clk, | |
4188 | se, | |
4189 | pce, | |
4190 | pce_ov, | |
4191 | stop, | |
4192 | l1clk | |
4193 | ); | |
4194 | // RFM 05/21/2004 | |
4195 | ||
4196 | ||
4197 | ||
4198 | input l2clk; // level 2 clock, from clock grid | |
4199 | input se; // Scan Enable | |
4200 | input pce; // Clock enable for local power savings | |
4201 | input pce_ov; // TCU sourced clock enable override for testing | |
4202 | input stop; // TCU/CCU sourced clock stop for debug | |
4203 | output l1clk; | |
4204 | `ifdef FORMAL_TOOL | |
4205 | wire l1en = (~stop & ( pce | pce_ov )); | |
4206 | assign l1clk = (l2clk & l1en) | se; | |
4207 | `else | |
4208 | `ifdef LIB | |
4209 | reg l1en; | |
4210 | ||
4211 | `ifdef SCAN_MODE | |
4212 | always @ (l2clk or stop or pce or pce_ov) | |
4213 | begin | |
4214 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4215 | end | |
4216 | `else | |
4217 | always @ (negedge l2clk ) | |
4218 | begin | |
4219 | l1en <= (~stop & ( pce | pce_ov )); | |
4220 | end | |
4221 | `endif | |
4222 | ||
4223 | ||
4224 | ||
4225 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4226 | ||
4227 | ||
4228 | ||
4229 | `endif | |
4230 | `endif | |
4231 | ||
4232 | endmodule | |
4233 | module cl_sc1_l1hdr_48x ( | |
4234 | l2clk, | |
4235 | se, | |
4236 | pce, | |
4237 | pce_ov, | |
4238 | stop, | |
4239 | l1clk | |
4240 | ||
4241 | ); | |
4242 | ||
4243 | ||
4244 | ||
4245 | ||
4246 | input l2clk; // level 2 clock, from clock grid | |
4247 | input se; // Scan Enable | |
4248 | input pce; // Clock enable for local power savings | |
4249 | input pce_ov; // TCU sourced clock enable override for testing | |
4250 | input stop; // TCU/CCU sourced clock stop for debug | |
4251 | output l1clk; | |
4252 | `ifdef FORMAL_TOOL | |
4253 | wire l1en = (~stop & ( pce | pce_ov )); | |
4254 | assign l1clk = (l2clk & l1en) | se; | |
4255 | `else | |
4256 | `ifdef LIB | |
4257 | reg l1en; | |
4258 | ||
4259 | ||
4260 | ||
4261 | `ifdef SCAN_MODE | |
4262 | always @ (l2clk or stop or pce or pce_ov) | |
4263 | begin | |
4264 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4265 | end | |
4266 | `else | |
4267 | always @ (negedge l2clk ) | |
4268 | begin | |
4269 | l1en <= (~stop & ( pce | pce_ov )); | |
4270 | end | |
4271 | `endif | |
4272 | ||
4273 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4274 | ||
4275 | ||
4276 | ||
4277 | `endif | |
4278 | `endif | |
4279 | ||
4280 | endmodule | |
4281 | module cl_sc1_l1hdr_64x ( | |
4282 | l2clk, | |
4283 | se, | |
4284 | pce, | |
4285 | pce_ov, | |
4286 | stop, | |
4287 | l1clk | |
4288 | ||
4289 | ); | |
4290 | ||
4291 | ||
4292 | ||
4293 | ||
4294 | input l2clk; // level 2 clock, from clock grid | |
4295 | input se; // Scan Enable | |
4296 | input pce; // Clock enable for local power savings | |
4297 | input pce_ov; // TCU sourced clock enable override for testing | |
4298 | input stop; // TCU/CCU sourced clock stop for debug | |
4299 | output l1clk; | |
4300 | `ifdef FORMAL_TOOL | |
4301 | wire l1en = (~stop & ( pce | pce_ov )); | |
4302 | assign l1clk = (l2clk & l1en) | se; | |
4303 | `else | |
4304 | `ifdef LIB | |
4305 | reg l1en; | |
4306 | ||
4307 | ||
4308 | ||
4309 | `ifdef SCAN_MODE | |
4310 | always @ (l2clk or stop or pce or pce_ov) | |
4311 | begin | |
4312 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4313 | end | |
4314 | `else | |
4315 | always @ (negedge l2clk ) | |
4316 | begin | |
4317 | l1en <= (~stop & ( pce | pce_ov )); | |
4318 | end | |
4319 | `endif | |
4320 | ||
4321 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4322 | ||
4323 | ||
4324 | ||
4325 | `endif | |
4326 | `endif | |
4327 | ||
4328 | endmodule | |
4329 | ||
4330 | `ifdef FPGA | |
4331 | `else | |
4332 | module cl_sc1_l1hdr_8x ( | |
4333 | l2clk, | |
4334 | se, | |
4335 | pce, | |
4336 | pce_ov, | |
4337 | stop, | |
4338 | l1clk | |
4339 | ); | |
4340 | // RFM 05/21/2004 | |
4341 | ||
4342 | ||
4343 | ||
4344 | input l2clk; // level 2 clock, from clock grid | |
4345 | input se; // Scan Enable | |
4346 | input pce; // Clock enable for local power savings | |
4347 | input pce_ov; // TCU sourced clock enable override for testing | |
4348 | input stop; // TCU/CCU sourced clock stop for debug | |
4349 | output l1clk; | |
4350 | `ifdef FORMAL_TOOL | |
4351 | wire l1en = (~stop & ( pce | pce_ov )); | |
4352 | assign l1clk = (l2clk & l1en) | se; | |
4353 | `else | |
4354 | `ifdef LIB | |
4355 | reg l1en; | |
4356 | ||
4357 | ||
4358 | `ifdef SCAN_MODE | |
4359 | always @ (l2clk or stop or pce or pce_ov) | |
4360 | begin | |
4361 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4362 | end | |
4363 | `else | |
4364 | always @ (negedge l2clk ) | |
4365 | begin | |
4366 | l1en <= (~stop & ( pce | pce_ov )); | |
4367 | end | |
4368 | `endif | |
4369 | ||
4370 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4371 | ||
4372 | ||
4373 | ||
4374 | `endif | |
4375 | `endif | |
4376 | ||
4377 | endmodule | |
4378 | `endif // `ifdef FPGA | |
4379 | ||
4380 | module cl_sc1_msffmin_16x ( q, so, d, l1clk, si, siclk, soclk ); | |
4381 | // RFM 05-14-2004 | |
4382 | // Level sensitive in SCAN_MODE | |
4383 | // Edge triggered when not in SCAN_MODE | |
4384 | ||
4385 | ||
4386 | parameter SIZE = 1; | |
4387 | ||
4388 | output q; | |
4389 | output so; | |
4390 | ||
4391 | input d; | |
4392 | input l1clk; | |
4393 | input si; | |
4394 | input siclk; | |
4395 | input soclk; | |
4396 | ||
4397 | reg q; | |
4398 | wire so; | |
4399 | wire l1clk, siclk, soclk; | |
4400 | ||
4401 | `ifdef SCAN_MODE | |
4402 | ||
4403 | reg l1; | |
4404 | `ifdef FAST_FLUSH | |
4405 | always @(posedge l1clk or posedge siclk ) begin | |
4406 | if (siclk) begin | |
4407 | q <= 1'b0; //pseudo flush reset | |
4408 | end else begin | |
4409 | q <= d; | |
4410 | end | |
4411 | end | |
4412 | `else | |
4413 | always @(l1clk or siclk or soclk or d or si) | |
4414 | begin | |
4415 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4416 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4417 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4418 | ||
4419 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4420 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4421 | end | |
4422 | `endif | |
4423 | `else | |
4424 | wire si_unused; | |
4425 | wire siclk_unused; | |
4426 | wire soclk_unused; | |
4427 | assign si_unused = si; | |
4428 | assign siclk_unused = siclk; | |
4429 | assign soclk_unused = soclk; | |
4430 | ||
4431 | ||
4432 | `ifdef INITLATZERO | |
4433 | initial q = 1'b0; | |
4434 | `endif | |
4435 | ||
4436 | always @(posedge l1clk) | |
4437 | begin | |
4438 | if (!siclk && !soclk) q <= d; | |
4439 | else q <= 1'bx; | |
4440 | end | |
4441 | `endif | |
4442 | ||
4443 | assign so = q; | |
4444 | ||
4445 | endmodule // dff | |
4446 | ||
4447 | ||
4448 | ||
4449 | ||
4450 | module cl_sc1_msffmin_8x ( q, so, d, l1clk, si, siclk, soclk ); | |
4451 | // RFM 05-14-2004 | |
4452 | // Level sensitive in SCAN_MODE | |
4453 | // Edge triggered when not in SCAN_MODE | |
4454 | ||
4455 | ||
4456 | parameter SIZE = 1; | |
4457 | ||
4458 | output q; | |
4459 | output so; | |
4460 | ||
4461 | input d; | |
4462 | input l1clk; | |
4463 | input si; | |
4464 | input siclk; | |
4465 | input soclk; | |
4466 | ||
4467 | reg q; | |
4468 | wire so; | |
4469 | wire l1clk, siclk, soclk; | |
4470 | ||
4471 | `ifdef SCAN_MODE | |
4472 | `ifdef FAST_FLUSH | |
4473 | always @(posedge l1clk or posedge siclk ) begin | |
4474 | if (siclk) begin | |
4475 | q <= 1'b0; //pseudo flush reset | |
4476 | end else begin | |
4477 | q <= d; | |
4478 | end | |
4479 | end | |
4480 | `else | |
4481 | reg l1; | |
4482 | ||
4483 | always @(l1clk or siclk or soclk or d or si) | |
4484 | begin | |
4485 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4486 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4487 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4488 | ||
4489 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4490 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4491 | end | |
4492 | `endif | |
4493 | `else | |
4494 | wire si_unused; | |
4495 | wire siclk_unused; | |
4496 | wire soclk_unused; | |
4497 | assign si_unused = si; | |
4498 | assign siclk_unused = siclk; | |
4499 | assign soclk_unused = soclk; | |
4500 | ||
4501 | ||
4502 | `ifdef INITLATZERO | |
4503 | initial q = 1'b0; | |
4504 | `endif | |
4505 | ||
4506 | always @(posedge l1clk) | |
4507 | begin | |
4508 | if (!siclk && !soclk) q <= d; | |
4509 | else q <= 1'bx; | |
4510 | end | |
4511 | `endif | |
4512 | ||
4513 | assign so = q; | |
4514 | ||
4515 | endmodule // dff | |
4516 | module cl_sc1_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
4517 | // RFM 05-14-2004 | |
4518 | // Level sensitive in SCAN_MODE | |
4519 | // Edge triggered when not in SCAN_MODE | |
4520 | ||
4521 | ||
4522 | parameter SIZE = 1; | |
4523 | ||
4524 | output q; | |
4525 | output so; | |
4526 | ||
4527 | input d; | |
4528 | input l1clk; | |
4529 | input si; | |
4530 | input siclk; | |
4531 | input soclk; | |
4532 | ||
4533 | reg q; | |
4534 | wire so; | |
4535 | wire l1clk, siclk, soclk; | |
4536 | ||
4537 | `ifdef SCAN_MODE | |
4538 | ||
4539 | reg l1; | |
4540 | `ifdef FAST_FLUSH | |
4541 | always @(posedge l1clk or posedge siclk ) begin | |
4542 | if (siclk) begin | |
4543 | q <= 1'b0; //pseudo flush reset | |
4544 | end else begin | |
4545 | q <= d; | |
4546 | end | |
4547 | end | |
4548 | `else | |
4549 | always @(l1clk or siclk or soclk or d or si) | |
4550 | begin | |
4551 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4552 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4553 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4554 | ||
4555 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4556 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4557 | end | |
4558 | `endif | |
4559 | `else | |
4560 | wire si_unused; | |
4561 | wire siclk_unused; | |
4562 | wire soclk_unused; | |
4563 | assign si_unused = si; | |
4564 | assign siclk_unused = siclk; | |
4565 | assign soclk_unused = soclk; | |
4566 | ||
4567 | ||
4568 | `ifdef INITLATZERO | |
4569 | initial q = 1'b0; | |
4570 | `endif | |
4571 | ||
4572 | always @(posedge l1clk) | |
4573 | begin | |
4574 | if (!siclk && !soclk) q <= d; | |
4575 | else q <= 1'bx; | |
4576 | end | |
4577 | `endif | |
4578 | ||
4579 | assign so = q; | |
4580 | ||
4581 | endmodule // dff | |
4582 | module cl_sc1_msffmin_32x ( q, so, d, l1clk, si, siclk, soclk ); | |
4583 | // RFM 05-14-2004 | |
4584 | // Level sensitive in SCAN_MODE | |
4585 | // Edge triggered when not in SCAN_MODE | |
4586 | ||
4587 | ||
4588 | parameter SIZE = 1; | |
4589 | ||
4590 | output q; | |
4591 | output so; | |
4592 | ||
4593 | input d; | |
4594 | input l1clk; | |
4595 | input si; | |
4596 | input siclk; | |
4597 | input soclk; | |
4598 | ||
4599 | reg q; | |
4600 | wire so; | |
4601 | wire l1clk, siclk, soclk; | |
4602 | ||
4603 | `ifdef SCAN_MODE | |
4604 | ||
4605 | reg l1; | |
4606 | `ifdef FAST_FLUSH | |
4607 | always @(posedge l1clk or posedge siclk ) begin | |
4608 | if (siclk) begin | |
4609 | q <= 1'b0; //pseudo flush reset | |
4610 | end else begin | |
4611 | q <= d; | |
4612 | end | |
4613 | end | |
4614 | `else | |
4615 | always @(l1clk or siclk or soclk or d or si) | |
4616 | begin | |
4617 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4618 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4619 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4620 | ||
4621 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4622 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4623 | end | |
4624 | `endif | |
4625 | `else | |
4626 | wire si_unused; | |
4627 | wire siclk_unused; | |
4628 | wire soclk_unused; | |
4629 | assign si_unused = si; | |
4630 | assign siclk_unused = siclk; | |
4631 | assign soclk_unused = soclk; | |
4632 | ||
4633 | ||
4634 | `ifdef INITLATZERO | |
4635 | initial q = 1'b0; | |
4636 | `endif | |
4637 | ||
4638 | always @(posedge l1clk) | |
4639 | begin | |
4640 | if (!siclk && !soclk) q <= d; | |
4641 | else q <= 1'bx; | |
4642 | end | |
4643 | `endif | |
4644 | ||
4645 | assign so = q; | |
4646 | ||
4647 | endmodule // dff | |
4648 | module cl_sc1_msffmin_1x ( q, so, d, l1clk, si, siclk, soclk ); | |
4649 | // RFM 05-14-2004 | |
4650 | // Level sensitive in SCAN_MODE | |
4651 | // Edge triggered when not in SCAN_MODE | |
4652 | ||
4653 | ||
4654 | parameter SIZE = 1; | |
4655 | ||
4656 | output q; | |
4657 | output so; | |
4658 | ||
4659 | input d; | |
4660 | input l1clk; | |
4661 | input si; | |
4662 | input siclk; | |
4663 | input soclk; | |
4664 | ||
4665 | reg q; | |
4666 | wire so; | |
4667 | wire l1clk, siclk, soclk; | |
4668 | ||
4669 | `ifdef SCAN_MODE | |
4670 | ||
4671 | reg l1; | |
4672 | `ifdef FAST_FLUSH | |
4673 | always @(posedge l1clk or posedge siclk ) begin | |
4674 | if (siclk) begin | |
4675 | q <= 1'b0; //pseudo flush reset | |
4676 | end else begin | |
4677 | q <= d; | |
4678 | end | |
4679 | end | |
4680 | `else | |
4681 | always @(l1clk or siclk or soclk or d or si) | |
4682 | begin | |
4683 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4684 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4685 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4686 | ||
4687 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4688 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4689 | end | |
4690 | `endif | |
4691 | `else | |
4692 | wire si_unused; | |
4693 | wire siclk_unused; | |
4694 | wire soclk_unused; | |
4695 | assign si_unused = si; | |
4696 | assign siclk_unused = siclk; | |
4697 | assign soclk_unused = soclk; | |
4698 | ||
4699 | ||
4700 | `ifdef INITLATZERO | |
4701 | initial q = 1'b0; | |
4702 | `endif | |
4703 | ||
4704 | always @(posedge l1clk) | |
4705 | begin | |
4706 | if (!siclk && !soclk) q <= d; | |
4707 | else q <= 1'bx; | |
4708 | end | |
4709 | `endif | |
4710 | ||
4711 | assign so = q; | |
4712 | ||
4713 | endmodule // dff | |
4714 | module cl_sc1_msff_lp_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
4715 | // RFM 05-14-2004 | |
4716 | // Level sensitive in SCAN_MODE | |
4717 | // Edge triggered when not in SCAN_MODE | |
4718 | ||
4719 | ||
4720 | parameter SIZE = 1; | |
4721 | ||
4722 | output q; | |
4723 | output so; | |
4724 | ||
4725 | input d; | |
4726 | input l1clk; | |
4727 | input si; | |
4728 | input siclk; | |
4729 | input soclk; | |
4730 | ||
4731 | reg q; | |
4732 | wire so; | |
4733 | wire l1clk, siclk, soclk; | |
4734 | ||
4735 | `ifdef SCAN_MODE | |
4736 | ||
4737 | reg l1; | |
4738 | `ifdef FAST_FLUSH | |
4739 | always @(posedge l1clk or posedge siclk ) begin | |
4740 | if (siclk) begin | |
4741 | q <= 1'b0; //pseudo flush reset | |
4742 | end else begin | |
4743 | q <= d; | |
4744 | end | |
4745 | end | |
4746 | `else | |
4747 | always @(l1clk or siclk or soclk or d or si) | |
4748 | begin | |
4749 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4750 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4751 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4752 | ||
4753 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4754 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4755 | end | |
4756 | `endif | |
4757 | `else | |
4758 | wire si_unused; | |
4759 | wire siclk_unused; | |
4760 | wire soclk_unused; | |
4761 | assign si_unused = si; | |
4762 | assign siclk_unused = siclk; | |
4763 | assign soclk_unused = soclk; | |
4764 | ||
4765 | ||
4766 | `ifdef INITLATZERO | |
4767 | initial q = 1'b0; | |
4768 | `endif | |
4769 | ||
4770 | always @(posedge l1clk) | |
4771 | begin | |
4772 | if (!siclk && !soclk) q <= d; | |
4773 | else q <= 1'bx; | |
4774 | end | |
4775 | `endif | |
4776 | ||
4777 | assign so = q; | |
4778 | ||
4779 | endmodule // dff | |
4780 | ||
4781 | ||
4782 | module cl_sc1_msff_16x ( q, so, d, l1clk, si, siclk, soclk ); | |
4783 | // RFM 05-14-2004 | |
4784 | // Level sensitive in SCAN_MODE | |
4785 | // Edge triggered when not in SCAN_MODE | |
4786 | ||
4787 | ||
4788 | parameter SIZE = 1; | |
4789 | ||
4790 | output q; | |
4791 | output so; | |
4792 | ||
4793 | input d; | |
4794 | input l1clk; | |
4795 | input si; | |
4796 | input siclk; | |
4797 | input soclk; | |
4798 | ||
4799 | reg q; | |
4800 | wire so; | |
4801 | wire l1clk, siclk, soclk; | |
4802 | ||
4803 | `ifdef SCAN_MODE | |
4804 | ||
4805 | reg l1; | |
4806 | `ifdef INITLATZERO | |
4807 | initial l1 = 1'b0; | |
4808 | initial q = 1'b0; | |
4809 | `endif | |
4810 | ||
4811 | `ifdef FAST_FLUSH | |
4812 | always @(posedge l1clk or posedge siclk ) begin | |
4813 | if (siclk) begin | |
4814 | q <= 1'b0; //pseudo flush reset | |
4815 | end else begin | |
4816 | q <= d; | |
4817 | end | |
4818 | end | |
4819 | `else | |
4820 | always @(l1clk or siclk or soclk or d or si) | |
4821 | begin | |
4822 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4823 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4824 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4825 | ||
4826 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4827 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4828 | end | |
4829 | `endif | |
4830 | `else | |
4831 | wire si_unused; | |
4832 | wire siclk_unused; | |
4833 | wire soclk_unused; | |
4834 | assign si_unused = si; | |
4835 | assign siclk_unused = siclk; | |
4836 | assign soclk_unused = soclk; | |
4837 | ||
4838 | ||
4839 | `ifdef INITLATZERO | |
4840 | initial q = 1'b0; | |
4841 | `endif | |
4842 | ||
4843 | always @(posedge l1clk) | |
4844 | begin | |
4845 | if (!siclk && !soclk) q <= d; | |
4846 | else q <= 1'bx; | |
4847 | end | |
4848 | `endif | |
4849 | ||
4850 | assign so = q; | |
4851 | ||
4852 | endmodule // dff | |
4853 | module cl_sc1_msff_1x ( q, so, d, l1clk, si, siclk, soclk ); | |
4854 | // RFM 05-14-2004 | |
4855 | // Level sensitive in SCAN_MODE | |
4856 | // Edge triggered when not in SCAN_MODE | |
4857 | ||
4858 | ||
4859 | parameter SIZE = 1; | |
4860 | ||
4861 | output q; | |
4862 | output so; | |
4863 | ||
4864 | input d; | |
4865 | input l1clk; | |
4866 | input si; | |
4867 | input siclk; | |
4868 | input soclk; | |
4869 | ||
4870 | reg q; | |
4871 | wire so; | |
4872 | wire l1clk, siclk, soclk; | |
4873 | ||
4874 | `ifdef SCAN_MODE | |
4875 | reg l1; | |
4876 | ||
4877 | `ifdef INITLATZERO | |
4878 | initial l1 = 1'b0; | |
4879 | initial q = 1'b0; | |
4880 | `endif | |
4881 | `ifdef FAST_FLUSH | |
4882 | always @(posedge l1clk or posedge siclk ) begin | |
4883 | if (siclk) begin | |
4884 | q <= 1'b0; //pseudo flush reset | |
4885 | end else begin | |
4886 | q <= d; | |
4887 | end | |
4888 | end | |
4889 | `else | |
4890 | always @(l1clk or siclk or soclk or d or si) | |
4891 | begin | |
4892 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4893 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4894 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4895 | ||
4896 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4897 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4898 | end | |
4899 | `endif | |
4900 | `else | |
4901 | wire si_unused; | |
4902 | wire siclk_unused; | |
4903 | wire soclk_unused; | |
4904 | assign si_unused = si; | |
4905 | assign siclk_unused = siclk; | |
4906 | assign soclk_unused = soclk; | |
4907 | ||
4908 | ||
4909 | `ifdef INITLATZERO | |
4910 | initial q = 1'b0; | |
4911 | `endif | |
4912 | ||
4913 | always @(posedge l1clk) | |
4914 | begin | |
4915 | if (!siclk && !soclk) q <= d; | |
4916 | else q <= 1'bx; | |
4917 | end | |
4918 | `endif | |
4919 | ||
4920 | assign so = q; | |
4921 | ||
4922 | endmodule // dff | |
4923 | ||
4924 | ||
4925 | module cl_sc1_msff_32x ( q, so, d, l1clk, si, siclk, soclk ); | |
4926 | // RFM 05-14-2004 | |
4927 | // Level sensitive in SCAN_MODE | |
4928 | // Edge triggered when not in SCAN_MODE | |
4929 | ||
4930 | ||
4931 | parameter SIZE = 1; | |
4932 | ||
4933 | output q; | |
4934 | output so; | |
4935 | ||
4936 | input d; | |
4937 | input l1clk; | |
4938 | input si; | |
4939 | input siclk; | |
4940 | input soclk; | |
4941 | ||
4942 | reg q; | |
4943 | wire so; | |
4944 | wire l1clk, siclk, soclk; | |
4945 | ||
4946 | `ifdef SCAN_MODE | |
4947 | reg l1; | |
4948 | ||
4949 | `ifdef INITLATZERO | |
4950 | initial l1 = 1'b0; | |
4951 | initial q = 1'b0; | |
4952 | `endif | |
4953 | `ifdef FAST_FLUSH | |
4954 | always @(posedge l1clk or posedge siclk ) begin | |
4955 | if (siclk) begin | |
4956 | q <= 1'b0; //pseudo flush reset | |
4957 | end else begin | |
4958 | q <= d; | |
4959 | end | |
4960 | end | |
4961 | `else | |
4962 | ||
4963 | always @(l1clk or siclk or soclk or d or si) | |
4964 | begin | |
4965 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4966 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4967 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4968 | ||
4969 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4970 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4971 | end | |
4972 | `endif | |
4973 | `else | |
4974 | wire si_unused; | |
4975 | wire siclk_unused; | |
4976 | wire soclk_unused; | |
4977 | assign si_unused = si; | |
4978 | assign siclk_unused = siclk; | |
4979 | assign soclk_unused = soclk; | |
4980 | ||
4981 | ||
4982 | `ifdef INITLATZERO | |
4983 | initial q = 1'b0; | |
4984 | `endif | |
4985 | ||
4986 | always @(posedge l1clk) | |
4987 | begin | |
4988 | if (!siclk && !soclk) q <= d; | |
4989 | else q <= 1'bx; | |
4990 | end | |
4991 | `endif | |
4992 | ||
4993 | assign so = q; | |
4994 | ||
4995 | endmodule // dff | |
4996 | module cl_sc1_msff_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
4997 | // RFM 05-14-2004 | |
4998 | // Level sensitive in SCAN_MODE | |
4999 | // Edge triggered when not in SCAN_MODE | |
5000 | ||
5001 | ||
5002 | parameter SIZE = 1; | |
5003 | ||
5004 | output q; | |
5005 | output so; | |
5006 | ||
5007 | input d; | |
5008 | input l1clk; | |
5009 | input si; | |
5010 | input siclk; | |
5011 | input soclk; | |
5012 | ||
5013 | reg q; | |
5014 | wire so; | |
5015 | wire l1clk, siclk, soclk; | |
5016 | ||
5017 | `ifdef SCAN_MODE | |
5018 | ||
5019 | reg l1; | |
5020 | ||
5021 | `ifdef INITLATZERO | |
5022 | initial l1 = 1'b0; | |
5023 | initial q = 1'b0; | |
5024 | `endif | |
5025 | `ifdef FAST_FLUSH | |
5026 | always @(posedge l1clk or posedge siclk ) begin | |
5027 | if (siclk) begin | |
5028 | q <= 1'b0; //pseudo flush reset | |
5029 | end else begin | |
5030 | q <= d; | |
5031 | end | |
5032 | end | |
5033 | `else | |
5034 | always @(l1clk or siclk or soclk or d or si) | |
5035 | begin | |
5036 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5037 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5038 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5039 | ||
5040 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5041 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5042 | end | |
5043 | `endif | |
5044 | `else | |
5045 | wire si_unused; | |
5046 | wire siclk_unused; | |
5047 | wire soclk_unused; | |
5048 | assign si_unused = si; | |
5049 | assign siclk_unused = siclk; | |
5050 | assign soclk_unused = soclk; | |
5051 | ||
5052 | ||
5053 | `ifdef INITLATZERO | |
5054 | initial q = 1'b0; | |
5055 | `endif | |
5056 | ||
5057 | always @(posedge l1clk) | |
5058 | begin | |
5059 | if (!siclk && !soclk) q <= d; | |
5060 | else q <= 1'bx; | |
5061 | end | |
5062 | `endif | |
5063 | ||
5064 | assign so = q; | |
5065 | ||
5066 | endmodule // dff | |
5067 | ||
5068 | `ifdef FPGA | |
5069 | `else | |
5070 | ||
5071 | module cl_sc1_msff_8x ( q, so, d, l1clk, si, siclk, soclk ); | |
5072 | // RFM 05-14-2004 | |
5073 | // Level sensitive in SCAN_MODE | |
5074 | // Edge triggered when not in SCAN_MODE | |
5075 | ||
5076 | ||
5077 | parameter SIZE = 1; | |
5078 | ||
5079 | output q; | |
5080 | output so; | |
5081 | ||
5082 | input d; | |
5083 | input l1clk; | |
5084 | input si; | |
5085 | input siclk; | |
5086 | input soclk; | |
5087 | ||
5088 | reg q; | |
5089 | wire so; | |
5090 | wire l1clk, siclk, soclk; | |
5091 | ||
5092 | `ifdef SCAN_MODE | |
5093 | reg l1; | |
5094 | ||
5095 | `ifdef INITLATZERO | |
5096 | initial l1 = 1'b0; | |
5097 | initial q = 1'b0; | |
5098 | `endif | |
5099 | `ifdef FAST_FLUSH | |
5100 | always @(posedge l1clk or posedge siclk ) begin | |
5101 | if (siclk) begin | |
5102 | q <= 1'b0; //pseudo flush reset | |
5103 | end else begin | |
5104 | q <= d; | |
5105 | end | |
5106 | end | |
5107 | `else | |
5108 | ||
5109 | always @(l1clk or siclk or soclk or d or si) | |
5110 | begin | |
5111 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5112 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5113 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5114 | ||
5115 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5116 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5117 | end | |
5118 | `endif | |
5119 | `else | |
5120 | wire si_unused; | |
5121 | wire siclk_unused; | |
5122 | wire soclk_unused; | |
5123 | assign si_unused = si; | |
5124 | assign siclk_unused = siclk; | |
5125 | assign soclk_unused = soclk; | |
5126 | ||
5127 | ||
5128 | `ifdef INITLATZERO | |
5129 | initial q = 1'b0; | |
5130 | `endif | |
5131 | ||
5132 | always @(posedge l1clk) | |
5133 | begin | |
5134 | if (!siclk && !soclk) q <= d; | |
5135 | else q <= 1'bx; | |
5136 | end | |
5137 | `endif | |
5138 | ||
5139 | assign so = q; | |
5140 | ||
5141 | endmodule // dff | |
5142 | `endif // `ifdef FPGA | |
5143 | ||
5144 | module cl_sc1_msff_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
5145 | // RFM 05-14-2004 | |
5146 | // Level sensitive in SCAN_MODE | |
5147 | // Edge triggered when not in SCAN_MODE | |
5148 | ||
5149 | ||
5150 | parameter SIZE = 1; | |
5151 | ||
5152 | output q; | |
5153 | output so; | |
5154 | ||
5155 | input d; | |
5156 | input l1clk; | |
5157 | input si; | |
5158 | input siclk; | |
5159 | input soclk; | |
5160 | input reset; | |
5161 | reg q; | |
5162 | wire so; | |
5163 | wire l1clk, siclk, soclk; | |
5164 | ||
5165 | `ifdef SCAN_MODE | |
5166 | reg l1; | |
5167 | `ifdef FAST_FLUSH | |
5168 | always @(l1clk or siclk or d ) // vcs optimized code | |
5169 | begin | |
5170 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5171 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
5172 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
5173 | l1 <= 1'b0; | |
5174 | q <= 1'b0; | |
5175 | end | |
5176 | end | |
5177 | `else | |
5178 | always @(l1clk or siclk or soclk or d or si) | |
5179 | begin | |
5180 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5181 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5182 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5183 | ||
5184 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5185 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5186 | end | |
5187 | `endif | |
5188 | `else | |
5189 | wire si_unused; | |
5190 | wire siclk_unused; | |
5191 | wire soclk_unused; | |
5192 | assign si_unused = si; | |
5193 | assign siclk_unused = siclk; | |
5194 | assign soclk_unused = soclk; | |
5195 | ||
5196 | ||
5197 | `ifdef INITLATZERO | |
5198 | initial q = 1'b0; | |
5199 | `endif | |
5200 | ||
5201 | always @(posedge l1clk) | |
5202 | begin | |
5203 | if (!siclk && !soclk) q <= (d&reset); | |
5204 | else q <= 1'bx; | |
5205 | end | |
5206 | `endif | |
5207 | ||
5208 | assign so = q; | |
5209 | ||
5210 | endmodule // dff | |
5211 | module cl_sc1_msff_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
5212 | // RFM 05-14-2004 | |
5213 | // Level sensitive in SCAN_MODE | |
5214 | // Edge triggered when not in SCAN_MODE | |
5215 | ||
5216 | ||
5217 | parameter SIZE = 1; | |
5218 | ||
5219 | output q; | |
5220 | output so; | |
5221 | ||
5222 | input d; | |
5223 | input l1clk; | |
5224 | input si; | |
5225 | input siclk; | |
5226 | input soclk; | |
5227 | input reset; | |
5228 | reg q; | |
5229 | wire so; | |
5230 | wire l1clk, siclk, soclk; | |
5231 | ||
5232 | `ifdef SCAN_MODE | |
5233 | ||
5234 | reg l1; | |
5235 | `ifdef FAST_FLUSH | |
5236 | always @(l1clk or siclk or d ) // vcs optimized code | |
5237 | begin | |
5238 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5239 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
5240 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
5241 | l1 <= 1'b0; | |
5242 | q <= 1'b0; | |
5243 | end | |
5244 | end | |
5245 | `else | |
5246 | always @(l1clk or siclk or soclk or d or si) | |
5247 | begin | |
5248 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5249 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5250 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5251 | ||
5252 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5253 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5254 | end | |
5255 | `endif | |
5256 | `else | |
5257 | wire si_unused; | |
5258 | wire siclk_unused; | |
5259 | wire soclk_unused; | |
5260 | assign si_unused = si; | |
5261 | assign siclk_unused = siclk; | |
5262 | assign soclk_unused = soclk; | |
5263 | ||
5264 | ||
5265 | `ifdef INITLATZERO | |
5266 | initial q = 1'b0; | |
5267 | `endif | |
5268 | ||
5269 | always @(posedge l1clk) | |
5270 | begin | |
5271 | if (!siclk && !soclk) q <= (d&reset); | |
5272 | else q <= 1'bx; | |
5273 | end | |
5274 | `endif | |
5275 | ||
5276 | assign so = q; | |
5277 | ||
5278 | endmodule // dff | |
5279 | module cl_sc1_msff_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
5280 | // RFM 05-14-2004 | |
5281 | // Level sensitive in SCAN_MODE | |
5282 | // Edge triggered when not in SCAN_MODE | |
5283 | ||
5284 | ||
5285 | parameter SIZE = 1; | |
5286 | ||
5287 | output q; | |
5288 | output so; | |
5289 | ||
5290 | input d; | |
5291 | input l1clk; | |
5292 | input si; | |
5293 | input siclk; | |
5294 | input soclk; | |
5295 | input reset; | |
5296 | reg q; | |
5297 | wire so; | |
5298 | wire l1clk, siclk, soclk; | |
5299 | ||
5300 | `ifdef SCAN_MODE | |
5301 | ||
5302 | reg l1; | |
5303 | `ifdef FAST_FLUSH | |
5304 | always @(l1clk or siclk or d ) // vcs optimized code | |
5305 | begin | |
5306 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5307 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
5308 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
5309 | l1 <= 1'b0; | |
5310 | q <= 1'b0; | |
5311 | end | |
5312 | end | |
5313 | `else | |
5314 | always @(l1clk or siclk or soclk or d or si) | |
5315 | begin | |
5316 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5317 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5318 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5319 | ||
5320 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5321 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5322 | end | |
5323 | `endif | |
5324 | `else | |
5325 | wire si_unused; | |
5326 | wire siclk_unused; | |
5327 | wire soclk_unused; | |
5328 | assign si_unused = si; | |
5329 | assign siclk_unused = siclk; | |
5330 | assign soclk_unused = soclk; | |
5331 | ||
5332 | ||
5333 | `ifdef INITLATZERO | |
5334 | initial q = 1'b0; | |
5335 | `endif | |
5336 | ||
5337 | always @(posedge l1clk) | |
5338 | begin | |
5339 | if (!siclk && !soclk) q <= (d&reset); | |
5340 | else q <= 1'bx; | |
5341 | end | |
5342 | `endif | |
5343 | ||
5344 | assign so = q; | |
5345 | ||
5346 | endmodule // dff | |
5347 | module cl_sc1_msff_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
5348 | // RFM 05-14-2004 | |
5349 | // Level sensitive in SCAN_MODE | |
5350 | // Edge triggered when not in SCAN_MODE | |
5351 | ||
5352 | ||
5353 | parameter SIZE = 1; | |
5354 | ||
5355 | output q; | |
5356 | output so; | |
5357 | ||
5358 | input d; | |
5359 | input l1clk; | |
5360 | input si; | |
5361 | input siclk; | |
5362 | input soclk; | |
5363 | input reset; | |
5364 | reg q; | |
5365 | wire so; | |
5366 | wire l1clk, siclk, soclk; | |
5367 | ||
5368 | `ifdef SCAN_MODE | |
5369 | ||
5370 | reg l1; | |
5371 | `ifdef FAST_FLUSH | |
5372 | always @(l1clk or siclk or d ) // vcs optimized code | |
5373 | begin | |
5374 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5375 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
5376 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
5377 | l1 <= 1'b0; | |
5378 | q <= 1'b0; | |
5379 | end | |
5380 | end | |
5381 | `else | |
5382 | always @(l1clk or siclk or soclk or d or si) | |
5383 | begin | |
5384 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5385 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5386 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5387 | ||
5388 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5389 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5390 | end | |
5391 | `endif | |
5392 | `else | |
5393 | wire si_unused; | |
5394 | wire siclk_unused; | |
5395 | wire soclk_unused; | |
5396 | assign si_unused = si; | |
5397 | assign siclk_unused = siclk; | |
5398 | assign soclk_unused = soclk; | |
5399 | ||
5400 | ||
5401 | `ifdef INITLATZERO | |
5402 | initial q = 1'b0; | |
5403 | `endif | |
5404 | ||
5405 | always @(posedge l1clk) | |
5406 | begin | |
5407 | if (!siclk && !soclk) q <= (d&reset); | |
5408 | else q <= 1'bx; | |
5409 | end | |
5410 | `endif | |
5411 | ||
5412 | assign so = q; | |
5413 | ||
5414 | endmodule // dff | |
5415 | module cl_sc1_msff_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
5416 | // RFM 05-14-2004 | |
5417 | // Level sensitive in SCAN_MODE | |
5418 | // Edge triggered when not in SCAN_MODE | |
5419 | ||
5420 | ||
5421 | parameter SIZE = 1; | |
5422 | ||
5423 | output q; | |
5424 | output so; | |
5425 | ||
5426 | input d; | |
5427 | input l1clk; | |
5428 | input si; | |
5429 | input siclk; | |
5430 | input soclk; | |
5431 | input reset; | |
5432 | reg q; | |
5433 | wire so; | |
5434 | wire l1clk, siclk, soclk; | |
5435 | ||
5436 | `ifdef SCAN_MODE | |
5437 | ||
5438 | reg l1; | |
5439 | `ifdef FAST_FLUSH | |
5440 | always @(l1clk or siclk or d ) // vcs optimized code | |
5441 | begin | |
5442 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5443 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
5444 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
5445 | l1 <= 1'b0; | |
5446 | q <= 1'b0; | |
5447 | end | |
5448 | end | |
5449 | `else | |
5450 | always @(l1clk or siclk or soclk or d or si) | |
5451 | begin | |
5452 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5453 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5454 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5455 | ||
5456 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5457 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5458 | end | |
5459 | `endif | |
5460 | `else | |
5461 | wire si_unused; | |
5462 | wire siclk_unused; | |
5463 | wire soclk_unused; | |
5464 | assign si_unused = si; | |
5465 | assign siclk_unused = siclk; | |
5466 | assign soclk_unused = soclk; | |
5467 | ||
5468 | ||
5469 | `ifdef INITLATZERO | |
5470 | initial q = 1'b0; | |
5471 | `endif | |
5472 | ||
5473 | always @(posedge l1clk) | |
5474 | begin | |
5475 | if (!siclk && !soclk) q <= (d&reset); | |
5476 | else q <= 1'bx; | |
5477 | end | |
5478 | `endif | |
5479 | ||
5480 | assign so = q; | |
5481 | ||
5482 | endmodule // dff | |
5483 | ||
5484 | ||
5485 | module cl_sc1_msffi_16x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
5486 | // RFM 05-14-2004 | |
5487 | // Level sensitive in SCAN_MODE | |
5488 | // Edge triggered when not in SCAN_MODE | |
5489 | ||
5490 | ||
5491 | parameter SIZE = 1; | |
5492 | ||
5493 | output q_l; | |
5494 | output so; | |
5495 | ||
5496 | input d; | |
5497 | input l1clk; | |
5498 | input si; | |
5499 | input siclk; | |
5500 | input soclk; | |
5501 | ||
5502 | reg q_l; | |
5503 | reg q; | |
5504 | wire so; | |
5505 | wire l1clk, siclk, soclk; | |
5506 | ||
5507 | `ifdef SCAN_MODE | |
5508 | reg l1; | |
5509 | `ifdef FAST_FLUSH | |
5510 | always @(posedge l1clk or posedge siclk ) begin | |
5511 | if (siclk) begin | |
5512 | q <= 1'b0; //pseudo flush reset | |
5513 | end else begin | |
5514 | q <= d; | |
5515 | end | |
5516 | end | |
5517 | `else | |
5518 | ||
5519 | always @(l1clk or siclk or soclk or d or si) | |
5520 | begin | |
5521 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5522 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5523 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5524 | ||
5525 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5526 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5527 | end | |
5528 | `endif | |
5529 | `else | |
5530 | wire si_unused; | |
5531 | wire siclk_unused; | |
5532 | wire soclk_unused; | |
5533 | assign si_unused = si; | |
5534 | assign siclk_unused = siclk; | |
5535 | assign soclk_unused = soclk; | |
5536 | ||
5537 | ||
5538 | `ifdef INITLATZERO | |
5539 | initial q_l = 1'b1; | |
5540 | initial q = 1'b0; | |
5541 | `endif | |
5542 | ||
5543 | always @(posedge l1clk) | |
5544 | begin | |
5545 | if (!siclk && !soclk) q <= d; | |
5546 | else q <= 1'bx; | |
5547 | end | |
5548 | `endif | |
5549 | ||
5550 | ||
5551 | always @ (q) | |
5552 | begin | |
5553 | q_l=~q; | |
5554 | end | |
5555 | ||
5556 | ||
5557 | ||
5558 | assign so = q; | |
5559 | ||
5560 | endmodule // dff | |
5561 | ||
5562 | module cl_sc1_msffi_1x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
5563 | // RFM 05-14-2004 | |
5564 | // Level sensitive in SCAN_MODE | |
5565 | // Edge triggered when not in SCAN_MODE | |
5566 | ||
5567 | ||
5568 | parameter SIZE = 1; | |
5569 | ||
5570 | output q_l; | |
5571 | output so; | |
5572 | ||
5573 | input d; | |
5574 | input l1clk; | |
5575 | input si; | |
5576 | input siclk; | |
5577 | input soclk; | |
5578 | ||
5579 | reg q_l; | |
5580 | reg q; | |
5581 | wire so; | |
5582 | wire l1clk, siclk, soclk; | |
5583 | ||
5584 | `ifdef SCAN_MODE | |
5585 | ||
5586 | reg l1; | |
5587 | `ifdef FAST_FLUSH | |
5588 | always @(posedge l1clk or posedge siclk ) begin | |
5589 | if (siclk) begin | |
5590 | q <= 1'b0; //pseudo flush reset | |
5591 | end else begin | |
5592 | q <= d; | |
5593 | end | |
5594 | end | |
5595 | `else | |
5596 | always @(l1clk or siclk or soclk or d or si) | |
5597 | begin | |
5598 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5599 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5600 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5601 | ||
5602 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5603 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5604 | end | |
5605 | `endif | |
5606 | `else | |
5607 | wire si_unused; | |
5608 | wire siclk_unused; | |
5609 | wire soclk_unused; | |
5610 | assign si_unused = si; | |
5611 | assign siclk_unused = siclk; | |
5612 | assign soclk_unused = soclk; | |
5613 | ||
5614 | ||
5615 | `ifdef INITLATZERO | |
5616 | initial q_l = 1'b1; | |
5617 | initial q = 1'b0; | |
5618 | `endif | |
5619 | ||
5620 | always @(posedge l1clk) | |
5621 | begin | |
5622 | if (!siclk && !soclk) q <= d; | |
5623 | else q <= 1'bx; | |
5624 | end | |
5625 | `endif | |
5626 | ||
5627 | ||
5628 | always @ (q) | |
5629 | begin | |
5630 | q_l=~q; | |
5631 | end | |
5632 | ||
5633 | ||
5634 | ||
5635 | assign so = q; | |
5636 | ||
5637 | endmodule // dff | |
5638 | ||
5639 | ||
5640 | module cl_sc1_msffi_32x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
5641 | // RFM 05-14-2004 | |
5642 | // Level sensitive in SCAN_MODE | |
5643 | // Edge triggered when not in SCAN_MODE | |
5644 | ||
5645 | ||
5646 | parameter SIZE = 1; | |
5647 | ||
5648 | output q_l; | |
5649 | output so; | |
5650 | ||
5651 | input d; | |
5652 | input l1clk; | |
5653 | input si; | |
5654 | input siclk; | |
5655 | input soclk; | |
5656 | ||
5657 | reg q_l; | |
5658 | reg q; | |
5659 | wire so; | |
5660 | wire l1clk, siclk, soclk; | |
5661 | ||
5662 | `ifdef SCAN_MODE | |
5663 | reg l1; | |
5664 | `ifdef FAST_FLUSH | |
5665 | always @(posedge l1clk or posedge siclk ) begin | |
5666 | if (siclk) begin | |
5667 | q <= 1'b0; //pseudo flush reset | |
5668 | end else begin | |
5669 | q <= d; | |
5670 | end | |
5671 | end | |
5672 | `else | |
5673 | ||
5674 | always @(l1clk or siclk or soclk or d or si) | |
5675 | begin | |
5676 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5677 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5678 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5679 | ||
5680 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5681 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5682 | end | |
5683 | `endif | |
5684 | `else | |
5685 | wire si_unused; | |
5686 | wire siclk_unused; | |
5687 | wire soclk_unused; | |
5688 | assign si_unused = si; | |
5689 | assign siclk_unused = siclk; | |
5690 | assign soclk_unused = soclk; | |
5691 | ||
5692 | ||
5693 | `ifdef INITLATZERO | |
5694 | initial q_l = 1'b1; | |
5695 | initial q = 1'b0; | |
5696 | `endif | |
5697 | ||
5698 | always @(posedge l1clk) | |
5699 | begin | |
5700 | if (!siclk && !soclk) q <= d; | |
5701 | else q <= 1'bx; | |
5702 | end | |
5703 | `endif | |
5704 | ||
5705 | ||
5706 | always @ (q) | |
5707 | begin | |
5708 | q_l=~q; | |
5709 | end | |
5710 | ||
5711 | ||
5712 | ||
5713 | assign so = q; | |
5714 | ||
5715 | endmodule // dff | |
5716 | ||
5717 | ||
5718 | module cl_sc1_msffi_4x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
5719 | // RFM 05-14-2004 | |
5720 | // Level sensitive in SCAN_MODE | |
5721 | // Edge triggered when not in SCAN_MODE | |
5722 | ||
5723 | ||
5724 | parameter SIZE = 1; | |
5725 | ||
5726 | output q_l; | |
5727 | output so; | |
5728 | ||
5729 | input d; | |
5730 | input l1clk; | |
5731 | input si; | |
5732 | input siclk; | |
5733 | input soclk; | |
5734 | ||
5735 | reg q_l; | |
5736 | reg q; | |
5737 | wire so; | |
5738 | wire l1clk, siclk, soclk; | |
5739 | ||
5740 | `ifdef SCAN_MODE | |
5741 | reg l1; | |
5742 | `ifdef FAST_FLUSH | |
5743 | always @(posedge l1clk or posedge siclk ) begin | |
5744 | if (siclk) begin | |
5745 | q <= 1'b0; //pseudo flush reset | |
5746 | end else begin | |
5747 | q <= d; | |
5748 | end | |
5749 | end | |
5750 | `else | |
5751 | ||
5752 | always @(l1clk or siclk or soclk or d or si) | |
5753 | begin | |
5754 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5755 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5756 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5757 | ||
5758 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5759 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5760 | end | |
5761 | `endif | |
5762 | `else | |
5763 | wire si_unused; | |
5764 | wire siclk_unused; | |
5765 | wire soclk_unused; | |
5766 | assign si_unused = si; | |
5767 | assign siclk_unused = siclk; | |
5768 | assign soclk_unused = soclk; | |
5769 | ||
5770 | ||
5771 | `ifdef INITLATZERO | |
5772 | initial q_l = 1'b1; | |
5773 | initial q = 1'b0; | |
5774 | `endif | |
5775 | ||
5776 | always @(posedge l1clk) | |
5777 | begin | |
5778 | if (!siclk && !soclk) q <= d; | |
5779 | else q <= 1'bx; | |
5780 | end | |
5781 | `endif | |
5782 | ||
5783 | ||
5784 | always @ (q) | |
5785 | begin | |
5786 | q_l=~q; | |
5787 | end | |
5788 | ||
5789 | ||
5790 | ||
5791 | assign so = q; | |
5792 | ||
5793 | endmodule // dff | |
5794 | ||
5795 | module cl_sc1_msffi_8x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
5796 | // RFM 05-14-2004 | |
5797 | // Level sensitive in SCAN_MODE | |
5798 | // Edge triggered when not in SCAN_MODE | |
5799 | ||
5800 | ||
5801 | parameter SIZE = 1; | |
5802 | ||
5803 | output q_l; | |
5804 | output so; | |
5805 | ||
5806 | input d; | |
5807 | input l1clk; | |
5808 | input si; | |
5809 | input siclk; | |
5810 | input soclk; | |
5811 | ||
5812 | reg q_l; | |
5813 | reg q; | |
5814 | wire so; | |
5815 | wire l1clk, siclk, soclk; | |
5816 | ||
5817 | `ifdef SCAN_MODE | |
5818 | reg l1; | |
5819 | `ifdef FAST_FLUSH | |
5820 | always @(posedge l1clk or posedge siclk ) begin | |
5821 | if (siclk) begin | |
5822 | q <= 1'b0; //pseudo flush reset | |
5823 | end else begin | |
5824 | q <= d; | |
5825 | end | |
5826 | end | |
5827 | `else | |
5828 | ||
5829 | always @(l1clk or siclk or soclk or d or si) | |
5830 | begin | |
5831 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5832 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5833 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5834 | ||
5835 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5836 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5837 | end | |
5838 | `endif | |
5839 | `else | |
5840 | wire si_unused; | |
5841 | wire siclk_unused; | |
5842 | wire soclk_unused; | |
5843 | assign si_unused = si; | |
5844 | assign siclk_unused = siclk; | |
5845 | assign soclk_unused = soclk; | |
5846 | ||
5847 | ||
5848 | `ifdef INITLATZERO | |
5849 | initial q_l = 1'b1; | |
5850 | initial q = 1'b0; | |
5851 | `endif | |
5852 | ||
5853 | always @(posedge l1clk) | |
5854 | begin | |
5855 | if (!siclk && !soclk) q <= d; | |
5856 | else q <= 1'bx; | |
5857 | end | |
5858 | `endif | |
5859 | ||
5860 | ||
5861 | always @ (q) | |
5862 | begin | |
5863 | q_l=~q; | |
5864 | end | |
5865 | ||
5866 | ||
5867 | ||
5868 | assign so = q; | |
5869 | ||
5870 | endmodule // dff | |
5871 | ||
5872 | module cl_sc1_msffjtag_4x ( q, so, d, l1clk, si, siclk, soclk, reset, updateclk ); | |
5873 | ||
5874 | output q; | |
5875 | output so; | |
5876 | ||
5877 | input d; | |
5878 | input l1clk; | |
5879 | input si; | |
5880 | input siclk; | |
5881 | input soclk; | |
5882 | input reset; | |
5883 | input updateclk; | |
5884 | `ifdef LIB | |
5885 | reg q; | |
5886 | reg so; | |
5887 | wire l1clk, siclk, soclk, updateclk; | |
5888 | ||
5889 | reg l1; | |
5890 | ||
5891 | always @(l1clk or siclk or soclk or d or si or reset) | |
5892 | begin | |
5893 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5894 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5895 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5896 | if (reset) so <=1'b0; | |
5897 | if ( l1clk && !siclk && !soclk && !reset) so <= l1; // Load slave with master data | |
5898 | if ( l1clk && siclk && !soclk && !reset) so <= si; // Flush | |
5899 | end | |
5900 | ||
5901 | `ifdef INITLATZERO | |
5902 | initial q = 1'b0; | |
5903 | `endif | |
5904 | ||
5905 | ||
5906 | ||
5907 | always@(updateclk or reset or l1) | |
5908 | begin | |
5909 | if(reset) q <=1'b0; | |
5910 | else if(updateclk) q <=l1; | |
5911 | ||
5912 | ||
5913 | ||
5914 | end | |
5915 | `endif | |
5916 | endmodule | |
5917 | ||
5918 | ||
5919 | ||
5920 | ||
5921 | ||
5922 | ||
5923 | ||
5924 | ||
5925 | module cl_sc1_clksyncff_4x(l1clk, d, si, siclk, soclk, q, so); | |
5926 | input l1clk, d, si, siclk, soclk; | |
5927 | output q, so; | |
5928 | wire q1o, slo; | |
5929 | ||
5930 | cl_sc1_msff_4x xx0 ( .l1clk(l1clk), .d(d), .si(si), .siclk(siclk), .soclk(soclk), .q(q1o), .so(slo)); | |
5931 | cl_sc1_msff_4x xx1 ( .l1clk(l1clk), .d(q1o), .si(slo), .siclk(siclk), .soclk(soclk), .q(q), .so(so)); | |
5932 | endmodule | |
5933 | module cl_sc1_bs_cell2_4x(q, so, d, l1clk, si, siclk, soclk, updateclk, mode, | |
5934 | muxd, highz_n); | |
5935 | ||
5936 | output q; | |
5937 | output so; | |
5938 | ||
5939 | input d, highz_n; | |
5940 | input l1clk; | |
5941 | input si; | |
5942 | input siclk; | |
5943 | input soclk; | |
5944 | ||
5945 | input updateclk, mode, muxd; | |
5946 | ||
5947 | reg q; | |
5948 | reg so; | |
5949 | wire l1clk, siclk, soclk, updateclk; | |
5950 | ||
5951 | ||
5952 | reg l1, qm; | |
5953 | ||
5954 | always @(l1clk or siclk or soclk or d or si) | |
5955 | begin | |
5956 | if (!l1clk && !siclk) l1 <= d; | |
5957 | if ( l1clk && siclk) l1 <= si; | |
5958 | if (!l1clk && siclk) l1 <= 1'bx; | |
5959 | if ( l1clk && !soclk) so <= l1; | |
5960 | if ( l1clk && siclk && !soclk) so <= si; // Flush | |
5961 | end | |
5962 | `ifdef INITLATZERO | |
5963 | initial qm = 1'b0; | |
5964 | `endif | |
5965 | always@(updateclk or l1) | |
5966 | begin | |
5967 | if(updateclk) qm <=l1; | |
5968 | end | |
5969 | always@(mode or muxd or qm or highz_n) | |
5970 | begin | |
5971 | if(mode==0) q=(qm && highz_n); | |
5972 | else q=muxd; | |
5973 | end | |
5974 | endmodule | |
5975 | ||
5976 | module cl_sc1_clk_buf_16x ( | |
5977 | in, | |
5978 | out | |
5979 | ); | |
5980 | input in; | |
5981 | output out; | |
5982 | ||
5983 | `ifdef LIB | |
5984 | //assign out = in; | |
5985 | buf (out, in); | |
5986 | `endif | |
5987 | ||
5988 | endmodule | |
5989 | module cl_sc1_clk_buf_20x ( | |
5990 | in, | |
5991 | out | |
5992 | ); | |
5993 | input in; | |
5994 | output out; | |
5995 | ||
5996 | `ifdef LIB | |
5997 | //assign out = in; | |
5998 | buf (out, in); | |
5999 | `endif | |
6000 | ||
6001 | endmodule | |
6002 | module cl_sc1_clk_buf_24x ( | |
6003 | in, | |
6004 | out | |
6005 | ); | |
6006 | input in; | |
6007 | output out; | |
6008 | ||
6009 | `ifdef LIB | |
6010 | //assign out = in; | |
6011 | buf (out, in); | |
6012 | `endif | |
6013 | ||
6014 | endmodule | |
6015 | module cl_sc1_clk_buf_32x ( | |
6016 | in, | |
6017 | out | |
6018 | ); | |
6019 | input in; | |
6020 | output out; | |
6021 | ||
6022 | `ifdef LIB | |
6023 | //assign out = in; | |
6024 | buf (out, in); | |
6025 | `endif | |
6026 | ||
6027 | endmodule | |
6028 | module cl_sc1_clk_buf_48x ( | |
6029 | in, | |
6030 | out | |
6031 | ); | |
6032 | input in; | |
6033 | output out; | |
6034 | ||
6035 | `ifdef LIB | |
6036 | //assign out = in; | |
6037 | buf (out, in); | |
6038 | `endif | |
6039 | ||
6040 | endmodule | |
6041 | module cl_sc1_clk_buf_64x ( | |
6042 | in, | |
6043 | out | |
6044 | ); | |
6045 | input in; | |
6046 | output out; | |
6047 | ||
6048 | `ifdef LIB | |
6049 | //assign out = in; | |
6050 | buf (out, in); | |
6051 | `endif | |
6052 | ||
6053 | endmodule | |
6054 | module cl_sc1_clk_buf_8x ( | |
6055 | in, | |
6056 | out | |
6057 | ); | |
6058 | input in; | |
6059 | output out; | |
6060 | ||
6061 | `ifdef LIB | |
6062 | //assign out = in; | |
6063 | buf (out, in); | |
6064 | `endif | |
6065 | ||
6066 | endmodule | |
6067 | module cl_sc1_clk_inv_16x ( | |
6068 | in, | |
6069 | out | |
6070 | ); | |
6071 | input in; | |
6072 | output out; | |
6073 | ||
6074 | `ifdef LIB | |
6075 | //assign out = ~in; | |
6076 | not (out, in); | |
6077 | `endif | |
6078 | ||
6079 | endmodule | |
6080 | module cl_sc1_clk_inv_20x ( | |
6081 | clkin, | |
6082 | clkout | |
6083 | ); | |
6084 | input clkin; | |
6085 | output clkout; | |
6086 | ||
6087 | `ifdef LIB | |
6088 | //assign clkout = ~clkin; | |
6089 | not (clkout, clkin); | |
6090 | `endif | |
6091 | ||
6092 | endmodule | |
6093 | module cl_sc1_clk_inv_24x ( | |
6094 | in, | |
6095 | out | |
6096 | ); | |
6097 | input in; | |
6098 | output out; | |
6099 | ||
6100 | `ifdef LIB | |
6101 | //assign out = ~in; | |
6102 | not (out, in); | |
6103 | `endif | |
6104 | ||
6105 | endmodule | |
6106 | module cl_sc1_clk_inv_32x ( | |
6107 | in, | |
6108 | out | |
6109 | ); | |
6110 | input in; | |
6111 | output out; | |
6112 | ||
6113 | `ifdef LIB | |
6114 | //assign out = ~in; | |
6115 | not (out, in); | |
6116 | `endif | |
6117 | ||
6118 | endmodule | |
6119 | module cl_sc1_clk_inv_48x ( | |
6120 | in, | |
6121 | out | |
6122 | ); | |
6123 | input in; | |
6124 | output out; | |
6125 | ||
6126 | `ifdef LIB | |
6127 | //assign out = ~in; | |
6128 | not (out, in); | |
6129 | `endif | |
6130 | ||
6131 | endmodule | |
6132 | module cl_sc1_clk_inv_64x ( | |
6133 | in, | |
6134 | out | |
6135 | ); | |
6136 | input in; | |
6137 | output out; | |
6138 | ||
6139 | `ifdef LIB | |
6140 | //assign out = ~in; | |
6141 | not (out, in); | |
6142 | `endif | |
6143 | ||
6144 | endmodule | |
6145 | module cl_sc1_clk_inv_8x ( | |
6146 | clkin, | |
6147 | clkout | |
6148 | ); | |
6149 | input clkin; | |
6150 | output clkout; | |
6151 | ||
6152 | `ifdef LIB | |
6153 | //assign clkout = ~clkin; | |
6154 | not (clkout, clkin); | |
6155 | `endif | |
6156 | ||
6157 | endmodule | |
6158 | module cl_sc1_clk_mux2_16x ( | |
6159 | in0, | |
6160 | in1, | |
6161 | sel0, | |
6162 | out | |
6163 | ); | |
6164 | input in0; | |
6165 | input in1; | |
6166 | input sel0; | |
6167 | output out; | |
6168 | ||
6169 | `ifdef LIB | |
6170 | reg out; | |
6171 | always @ ( sel0 or in0 or in1) | |
6172 | case ( sel0 ) | |
6173 | 1'b1: out = in0; | |
6174 | 1'b0: out = in1; | |
6175 | ||
6176 | default: out = 1'bx; | |
6177 | ||
6178 | endcase | |
6179 | `endif | |
6180 | ||
6181 | endmodule | |
6182 | ||
6183 | module cl_sc1_clk_mux2_24x ( | |
6184 | in0, | |
6185 | in1, | |
6186 | sel0, | |
6187 | out | |
6188 | ); | |
6189 | input in0; | |
6190 | input in1; | |
6191 | input sel0; | |
6192 | output out; | |
6193 | ||
6194 | `ifdef LIB | |
6195 | reg out; | |
6196 | always @ ( sel0 or in0 or in1) | |
6197 | case ( sel0 ) | |
6198 | 1'b1: out = in0; | |
6199 | 1'b0: out = in1; | |
6200 | ||
6201 | default: out = 1'bx; | |
6202 | ||
6203 | endcase | |
6204 | `endif | |
6205 | ||
6206 | endmodule | |
6207 | ||
6208 | module cl_sc1_clk_mux2_32x ( | |
6209 | in0, | |
6210 | in1, | |
6211 | sel0, | |
6212 | out | |
6213 | ); | |
6214 | input in0; | |
6215 | input in1; | |
6216 | input sel0; | |
6217 | output out; | |
6218 | ||
6219 | `ifdef LIB | |
6220 | reg out; | |
6221 | always @ ( sel0 or in0 or in1) | |
6222 | case ( sel0 ) | |
6223 | 1'b1: out = in0; | |
6224 | 1'b0: out = in1; | |
6225 | ||
6226 | default: out = 1'bx; | |
6227 | ||
6228 | endcase | |
6229 | `endif | |
6230 | ||
6231 | endmodule | |
6232 | ||
6233 | module cl_sc1_clk_mux2_8x ( | |
6234 | in0, | |
6235 | in1, | |
6236 | sel0, | |
6237 | out | |
6238 | ); | |
6239 | input in0; | |
6240 | input in1; | |
6241 | input sel0; | |
6242 | output out; | |
6243 | ||
6244 | `ifdef LIB | |
6245 | reg out; | |
6246 | always @ ( sel0 or in0 or in1) | |
6247 | case ( sel0 ) | |
6248 | 1'b1: out = in0; | |
6249 | 1'b0: out = in1; | |
6250 | ||
6251 | default: out = 1'bx; | |
6252 | ||
6253 | endcase | |
6254 | `endif | |
6255 | ||
6256 | endmodule | |
6257 | ||
6258 | ||
6259 | ||
6260 | ||
6261 | ||
6262 | ||
6263 | ||
6264 | ||
6265 |