// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: cl_sc1.v
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// ========== Copyright Header End ============================================
module cl_sc1_msffmin_fp_16x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_fp_8x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_fp_4x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_fp_32x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_fp_1x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_fp_30ps_16x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_fp_30ps_8x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_fp_30ps_4x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_fp_30ps_32x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_fp_30ps_1x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_fp_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_msffmin_fp_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_msffmin_fp_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_msffmin_fp_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_msffmin_fp_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_msffmin_30ps_16x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_30ps_8x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_30ps_4x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_30ps_32x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_30ps_1x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_clken_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk, clken);
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d & clken ) | (q & !clken); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d & clken ) | (q & !clken);
module cl_sc1_msffmin_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_msffmin_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_msffmin_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_msffmin_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_msffmin_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_bsac_cell_4x(q, so, d, l1clk, si, siclk, soclk, updateclk,
ac_mode, ac_test_signal);
input updateclk, ac_mode;
wire l1clk, siclk, soclk, updateclk;
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
if ( l1clk && siclk) l1 <= si; // Load master with
if (!l1clk && siclk) l1 <= 1'bx; // Conflict between
if ( l1clk && !soclk) so <= l1; // Load slave with
if ( l1clk && siclk && !soclk) so <= si; // Flush
always@(ac_mode or qm or ac_test_signal)
else q=qm ^ ac_test_signal;
module cl_sc1_blatch_4x ( latout, so, d, l1clk, si, siclk, soclk);
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if(siclk==0 && l1clk==0) m = d;
else if(siclk && !l1clk) m = 1'bx;
if(siclk && l1clk) m = si;
if(l1clk && !soclk) s = m;
module cl_sc1_alatch_4x ( q, so, d, l1clk, si, siclk, soclk, se );
wire l1clk, siclk, soclk;
always @(l1clk or siclk or soclk or d or si or se)
if (siclk) l1 <= si; // Load master with scan or flush
if(se && !soclk && l1clk && siclk) q <= si;
else if ( se && !soclk && l1clk) q <= l1;
else if ( !soclk && l1clk) q <= d;
module cl_sc1_clken_msff_4x ( q, so, d, l1clk, si, siclk, soclk, clken);
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d & clken ) | (q & !clken); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d & clken ) | (q & !clken);
module cl_sc1_msff_arst_4x ( q, so, d, l1clk, si, siclk, soclk, reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or soclk or d or si or reset)
else if (!l1clk && !siclk) l1 <= d;
else if ( l1clk && siclk) l1 <= si;
else if (!l1clk && siclk) l1 <= 1'bx;
else if ( l1clk && !siclk && !soclk) q <= l1;
else if ( l1clk && siclk && !soclk) q <= si;
assign siclk_unused = siclk;
assign soclk_unused = soclk;
always @(posedge l1clk or posedge reset)
else if (!siclk && !soclk ) q <= d;
module cl_sc1_aomux2_12x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux2_16x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux2_1x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux2_2x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux2_4x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux2_6x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux2_8x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux3_12x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux3_16x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux3_1x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux3_2x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux3_4x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux3_6x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux3_8x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux4_12x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux4_16x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux4_1x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux4_2x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux4_4x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux4_6x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux4_8x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux5_12x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux5_16x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux5_1x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux5_2x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux5_4x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux5_6x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux5_8x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux6_12x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux6_16x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux6_1x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux6_2x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux6_4x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux6_6x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux6_8x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux6_by2_1x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux6_by2_2x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux7_12x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux7_16x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux7_1x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux7_2x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux7_4x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux7_6x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux7_8x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux7_by2_1x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux7_by2_2x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux8_12x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux8_16x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux8_1x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux8_2x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux8_4x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux8_6x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux8_8x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux8_by2_1x (
assign out = ((sel0 & in0) |
module cl_sc1_aomux8_by2_2x (
assign out = ((sel0 & in0) |
module cl_sc1_l1hdr_12x (
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_sc1_l1hdr_16x (
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_sc1_l1hdr_24x (
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_sc1_l1hdr_32x (
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_sc1_l1hdr_48x (
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_sc1_l1hdr_64x (
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_sc1_msffmin_16x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_8x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_32x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffmin_1x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msff_lp_4x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msff_16x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msff_1x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msff_32x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msff_4x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msff_8x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msff_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_msff_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_msff_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_msff_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_msff_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_sc1_msffi_16x ( q_l, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffi_1x ( q_l, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffi_32x ( q_l, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffi_4x ( q_l, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffi_8x ( q_l, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_sc1_msffjtag_4x ( q, so, d, l1clk, si, siclk, soclk, reset, updateclk );
wire l1clk, siclk, soclk, updateclk;
always @(l1clk or siclk or soclk or d or si or reset)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
if ( l1clk && !siclk && !soclk && !reset) so <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk && !reset) so <= si; // Flush
always@(updateclk or reset or l1)
else if(updateclk) q <=l1;
module cl_sc1_clksyncff_4x(l1clk, d, si, siclk, soclk, q, so);
input l1clk, d, si, siclk, soclk;
cl_sc1_msff_4x xx0 ( .l1clk(l1clk), .d(d), .si(si), .siclk(siclk), .soclk(soclk), .q(q1o), .so(slo));
cl_sc1_msff_4x xx1 ( .l1clk(l1clk), .d(q1o), .si(slo), .siclk(siclk), .soclk(soclk), .q(q), .so(so));
module cl_sc1_bs_cell2_4x(q, so, d, l1clk, si, siclk, soclk, updateclk, mode,
input updateclk, mode, muxd;
wire l1clk, siclk, soclk, updateclk;
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d;
if ( l1clk && siclk) l1 <= si;
if (!l1clk && siclk) l1 <= 1'bx;
if ( l1clk && !soclk) so <= l1;
if ( l1clk && siclk && !soclk) so <= si; // Flush
always@(mode or muxd or qm or highz_n)
if(mode==0) q=(qm && highz_n);
module cl_sc1_clk_buf_16x (
module cl_sc1_clk_buf_20x (
module cl_sc1_clk_buf_24x (
module cl_sc1_clk_buf_32x (
module cl_sc1_clk_buf_48x (
module cl_sc1_clk_buf_64x (
module cl_sc1_clk_buf_8x (
module cl_sc1_clk_inv_16x (
module cl_sc1_clk_inv_20x (
//assign clkout = ~clkin;
module cl_sc1_clk_inv_24x (
module cl_sc1_clk_inv_32x (
module cl_sc1_clk_inv_48x (
module cl_sc1_clk_inv_64x (
module cl_sc1_clk_inv_8x (
//assign clkout = ~clkin;
module cl_sc1_clk_mux2_16x (
always @ ( sel0 or in0 or in1)
module cl_sc1_clk_mux2_24x (
always @ ( sel0 or in0 or in1)
module cl_sc1_clk_mux2_32x (
always @ ( sel0 or in0 or in1)
module cl_sc1_clk_mux2_8x (
always @ ( sel0 or in0 or in1)