[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_piu_int_ejr.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_piu_int_ejr.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Sw_Recoverable_Error_0x40	 My_Recoverable_Sw_error_trap
    
#define MAIN_PAGE_HV_ALSO

#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
        call    my_trap_code; \
        nop; \
        retry; \
        nop; 

#include "hboot.s"
#include "peu_defines.h"
#include "ncu_defines.h"

	
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global	 My_Recoverable_Sw_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

lear_esr_first:
	setx	SOC_ESR_REG, %l7, %i0
	stx	%g0, [%i0]

set_ejr:
        set	0x1, %i1
	sllx	%i1, ERR_FIELD, %i2
	setx	SOC_EJR_REG, %l7, %i3
	stx	%i2, [%i3]
	membar	0x40


/*      Initialize the NCU for the interrupt.   */

        ! Disable interrupts


no_intr:
        rdpr    %pstate, %g7
        xor     %g7, 0x2, %g7           ! Reset interrupt enable
        wrpr    %g7, %pstate

	! Initialize NCU's Mondo Interrupt Vector Register
	! VECTOR = 63

ncu_mondo_int_vec:
	set	63, %g1
	setx	MONDO_INT_VEC, %g2, %g3
	stx	%g1, [%g3]

	! Clear NCU's Mondo Interrupt Busy registers.

ncu_mondo_int_busy:
	setx	MONDO_INT_ABUSY, %g1, %g2
	stx	%g0, [%g2]

	! Enable in MMU, TTE_INV_P, primary TTE valid bit not set error.

mmu_intr_enable_reg_init:
	setx	PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
	set	PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT, %g3
	set	1, %g4
	sllx	%g4, %g3, %g4
	stx	%g4, [%g2]

	! Enable in IMU, MSI_MAL_ERR_P, malformed MSI message error.

imu_intr_enable_reg_init:
	setx	PCI_E_IMU_INT_ENB_ADDR, %g1, %g2
	set	PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g3
	set	1, %g4
	sllx	%g4, %g3, %g4
	stx	%g4, [%g2]

        ! Initialize Interrupt Mapping register
	! Valid, thread ID 0, no interrupt controller

pci_intr_map_reg_init:
        setx    PCI_E_INT_MAP_ADDR, %g1, %g7
        setx    PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
        add     %g7, %g3, %g7
        setx    0x80000040, %g1, %g6            ! valid = 1, thread id = 0
        stx     %g6, [%g7]                      ! interrupt controller = 1

yes_intr:
        rdpr    %pstate, %g7
        or      %g7, 0x2, %g7           ! Set interrupt enable
        wrpr    %g7, %pstate

	! Enable IMU, MMU interrupts in the DMU Core and Block
	! Interrupt Enable register.

dmu_core_block_enable:
	setx	PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
	setx	PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK, %g1, %g3
	setx	PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK, %g1, %g4
	or	%g3, %g4, %g4
	setx	PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK, %g1, %g3
	or	%g3, %g4, %g4
	stx	%g4, [%g2]
	membar	#Sync

	! Generate an interrupt from the IMU block.

gen_imu_intr:
	setx	PCI_E_IMU_ERR_STAT_SET_ADDR, %g1, %g2
	set	1, %g6
	setx	PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g1, %g3
	sllx	%g6, %g3, %g6
	stx	%g6, [%g2]
	membar	#Sync

	! Wait for the interrupt trap

intr_wait1:
	setx	0x400, %g1, %g2			! timeout count
	setx	user_data_start, %g1, %g7

intr_wait_loop1:
	ld	[%g7], %g5
	cmp	%g5, 1
	be	read_esr
	nop

	cmp	%g2, 0
	be	test_failed		! time out
	nop
	ba	intr_wait_loop1
	dec	%g2


	/******************************
		Error Check
	******************************/
read_esr:
        setx	SOC_ESR_REG, %l7, %i0
	ldx	[%i0], %i1
	nop

	setx	0x8000000000000000, %l7, %o3	!valid bit
	set	0x1, %i2
	sllx	%i2, ERR_FIELD, %i3
	or	%i3, %o3, %i4
	sub	%i1, %i4, %i5
	brnz	%i5, test_failed
	nop

eie_reg_ones:
	setx    SOC_EIE_REG, %g3, %g2
	set	ERR_FIELD, %g1
	stx	%g1, [%g2]
	membar	0x40

	setx	0x40, %g7, %g6
	set	0x1, %g1			! 1 Trap
err_trap_loop:
	cmp	    %g6, %g0
	be	%xcc, test_failed
	nop

	cmp	%g1, %i7
	be	%xcc, check_tt
	nop

	ba	err_trap_loop
	nop

check_tt:
        mov	0x40, %l0
	cmp	%o7,  %l0
	bne	%xcc, test_failed
	nop


	/********************************/


test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/**********************************************************************
   Interrupt trap handler.
**********************************************************************/

.global my_trap_code

my_trap_code:

	! Record interrupt occured.

trap_intr_flag:
        setx    user_data_start, %l1, %l3
	set	1, %l1
	st	%l1, [%l3]

	! Check Mondo Interrupt Busy reg.

trap_mondo_busy:
        ta      T_RD_THID			! thread id into %o1
	setx	MONDO_INT_BUSY, %l1, %l2
	setx	MONDO_INT_BUSY_STEP, %l1, %l3
	mulx	%l3, %o1, %l3
	add	%l3, %l2, %l2
	ldx	[%l2], %l4
	and	%l4, 0x40, %l5			! Is busy bit set?
	cmp	%l5, 0
	be	test_failed
	nop

	! Clear the mondo interrupt in the PIU.

	! MMU Error Status Set reg.

trap_clear_mmu_err_set:	
	setx	PCI_E_MMU_ERR_STAT_SET_ADDR, %l1, %l2
	stx	%g0, [%l2]			! removes setting of the error

	! MMU Error Status Clear reg.

trap_mmu_err_clear:
	setx	PCI_E_MMU_ERR_STAT_CL_ADDR, %l1, %l2
	sub	%g0, 1, %l0			! a W1C register
	stx	%l0, [%l2]			! clears the error flag

	! IMU Error Status Set reg.

trap_clear_imu_err_set:	
	setx	PCI_E_IMU_ERR_STAT_SET_ADDR, %l1, %l2
	stx	%g0, [%l2]			! removes setting of the error

	! IMU Error Status Clear reg.

trap_imu_err_clear:
	setx	PCI_E_IMU_ERR_STAT_CLR_ADDR, %l1, %l2
	sub	%g0, 1, %l0			! a W1C register
	stx	%l0, [%l2]			! clears the error flag

	! Interrupt Clear reg.

trap_intr_clear:
	setx	PCI_E_INT_CLEAR_ADDR, %l1, %l2
        setx    PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
	add	%l2, %l3, %l2
	stx	%g0, [%l2]

	! Clear the mondo interrupt in the NCU

trap_mondo_intr_clear:
	setx	MONDO_INT_ABUSY, %l0, %l1
	stx	%g0, [%l1]
	membar	#Sync

	ldx	[%l1], %l2
	and	%l2, 0x40, %l2
	cmp	%l2, 0			! Busy should be cleared
	bne	test_failed
	nop

	! Clear the interrupt in the core.

trap_clear_asi_intr_r:
	ldxa	[%g0]ASI_SWVR_INTR_R, %l5
	cmp	%l5, 63			! check for correct vector number
	bne	test_failed
	nop

	! Done.

trap_done:
	jmpl    %o7+0x8, %g0
	nop


/************************************************************************
	RAS
	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
	! Signal trap taken
	setx	EXECUTED, %l0, %o6
	! save trap type value
	rdpr	%tt, %o7

	inc	%i7

check_desr_tt40:
	ldxa  [%g0]0x4c, %g2
	nop

/*
	setx	0xb300000000000000, %l0, %g3
	subcc	%g2, %g3, %g4
	brnz	%g4, l2_trap
	nop
*/

check_DSFSR_tt32:
	set	0x18, %g1
	ldxa	[%g1]0x58, %g2
	nop
	set	0x4, %g3
	subcc	%g2, %g3, %g4
	brnz	%g4, test_failed
	nop


check_per_tt40:
	setx	SOC_PER_REG, %l7, %g1
	ldx	[%g1], %g2
	setx	0x8000000000000000, %g7, %g1
	set	0x1, %g3
	sllx	%g3, ERR_FIELD, %g4
	or	%g1, %g4, %g3
	sub	%g2, %g3, %g5
	brnz	%g5, test_failed
	nop

clear_per_tt40:
	setx	SOC_PER_REG, %l7, %g1
	stx	%g0, [%g1]
	nop

clear_ejr_tt40:
	setx	SOC_EJR_REG, %l7, %g1
	stx	%g0, [%g1]
	nop

clear_eie_tt40:
	setx	SOC_EIE_REG, %l7, %g1
	stx	%g0, [%g1]
	nop

trap_done_tt40:
	done
	nop


/************************************************************************
   Test case data start
************************************************************************/

.align  1024
.data
user_data_start:
        .word   0x0
        .word   0x0
        .word   0x0
        .word   0x0
user_data_end:
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_piu_int_ejr.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	39
	40	#define MAIN_PAGE_HV_ALSO
	41
	42	#define H_HT0_Interrupt_0x60
	43	#define My_HT0_Interrupt_0x60 \
	44	call my_trap_code; \
	45	nop; \
	46	retry; \
	47	nop;
	48
	49	#include "hboot.s"
	50	#include "peu_defines.h"
	51	#include "ncu_defines.h"
	52
	53
	54	/************************************************************************
	55	Test case code start
	56	************************************************************************/
	57	.text
	58	.global main
	59	.global My_Recoverable_Sw_error_trap
	60
	61	main:
	62	ta T_CHANGE_HPRIV
	63	nop
	64
65	lear_esr_first:
66	setx SOC_ESR_REG, %l7, %i0
67	stx %g0, [%i0]
68
69	set_ejr:
70	set 0x1, %i1
71	sllx %i1, ERR_FIELD, %i2
72	setx SOC_EJR_REG, %l7, %i3
73	stx %i2, [%i3]
74	membar 0x40
75
76
77	/* Initialize the NCU for the interrupt. */
78
79	! Disable interrupts
80
81
82	no_intr:
83	rdpr %pstate, %g7
84	xor %g7, 0x2, %g7 ! Reset interrupt enable
85	wrpr %g7, %pstate
86
87	! Initialize NCU's Mondo Interrupt Vector Register
88	! VECTOR = 63
89
90	ncu_mondo_int_vec:
91	set 63, %g1
92	setx MONDO_INT_VEC, %g2, %g3
93	stx %g1, [%g3]
94
95	! Clear NCU's Mondo Interrupt Busy registers.
96
97	ncu_mondo_int_busy:
98	setx MONDO_INT_ABUSY, %g1, %g2
99	stx %g0, [%g2]
100
101	! Enable in MMU, TTE_INV_P, primary TTE valid bit not set error.
102
103	mmu_intr_enable_reg_init:
104	setx PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
105	set PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT, %g3
106	set 1, %g4
107	sllx %g4, %g3, %g4
108	stx %g4, [%g2]
109
110	! Enable in IMU, MSI_MAL_ERR_P, malformed MSI message error.
111
112	imu_intr_enable_reg_init:
113	setx PCI_E_IMU_INT_ENB_ADDR, %g1, %g2
114	set PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g3
115	set 1, %g4
116	sllx %g4, %g3, %g4
117	stx %g4, [%g2]
118
119	! Initialize Interrupt Mapping register
120	! Valid, thread ID 0, no interrupt controller
121
122	pci_intr_map_reg_init:
123	setx PCI_E_INT_MAP_ADDR, %g1, %g7
124	setx PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
125	add %g7, %g3, %g7
126	setx 0x80000040, %g1, %g6 ! valid = 1, thread id = 0
127	stx %g6, [%g7] ! interrupt controller = 1
128
129	yes_intr:
130	rdpr %pstate, %g7
131	or %g7, 0x2, %g7 ! Set interrupt enable
132	wrpr %g7, %pstate
133
134	! Enable IMU, MMU interrupts in the DMU Core and Block
135	! Interrupt Enable register.
136
137	dmu_core_block_enable:
138	setx PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
139	setx PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK, %g1, %g3
140	setx PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK, %g1, %g4
141	or %g3, %g4, %g4
142	setx PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK, %g1, %g3
143	or %g3, %g4, %g4
144	stx %g4, [%g2]
145	membar #Sync
146
147	! Generate an interrupt from the IMU block.
148
149	gen_imu_intr:
150	setx PCI_E_IMU_ERR_STAT_SET_ADDR, %g1, %g2
151	set 1, %g6
152	setx PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g1, %g3
153	sllx %g6, %g3, %g6
154	stx %g6, [%g2]
155	membar #Sync
156
157	! Wait for the interrupt trap
158
159	intr_wait1:
160	setx 0x400, %g1, %g2 ! timeout count
161	setx user_data_start, %g1, %g7
162
163	intr_wait_loop1:
164	ld [%g7], %g5
165	cmp %g5, 1
166	be read_esr
167	nop
168
169	cmp %g2, 0
170	be test_failed ! time out
171	nop
172	ba intr_wait_loop1
173	dec %g2
174
175
176	/******************************
177	Error Check
178	******************************/
179	read_esr:
180	setx SOC_ESR_REG, %l7, %i0
181	ldx [%i0], %i1
182	nop
183
184	setx 0x8000000000000000, %l7, %o3 !valid bit
185	set 0x1, %i2
186	sllx %i2, ERR_FIELD, %i3
187	or %i3, %o3, %i4
188	sub %i1, %i4, %i5
189	brnz %i5, test_failed
190	nop
191
192	eie_reg_ones:
193	setx SOC_EIE_REG, %g3, %g2
194	set ERR_FIELD, %g1
195	stx %g1, [%g2]
196	membar 0x40
197
198	setx 0x40, %g7, %g6
199	set 0x1, %g1 ! 1 Trap
200	err_trap_loop:
201	cmp %g6, %g0
202	be %xcc, test_failed
203	nop
204
205	cmp %g1, %i7
206	be %xcc, check_tt
207	nop
208
209	ba err_trap_loop
210	nop
211
212	check_tt:
213	mov 0x40, %l0
214	cmp %o7, %l0
215	bne %xcc, test_failed
216	nop
217
218
219	/********************************/
220
221
222	test_passed:
223	EXIT_GOOD
224
225	test_failed:
226	EXIT_BAD
227
228
229	/**********************************************************************
230	Interrupt trap handler.
231	**********************************************************************/
232
233	.global my_trap_code
234
235	my_trap_code:
236
237	! Record interrupt occured.
238
239	trap_intr_flag:
240	setx user_data_start, %l1, %l3
241	set 1, %l1
242	st %l1, [%l3]
243
244	! Check Mondo Interrupt Busy reg.
245
246	trap_mondo_busy:
247	ta T_RD_THID ! thread id into %o1
248	setx MONDO_INT_BUSY, %l1, %l2
249	setx MONDO_INT_BUSY_STEP, %l1, %l3
250	mulx %l3, %o1, %l3
251	add %l3, %l2, %l2
252	ldx [%l2], %l4
253	and %l4, 0x40, %l5 ! Is busy bit set?
254	cmp %l5, 0
255	be test_failed
256	nop
257
258	! Clear the mondo interrupt in the PIU.
259
260	! MMU Error Status Set reg.
261
262	trap_clear_mmu_err_set:
263	setx PCI_E_MMU_ERR_STAT_SET_ADDR, %l1, %l2
264	stx %g0, [%l2] ! removes setting of the error
265
266	! MMU Error Status Clear reg.
267
268	trap_mmu_err_clear:
269	setx PCI_E_MMU_ERR_STAT_CL_ADDR, %l1, %l2
270	sub %g0, 1, %l0 ! a W1C register
271	stx %l0, [%l2] ! clears the error flag
272
273	! IMU Error Status Set reg.
274
275	trap_clear_imu_err_set:
276	setx PCI_E_IMU_ERR_STAT_SET_ADDR, %l1, %l2
277	stx %g0, [%l2] ! removes setting of the error
278
279	! IMU Error Status Clear reg.
280
281	trap_imu_err_clear:
282	setx PCI_E_IMU_ERR_STAT_CLR_ADDR, %l1, %l2
283	sub %g0, 1, %l0 ! a W1C register
284	stx %l0, [%l2] ! clears the error flag
285
286	! Interrupt Clear reg.
287
288	trap_intr_clear:
289	setx PCI_E_INT_CLEAR_ADDR, %l1, %l2
290	setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
291	add %l2, %l3, %l2
292	stx %g0, [%l2]
293
294	! Clear the mondo interrupt in the NCU
295
296	trap_mondo_intr_clear:
297	setx MONDO_INT_ABUSY, %l0, %l1
298	stx %g0, [%l1]
299	membar #Sync
300
301	ldx [%l1], %l2
302	and %l2, 0x40, %l2
303	cmp %l2, 0 ! Busy should be cleared
304	bne test_failed
305	nop
306
307	! Clear the interrupt in the core.
308
309	trap_clear_asi_intr_r:
310	ldxa [%g0]ASI_SWVR_INTR_R, %l5
311	cmp %l5, 63 ! check for correct vector number
312	bne test_failed
313	nop
314
315	! Done.
316
317	trap_done:
318	jmpl %o7+0x8, %g0
319	nop
320
321
322
323
324	/************************************************************************
325	RAS
326	Trap Handlers
327	************************************************************************/
328	My_Recoverable_Sw_error_trap:
329	! Signal trap taken
330	setx EXECUTED, %l0, %o6
331	! save trap type value
332	rdpr %tt, %o7
333
334	inc %i7
335
336	check_desr_tt40:
337	ldxa [%g0]0x4c, %g2
338	nop
339
340	/*
341	setx 0xb300000000000000, %l0, %g3
342	subcc %g2, %g3, %g4
343	brnz %g4, l2_trap
344	nop
345	*/
346
347	check_DSFSR_tt32:
348	set 0x18, %g1
349	ldxa [%g1]0x58, %g2
350	nop
351	set 0x4, %g3
352	subcc %g2, %g3, %g4
353	brnz %g4, test_failed
354	nop
355
356
357	check_per_tt40:
358	setx SOC_PER_REG, %l7, %g1
359	ldx [%g1], %g2
360	setx 0x8000000000000000, %g7, %g1
361	set 0x1, %g3
362	sllx %g3, ERR_FIELD, %g4
363	or %g1, %g4, %g3
364	sub %g2, %g3, %g5
365	brnz %g5, test_failed
366	nop
367
368	clear_per_tt40:
369	setx SOC_PER_REG, %l7, %g1
370	stx %g0, [%g1]
371	nop
372
373	clear_ejr_tt40:
374	setx SOC_EJR_REG, %l7, %g1
375	stx %g0, [%g1]
376	nop
377
378	clear_eie_tt40:
379	setx SOC_EIE_REG, %l7, %g1
380	stx %g0, [%g1]
381	nop
382
383	trap_done_tt40:
384	done
385	nop
386
387
388	/************************************************************************
389	Test case data start
390	************************************************************************/
391
392	.align 1024
393	.data
394	user_data_start:
395	.word 0x0
396	.word 0x0
397	.word 0x0
398	.word 0x0
399	user_data_end:
400	.end
401