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* OpenSPARC T2 Processor File: n2_err_piu_int_ejr.s
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* ========== Copyright Header End ============================================
#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
#define MAIN_PAGE_HV_ALSO
#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
/************************************************************************
************************************************************************/
.global My_Recoverable_Sw_error_trap
setx SOC_ESR_REG, %l7, %i0
setx SOC_EJR_REG, %l7, %i3
/* Initialize the NCU for the interrupt. */
xor %g7, 0x2, %g7 ! Reset interrupt enable
! Initialize NCU's Mondo Interrupt Vector Register
setx MONDO_INT_VEC, %g2, %g3
! Clear NCU's Mondo Interrupt Busy registers.
setx MONDO_INT_ABUSY, %g1, %g2
! Enable in MMU, TTE_INV_P, primary TTE valid bit not set error.
mmu_intr_enable_reg_init:
setx PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
set PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT, %g3
! Enable in IMU, MSI_MAL_ERR_P, malformed MSI message error.
imu_intr_enable_reg_init:
setx PCI_E_IMU_INT_ENB_ADDR, %g1, %g2
set PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g3
! Initialize Interrupt Mapping register
! Valid, thread ID 0, no interrupt controller
setx PCI_E_INT_MAP_ADDR, %g1, %g7
setx PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
setx 0x80000040, %g1, %g6 ! valid = 1, thread id = 0
stx %g6, [%g7] ! interrupt controller = 1
or %g7, 0x2, %g7 ! Set interrupt enable
! Enable IMU, MMU interrupts in the DMU Core and Block
! Interrupt Enable register.
setx PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
setx PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK, %g1, %g3
setx PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK, %g1, %g4
setx PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK, %g1, %g3
! Generate an interrupt from the IMU block.
setx PCI_E_IMU_ERR_STAT_SET_ADDR, %g1, %g2
setx PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g1, %g3
! Wait for the interrupt trap
setx 0x400, %g1, %g2 ! timeout count
setx user_data_start, %g1, %g7
be test_failed ! time out
/******************************
******************************/
setx SOC_ESR_REG, %l7, %i0
setx 0x8000000000000000, %l7, %o3 !valid bit
setx SOC_EIE_REG, %g3, %g2
/********************************/
/**********************************************************************
**********************************************************************/
! Record interrupt occured.
setx user_data_start, %l1, %l3
! Check Mondo Interrupt Busy reg.
ta T_RD_THID ! thread id into %o1
setx MONDO_INT_BUSY, %l1, %l2
setx MONDO_INT_BUSY_STEP, %l1, %l3
and %l4, 0x40, %l5 ! Is busy bit set?
! Clear the mondo interrupt in the PIU.
! MMU Error Status Set reg.
setx PCI_E_MMU_ERR_STAT_SET_ADDR, %l1, %l2
stx %g0, [%l2] ! removes setting of the error
! MMU Error Status Clear reg.
setx PCI_E_MMU_ERR_STAT_CL_ADDR, %l1, %l2
sub %g0, 1, %l0 ! a W1C register
stx %l0, [%l2] ! clears the error flag
! IMU Error Status Set reg.
setx PCI_E_IMU_ERR_STAT_SET_ADDR, %l1, %l2
stx %g0, [%l2] ! removes setting of the error
! IMU Error Status Clear reg.
setx PCI_E_IMU_ERR_STAT_CLR_ADDR, %l1, %l2
sub %g0, 1, %l0 ! a W1C register
stx %l0, [%l2] ! clears the error flag
setx PCI_E_INT_CLEAR_ADDR, %l1, %l2
setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
! Clear the mondo interrupt in the NCU
setx MONDO_INT_ABUSY, %l0, %l1
cmp %l2, 0 ! Busy should be cleared
! Clear the interrupt in the core.
ldxa [%g0]ASI_SWVR_INTR_R, %l5
cmp %l5, 63 ! check for correct vector number
/************************************************************************
************************************************************************/
My_Recoverable_Sw_error_trap:
setx 0xb300000000000000, %l0, %g3
setx SOC_PER_REG, %l7, %g1
setx 0x8000000000000000, %g7, %g1
setx SOC_PER_REG, %l7, %g1
setx SOC_EJR_REG, %l7, %g1
setx SOC_EIE_REG, %l7, %g1
/************************************************************************
************************************************************************/