[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / interrupt / interrupt_mondo_intr_all_threads.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: interrupt_mondo_intr_all_threads.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define HBOOT_HV_ONLY
#define ENABLE_PCIE_LINK_TRAINING

#define ENABLE_INTR0x60 1

#define INTR0x60_EVENT_QUEUE_BASE event_queue_base
#define INTR0x60_MSI_START_ADDRESS 0x0

!#define INTR0x60_MONDO_IV 63
!#define INTR0x60_MSI_0_NUM 0
!#define INTR0x60_MSI_0_EQN 0
!/* Event Queue 0 == Mondo 24 */
!#define INTR0x60_MONDO_24_V 1
!#define INTR0x60_MONDO_24_THREAD 0
!#define INTR0x60_MONDO_24_CNTRL 0

#define INTR0x60_MONDO_IV 49
#define INTR0x60_MONDO_50_V 1
#define INTR0x60_MONDO_50_MODE 1
#define INTR0x60_MONDO_50_THREAD 0
#define INTR0x60_MONDO_50_CNTRL 2
#define INTR0x60_MSI_0_NUM 243
#define INTR0x60_MSI_0_EQN 26

/* Increment the thread to send the next interrupt to. */
#define INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED \
	best_set_reg(mpeval(PCI_E_INT_MAP_ADDR \
                            +PCI_E_INT_MAP_STEP*(INTR0x60_MSI_0_EQN+4)), \
                 %g7, %g5); \
	setx	0x2000000, %g7, %g4; \
	ldx	[%g5], %g6; \
	addx	%g6, %g4, %g6; \
	stx	%g6, [%g5]; \
	membar	#Sync

/* Get the thread id and calculate the address for this thread in user_data.
 * Has interrupt to this thread already occured?
 * Record the interrupt as done. */
#ifdef PORTABLE_CORE
#define MASK_THREAD_ID and %g1, 0x7, %g1;
#else
#define MASK_THREAD_ID /*nothing*/
#endif /* PORTABLE_CORE */
#define INTR0x60_MSI_EXTRA_HANDLER \
        MASK_THREAD_ID \
        sllx    %g1, 3, %g4; \
        setx    user_data_start, %g7, %g5; \
        add     %g4, %g5, %g4; \
	ldx	[%g4], %g5; \
	brz	%g5, msi_extra_handler_continue; \
	set	1, %g6; \
	EXIT_BAD; \
    msi_extra_handler_continue:\
	stx	%g6, [%g4]


#include "interrupt0x60_defines.h"

#include "hboot.s"
#include "cmp_macros.h"

#include "interrupt0x60_handler.s"

/************************************************************************
   Test case code start
 ************************************************************************/
SECTION .MAIN
.text
.global main

main:
        rdpr    %pstate, %g7
        or      %g7, 0x2, %g7           ! Set interrupt enable
        wrpr    %g7, %pstate

        ta      T_RD_THID
        mov     %o1, %g6                ! %o1, %g6 = thread ID
        set     8, %l7
        umul    %g6, %l7, %l7
        setx    user_data_start, %g1, %g3
        add     %l7, %g3, %g7           ! %g7 = pointer to thread's data area

	stx	%g0, [%g7]		! Clear this thread's interrupt count
	membar	#Sync

        cmp     %g6, 0x0
        be      main_t0                 ! branch if thread 0
        nop
        ba      main_t1_to_t63          ! branch if not thread 0
        nop


!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!
! Thread 0 Start Here
!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

main_t0:
/*      Initialize the NCU for the interrupt.   */

        /* Sync up all the threads. */

sync_t0:
#ifndef PORTABLE_CORE

        SYNC_THREAD_MAIN( local_test_failed, %g1, %g2, %g3 )
#else
        cmp_sync_threads
#endif


        /* Kick off first interrupt, trap handler kicks off rest */

first_mondo_intr:
	! user event to generate MSI msg.
	nop         ! $EV trig_pc_d(1, @VA(.MAIN.first_mondo_intr)) -> EnablePCIeIgCmd ("MSI32", eval(INTR0x60_MSI_0_NUM, 16), 0, 4, 1, *, 1 )

	/* Wait for interrupt to occur. */

intr_wait:
#ifdef DTM_ENABLED
	setx	0x400, %g1, %g2		! DTM timeout count
#else
	setx	0x100, %g1, %g2		! timeout count
#endif

intr_wait_loop_top:
	ldx	[%g7], %g5
	cmp	%g5, 1
	be	t0_next_mondo
	dec	%g2

	cmp	%g2, 0
	bne	intr_wait_loop_top
	nop
	ba	local_test_failed
	nop

	! Kick off next interrupt to next thread.

t0_next_mondo:
	ldx	[%g7], %g0		! Wait for last store
t0_mondo_gen:
	nop         ! $EV trig_pc_d(1, @VA(.MAIN.t0_mondo_gen)) -> EnablePCIeIgCmd ("MSI32", eval(INTR0x60_MSI_0_NUM, 16), 0, 4, 1, *, 1 )

	!Done
t0_done:	
	ba	test_passed
	nop


!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!
! All Threads Except 0 Start Here
!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!


main_t1_to_t63:
#ifndef PORTABLE_CORE

        SYNC_THREAD_OTHER( %g6,%g1,%g2 )
#else
        cmp_sync_threads
#endif

	/* Wait for interrupt to occur. */

t1_t63_intr_wait:
#ifdef DTM_ENABLED
	setx	0x400, %g1, %g2		! DTM timeout count
#else
	setx	0x100, %g1, %g2		! timeout count
#endif
	mulx	%g2, %g6, %g2		! Multiply by thread number

t1_t63_intr_wait_loop_top:
	ldx	[%g7], %g5
	cmp	%g5, 1
	be	t1_t63_next_mondo
	dec	%g2

	cmp	%g2, 0
	bne	t1_t63_intr_wait_loop_top
	nop
	ba	local_test_failed
	nop
	
	! Kick off next interrupt to next thread.

t1_t63_next_mondo:
	ldx	[%g7], %g0		! Wait for last store
t1_t63_mondo_gen:
	nop         ! $EV trig_pc_d(1, @VA(.MAIN.t1_t63_mondo_gen)) -> EnablePCIeIgCmd ("MSI32", eval(INTR0x60_MSI_0_NUM, 16), 0, 4, 1, *, 1 )

	!Done
t1_t63_done:	
	ba	test_passed
	nop

	
test_passed:
	EXIT_GOOD

local_test_failed:
	EXIT_BAD


/************************************************************************
   Test case data start
************************************************************************/

.align  1024
.data
.global user_data_start
user_data_start:
        .word   0xffffffff
        .word   0xffffffff
        .word   0xffffffff
        .word   0xffffffff

.align	eval(512*1024)
.global event_queue_base
event_queue_base:
	.skip	1024
user_data_end:
.end

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: interrupt_mondo_intr_all_threads.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define HBOOT_HV_ONLY
	39	#define ENABLE_PCIE_LINK_TRAINING
	40
	41	#define ENABLE_INTR0x60 1
	42
	43	#define INTR0x60_EVENT_QUEUE_BASE event_queue_base
	44	#define INTR0x60_MSI_START_ADDRESS 0x0
	45
	46	!#define INTR0x60_MONDO_IV 63
	47	!#define INTR0x60_MSI_0_NUM 0
	48	!#define INTR0x60_MSI_0_EQN 0
	49	!/* Event Queue 0 == Mondo 24 */
	50	!#define INTR0x60_MONDO_24_V 1
	51	!#define INTR0x60_MONDO_24_THREAD 0
	52	!#define INTR0x60_MONDO_24_CNTRL 0
	53
	54	#define INTR0x60_MONDO_IV 49
	55	#define INTR0x60_MONDO_50_V 1
	56	#define INTR0x60_MONDO_50_MODE 1
	57	#define INTR0x60_MONDO_50_THREAD 0
	58	#define INTR0x60_MONDO_50_CNTRL 2
	59	#define INTR0x60_MSI_0_NUM 243
	60	#define INTR0x60_MSI_0_EQN 26
	61
	62	/* Increment the thread to send the next interrupt to. */
	63	#define INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED \
	64	best_set_reg(mpeval(PCI_E_INT_MAP_ADDR \
65	+PCI_E_INT_MAP_STEP*(INTR0x60_MSI_0_EQN+4)), \
66	%g7, %g5); \
67	setx 0x2000000, %g7, %g4; \
68	ldx [%g5], %g6; \
69	addx %g6, %g4, %g6; \
70	stx %g6, [%g5]; \
71	membar #Sync
72
73	/* Get the thread id and calculate the address for this thread in user_data.
74	* Has interrupt to this thread already occured?
75	* Record the interrupt as done. */
76	#ifdef PORTABLE_CORE
77	#define MASK_THREAD_ID and %g1, 0x7, %g1;
78	#else
79	#define MASK_THREAD_ID /nothing/
80	#endif /* PORTABLE_CORE */
81	#define INTR0x60_MSI_EXTRA_HANDLER \
82	MASK_THREAD_ID \
83	sllx %g1, 3, %g4; \
84	setx user_data_start, %g7, %g5; \
85	add %g4, %g5, %g4; \
86	ldx [%g4], %g5; \
87	brz %g5, msi_extra_handler_continue; \
88	set 1, %g6; \
89	EXIT_BAD; \
90	msi_extra_handler_continue:\
91	stx %g6, [%g4]
92
93
94	#include "interrupt0x60_defines.h"
95
96	#include "hboot.s"
97	#include "cmp_macros.h"
98
99	#include "interrupt0x60_handler.s"
100
101	/************************************************************************
102	Test case code start
103	************************************************************************/
104	SECTION .MAIN
105	.text
106	.global main
107
108	main:
109	rdpr %pstate, %g7
110	or %g7, 0x2, %g7 ! Set interrupt enable
111	wrpr %g7, %pstate
112
113	ta T_RD_THID
114	mov %o1, %g6 ! %o1, %g6 = thread ID
115	set 8, %l7
116	umul %g6, %l7, %l7
117	setx user_data_start, %g1, %g3
118	add %l7, %g3, %g7 ! %g7 = pointer to thread's data area
119
120	stx %g0, [%g7] ! Clear this thread's interrupt count
121	membar #Sync
122
123	cmp %g6, 0x0
124	be main_t0 ! branch if thread 0
125	nop
126	ba main_t1_to_t63 ! branch if not thread 0
127	nop
128
129
130	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
131	!
132	! Thread 0 Start Here
133	!
134	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
135
136	main_t0:
137	/* Initialize the NCU for the interrupt. */
138
139	/* Sync up all the threads. */
140
141	sync_t0:
142	#ifndef PORTABLE_CORE
143
144	SYNC_THREAD_MAIN( local_test_failed, %g1, %g2, %g3 )
145	#else
146	cmp_sync_threads
147	#endif
148
149
150	/* Kick off first interrupt, trap handler kicks off rest */
151
152	first_mondo_intr:
153	! user event to generate MSI msg.
154	nop ! $EV trig_pc_d(1, @VA(.MAIN.first_mondo_intr)) -> EnablePCIeIgCmd ("MSI32", eval(INTR0x60_MSI_0_NUM, 16), 0, 4, 1, *, 1 )
155
156	/* Wait for interrupt to occur. */
157
158	intr_wait:
159	#ifdef DTM_ENABLED
160	setx 0x400, %g1, %g2 ! DTM timeout count
161	#else
162	setx 0x100, %g1, %g2 ! timeout count
163	#endif
164
165	intr_wait_loop_top:
166	ldx [%g7], %g5
167	cmp %g5, 1
168	be t0_next_mondo
169	dec %g2
170
171	cmp %g2, 0
172	bne intr_wait_loop_top
173	nop
174	ba local_test_failed
175	nop
176
177	! Kick off next interrupt to next thread.
178
179	t0_next_mondo:
180	ldx [%g7], %g0 ! Wait for last store
181	t0_mondo_gen:
182	nop ! $EV trig_pc_d(1, @VA(.MAIN.t0_mondo_gen)) -> EnablePCIeIgCmd ("MSI32", eval(INTR0x60_MSI_0_NUM, 16), 0, 4, 1, *, 1 )
183
184	!Done
185	t0_done:
186	ba test_passed
187	nop
188
189
190	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
191	!
192	! All Threads Except 0 Start Here
193	!
194	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
195
196
197	main_t1_to_t63:
198	#ifndef PORTABLE_CORE
199
200	SYNC_THREAD_OTHER( %g6,%g1,%g2 )
201	#else
202	cmp_sync_threads
203	#endif
204
205	/* Wait for interrupt to occur. */
206
207	t1_t63_intr_wait:
208	#ifdef DTM_ENABLED
209	setx 0x400, %g1, %g2 ! DTM timeout count
210	#else
211	setx 0x100, %g1, %g2 ! timeout count
212	#endif
213	mulx %g2, %g6, %g2 ! Multiply by thread number
214
215	t1_t63_intr_wait_loop_top:
216	ldx [%g7], %g5
217	cmp %g5, 1
218	be t1_t63_next_mondo
219	dec %g2
220
221	cmp %g2, 0
222	bne t1_t63_intr_wait_loop_top
223	nop
224	ba local_test_failed
225	nop
226
227	! Kick off next interrupt to next thread.
228
229	t1_t63_next_mondo:
230	ldx [%g7], %g0 ! Wait for last store
231	t1_t63_mondo_gen:
232	nop ! $EV trig_pc_d(1, @VA(.MAIN.t1_t63_mondo_gen)) -> EnablePCIeIgCmd ("MSI32", eval(INTR0x60_MSI_0_NUM, 16), 0, 4, 1, *, 1 )
233
234	!Done
235	t1_t63_done:
236	ba test_passed
237	nop
238
239
240	test_passed:
241	EXIT_GOOD
242
243	local_test_failed:
244	EXIT_BAD
245
246
247
248
249	/************************************************************************
250	Test case data start
251	************************************************************************/
252
253	.align 1024
254	.data
255	.global user_data_start
256	user_data_start:
257	.word 0xffffffff
258	.word 0xffffffff
259	.word 0xffffffff
260	.word 0xffffffff
261
262	.align eval(512*1024)
263	.global event_queue_base
264	event_queue_base:
265	.skip 1024
266	user_data_end:
267	.end
268
269	/************************************************************************/