Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / include / dmaept_init.h
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: dmaept_init.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
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14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
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21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
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32* CA 95054 USA or visit www.sun.com if you need additional information or
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36* ========== Copyright Header End ============================================
37*/
38#include "peu_defines.h"
39#include "dmaept_defines.h"
40
41 b PEU_DMAEPT_END
42 nop
43
44DMAEptInit:
45 save
46
47 ! Setup an ASI for little-endian access to PCI space
48 ! ************ %l4 saves %asi so it can be restored later
49 ! ************ Don't use %l4.
50 rd %asi, %l4
51 wr %g0, ASI_NL, %asi
52
53 ! Setup the Command Register
54 setx CFG0_CMDSTS_ADDR, %l1, %l2
55 lduwa [%l2] %asi, %l1 ! Read it first
56 ! Enable:
57 ! 8: SERR
58 ! 6: Parity Error
59 ! 2: Bus Mastering
60 ! 1: Memory Space
61 or %l1, 0x00000146, %l1
62 stwa %l1, [%l2] %asi
63
64 ! Find out which bits of BAR0 are writable.
65 setx CFG0_BAR0_ADDR, %l1, %l2 ! BAR0
66 setx 0xffffffff, %l1, %l3
67 stwa %l3, [%l2] %asi
68 lduwa [%l2] %asi, %l3
69
70 ! Now set BAR0 to the low 32 bits of PART_0_BASE
71 ! plus PCIE_MEM64_OFFSET
72 setx DMAEPT_BAR0, %l1, %l3
73 setx PCIE_MEM64_OFFSET, %l1, %l0
74 add %l0, %l3, %l0
75 stwa %l0, [%l2] %asi
76 ! Just want one last look.
77 lduwa [%l2] %asi, %l1
78
79 ! Setup BAR1 with upper 32 bits of base & offset
80 srlx %l0, 0x20, %l1
81 stwa %l1, [%l2+0x04] %asi ! BAR1
82
83 ! Setup BAR2 as a Mem 32 BAR
84 setx DMAEPT_MEM_SIZE, %l1, %l0
85 add %l0, %l3, %l1
86 stwa %l1, [%l2+0x08] %asi ! BAR2
87
88 ! Setup BAR3 as an IO BAR
89 clr %l1
90 stwa %l1, [%l2+0x0c] %asi ! BAR3
91
92 ! Restore %asi to what it had when we started.
93 wr %l4, %g0, %asi
94
95DMAEpt_Init_Done:
96 ret
97 restore
98
99PEU_DMAEPT_END:
100 nop
101
102