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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: spc_por_rdchk.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #ifndef __HBOOT_S__ | |
39 | ||
40 | #include "asi_s.h" | |
41 | ||
42 | SECTION .RED_SEC TEXT_VA = 0xfffffffff0000000 | |
43 | ||
44 | attr_text { | |
45 | Name=.RED_SEC, | |
46 | hypervisor | |
47 | } | |
48 | ||
49 | .text | |
50 | nop | |
51 | nop | |
52 | nop | |
53 | nop | |
54 | nop | |
55 | nop | |
56 | nop | |
57 | nop | |
58 | POR: | |
59 | jmp %g0+0x100 | |
60 | nop | |
61 | ||
62 | SECTION .POR_SEC TEXT_VA = 0x0 | |
63 | ||
64 | attr_text { | |
65 | Name=.POR_SEC, | |
66 | hypervisor | |
67 | } | |
68 | ||
69 | .text | |
70 | nop | |
71 | .align 0x100 | |
72 | #endif | |
73 | ||
74 | #ifndef ASI_CHECK_GOODTRAP | |
75 | por_asr: | |
76 | rdpr %pstate, %g1 | |
77 | rdhpr %hpstate, %g1 | |
78 | rdpr %tba, %g1 | |
79 | rdhpr %htba, %g1 | |
80 | rd %y, %g1 | |
81 | rdpr %pil, %g1 | |
82 | rdpr %cwp, %g1 | |
83 | rdpr %tt, %g1 | |
84 | rd %ccr, %g1 | |
85 | rd %asi, %g1 | |
86 | rdpr %tl, %g1 | |
87 | rdpr %cansave, %g1 | |
88 | rdpr %canrestore, %g1 | |
89 | rdpr %otherwin, %g1 | |
90 | rdpr %cleanwin, %g1 | |
91 | rdpr %wstate, %g1 | |
92 | rdhpr %ver, %g1 | |
93 | stx %fsr, [%g0] | |
94 | rd %fprs, %g1 | |
95 | rd %gsr, %g1 | |
96 | rd %pcr, %g1 | |
97 | rd %pic, %g1 | |
98 | rd %tick_cmpr, %g1 | |
99 | rd %asr25, %g1 | |
100 | rdhpr %hsys_tick_cmpr, %g1 | |
101 | rdhpr %hintp, %g1 | |
102 | rd %softint, %g1 | |
103 | ||
104 | por_tstack: | |
105 | ! Trap Stack | |
106 | por_irf: | |
107 | ! IRF | |
108 | por_frf: | |
109 | ! FRF | |
110 | por_stb: | |
111 | ! STBuffer | |
112 | ||
113 | #else | |
114 | !Clear error-inject | |
115 | ldxa [%g0]ASI_ERROR_INJECT, %g1 | |
116 | stxa %g0, [%g0]ASI_ERROR_INJECT | |
117 | #endif | |
118 | ||
119 | por_asi: | |
120 | ! ASIs | |
121 | ! ASI_SCRATCHPAD_0_REG | |
122 | ldxa [%g0]ASI_SCRATCHPAD, %g1 | |
123 | ! ASI_SCRATCHPAD_1_REG | |
124 | mov 0x8, %g1 | |
125 | ldxa [%g1]ASI_SCRATCHPAD, %g1 | |
126 | ! ASI_SCRATCHPAD_2_REG | |
127 | mov 0x10, %g1 | |
128 | ldxa [%g1]ASI_SCRATCHPAD, %g1 | |
129 | ! ASI_SCRATCHPAD_3_REG | |
130 | mov 0x18, %g1 | |
131 | ldxa [%g1]ASI_SCRATCHPAD, %g1 | |
132 | ! ASI_SCRATCHPAD_4_REG | |
133 | !mov 0x20, %g1 | |
134 | !ldxa [%g1]ASI_SCRATCHPAD, %g1 | |
135 | ! ASI_SCRATCHPAD_5_REG | |
136 | !mov 0x28, %g1 | |
137 | !ldxa [%g1]ASI_SCRATCHPAD, %g1 | |
138 | ! ASI_SCRATCHPAD_6_REG | |
139 | mov 0x30, %g1 | |
140 | ldxa [%g1]ASI_SCRATCHPAD, %g1 | |
141 | ! ASI_SCRATCHPAD_7_REG | |
142 | mov 0x38, %g1 | |
143 | ldxa [%g1]ASI_SCRATCHPAD, %g1 | |
144 | ! ASI_PRIMARY_CONTEXT_0 | |
145 | mov 0x8, %g1 | |
146 | ldxa [%g1]ASI_PRIMARY_CONTEXT_REG, %g1 | |
147 | ! ASI_PRIMARY_CONTEXT_1 | |
148 | mov 0x108, %g1 | |
149 | ldxa [%g1]ASI_PRIMARY_CONTEXT_REG, %g1 | |
150 | ! ASI_SECONDARY_CONTEXT_0 | |
151 | mov 0x010, %g1 | |
152 | ldxa [%g1]ASI_PRIMARY_CONTEXT_REG, %g1 | |
153 | ! ASI_SECONDARY_CONTEXT_1 | |
154 | mov 0x110, %g1 | |
155 | ldxa [%g1]ASI_PRIMARY_CONTEXT_REG, %g1 | |
156 | ! ASI_CPU_MONDO_QUEUE_HEAD | |
157 | mov 0x3c0, %g1 | |
158 | ldxa [%g1]ASI_QUEUE, %g1 | |
159 | ! ASI_CPU_MONDO_QUEUE_TAIL | |
160 | mov 0x3c8, %g1 | |
161 | ldxa [%g1]ASI_QUEUE, %g1 | |
162 | ! ASI_DEVICE_QUEUE_HEAD | |
163 | mov 0x3d0, %g1 | |
164 | ldxa [%g1]ASI_QUEUE, %g1 | |
165 | ! ASI_DEVICE_QUEUE_TAIL | |
166 | mov 0x3d8, %g1 | |
167 | ldxa [%g1]ASI_QUEUE, %g1 | |
168 | ! ASI_RES_ERROR_QUEUE_HEAD | |
169 | mov 0x3e0, %g1 | |
170 | ldxa [%g1]ASI_QUEUE, %g1 | |
171 | ! ASI_RES_ERROR_QUEUE_TAIL | |
172 | mov 0x3e8, %g1 | |
173 | ldxa [%g1]ASI_QUEUE, %g1 | |
174 | ! ASI_CWQ_HEAD | |
175 | ldxa [%g0]ASI_SPU, %g1 | |
176 | ! ASI_CWQ_TAIL | |
177 | mov 0x8, %g1 | |
178 | ldxa [%g1]ASI_SPU, %g1 | |
179 | ! ASI_CWQ_FIRST | |
180 | mov 0x10, %g1 | |
181 | ldxa [%g1]ASI_SPU, %g1 | |
182 | ! ASI_CWQ_LAST | |
183 | mov 0x18, %g1 | |
184 | ldxa [%g1]ASI_SPU, %g1 | |
185 | ! ASI_CWQ_CSR | |
186 | mov 0x20, %g1 | |
187 | ldxa [%g1]ASI_SPU, %g1 | |
188 | ! ASI_CWQ_SYNC | |
189 | mov 0x30, %g1 | |
190 | ldxa [%g1]ASI_SPU, %g1 | |
191 | ! ASI_SPU_MA_CTL | |
192 | mov 0x80, %g1 | |
193 | ldxa [%g1]ASI_SPU, %g1 | |
194 | ! ASI_SPU_MA_PA | |
195 | mov 0x88, %g1 | |
196 | ldxa [%g1]ASI_SPU, %g1 | |
197 | ! ASI_SPU_MA_ADDR | |
198 | mov 0x90, %g1 | |
199 | ldxa [%g1]ASI_SPU, %g1 | |
200 | ! ASI_SPU_MA_NP | |
201 | mov 0x98, %g1 | |
202 | ldxa [%g1]ASI_SPU, %g1 | |
203 | ! ASI_SPU_MA_SYNC | |
204 | mov 0xa0, %g1 | |
205 | ldxa [%g1]ASI_SPU, %g1 | |
206 | ! ASI_INST_MASK_REG | |
207 | mov 0x8, %g1 | |
208 | ldxa [%g1]ASI_DIAG, %g1 | |
209 | ! ASI_LSU_DIAG_REG | |
210 | mov 0x10, %g1 | |
211 | ldxa [%g1]ASI_DIAG, %g1 | |
212 | ! ASI_ERROR_INJECT_REG | |
213 | ldxa [%g0]ASI_ERROR_INJECT, %g1 | |
214 | ! ASI_LSU_CONTROL_REG | |
215 | ldxa [%g0]ASI_LSU_CONTROL, %g1 | |
216 | ! ASI_DECR | |
217 | mov 0x8, %g1 | |
218 | ldxa [%g1]ASI_LSU_CONTROL, %g1 | |
219 | ||
220 | ! ASI_OVERLAP_MODE - access not implemented. See bug 103105 | |
221 | !mov 0x10, %g1 | |
222 | !ldxa [%g1]ASI_LSU_CONTROL, %g1 | |
223 | ! ASI_WMR_VEC_MASK | |
224 | !mov 0x18, %g1 | |
225 | !ldxa [%g1]ASI_LSU_CONTROL, %g1 | |
226 | ||
227 | ! ASI_DESR | |
228 | ldxa [%g0]ASI_DESR, %g1 | |
229 | ! ASI_DFESR | |
230 | mov 0x8, %g1 | |
231 | ldxa [%g1]ASI_DFESR, %g1 | |
232 | ! ASI_CERER | |
233 | mov 0x10, %g1 | |
234 | ldxa [%g1]ASI_CERER, %g1 | |
235 | ! ASI_CETER | |
236 | mov 0x18, %g1 | |
237 | ldxa [%g1]ASI_CETER, %g1 | |
238 | ! ASI_CLESR | |
239 | mov 0x20, %g1 | |
240 | ldxa [%g1]0x4c, %g1 | |
241 | ! ASI_CLFESR | |
242 | mov 0x28, %g1 | |
243 | ldxa [%g1]0x4c, %g1 | |
244 | ! ASI_SPARC_PWR_MGMT | |
245 | ldxa [%g0]ASI_SPARC_PWR_MGMT, %g1 | |
246 | ! ASI_HYP_SCRATCHPAD_0_REG | |
247 | ldxa [%g0]ASI_HYP_SCRATCHPAD, %g1 | |
248 | ! ASI_HYP_SCRATCHPAD_1_REG | |
249 | mov 0x8, %g1 | |
250 | ldxa [%g1]ASI_HYP_SCRATCHPAD, %g1 | |
251 | ! ASI_HYP_SCRATCHPAD_2_REG | |
252 | mov 0x10, %g1 | |
253 | ldxa [%g1]ASI_HYP_SCRATCHPAD, %g1 | |
254 | ! ASI_HYP_SCRATCHPAD_3_REG | |
255 | mov 0x18, %g1 | |
256 | ldxa [%g1]ASI_HYP_SCRATCHPAD, %g1 | |
257 | ! ASI_HYP_SCRATCHPAD_4_REG | |
258 | mov 0x20, %g1 | |
259 | ldxa [%g1]ASI_HYP_SCRATCHPAD, %g1 | |
260 | ! ASI_HYP_SCRATCHPAD_5_REG | |
261 | mov 0x28, %g1 | |
262 | ldxa [%g1]ASI_HYP_SCRATCHPAD, %g1 | |
263 | ! ASI_HYP_SCRATCHPAD_6_REG | |
264 | mov 0x30, %g1 | |
265 | ldxa [%g1]ASI_HYP_SCRATCHPAD, %g1 | |
266 | ! ASI_HYP_SCRATCHPAD_7_REG | |
267 | mov 0x38, %g1 | |
268 | ldxa [%g1]ASI_HYP_SCRATCHPAD, %g1 | |
269 | ! ASI_IMMU_TAG_TARGET | |
270 | ldxa [%g0]ASI_IMMU_TAG_REG, %g1 | |
271 | ! ASI_IMMU_SFSR | |
272 | mov 0x18, %g1 | |
273 | ldxa [%g1]ASI_IMMU_TAG_REG, %g1 | |
274 | ! ASI_IMMU_TAG_ACCESS | |
275 | mov 0x30, %g1 | |
276 | ldxa [%g1]ASI_IMMU_TAG_REG, %g1 | |
277 | ! ASI_IMMU_VA_WATCHPOINT | |
278 | mov 0x38, %g1 | |
279 | ldxa [%g1]ASI_IMMU_TAG_REG, %g1 | |
280 | ! ASI_MMU_REAL_RANGE_0 | |
281 | mov 0x108, %g1 | |
282 | ldxa [%g1]ASI_MMU_REAL_RANGE, %g1 | |
283 | ! ASI_MMU_REAL_RANGE_1 | |
284 | mov 0x110, %g1 | |
285 | ldxa [%g1]ASI_MMU_REAL_RANGE, %g1 | |
286 | ! ASI_MMU_REAL_RANGE_2 | |
287 | mov 0x118, %g1 | |
288 | ldxa [%g1]ASI_MMU_REAL_RANGE, %g1 | |
289 | ! ASI_MMU_REAL_RANGE_3 | |
290 | mov 0x120, %g1 | |
291 | ldxa [%g1]ASI_MMU_REAL_RANGE, %g1 | |
292 | ! ASI_MMU_PHYSICAL_OFFSET_0 | |
293 | mov 0x208, %g1 | |
294 | ldxa [%g1]ASI_MMU_PHYSICAL_OFFSET, %g1 | |
295 | ! ASI_MMU_PHYSICAL_OFFSET_1 | |
296 | mov 0x210, %g1 | |
297 | ldxa [%g1]ASI_MMU_PHYSICAL_OFFSET, %g1 | |
298 | ! ASI_MMU_PHYSICAL_OFFSET_2 | |
299 | mov 0x218, %g1 | |
300 | ldxa [%g1]ASI_MMU_PHYSICAL_OFFSET, %g1 | |
301 | ! ASI_MMU_PHYSICAL_OFFSET_3 | |
302 | mov 0x220, %g1 | |
303 | ldxa [%g1]ASI_MMU_PHYSICAL_OFFSET, %g1 | |
304 | ! ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0 | |
305 | mov 0x10, %g1 | |
306 | ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1 | |
307 | ! ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1 | |
308 | mov 0x18, %g1 | |
309 | ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1 | |
310 | ! ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2 | |
311 | mov 0x20, %g1 | |
312 | ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1 | |
313 | ! ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3 | |
314 | mov 0x28, %g1 | |
315 | ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1 | |
316 | ! ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0 | |
317 | mov 0x30, %g1 | |
318 | ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1 | |
319 | ! ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1 | |
320 | mov 0x38, %g1 | |
321 | ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1 | |
322 | ! ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2 | |
323 | mov 0x40, %g1 | |
324 | ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1 | |
325 | ! ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3 | |
326 | mov 0x48, %g1 | |
327 | ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1 | |
328 | ! ASI_ITSB_PTR_0 | |
329 | mov 0x50, %g1 | |
330 | ldxa [%g1]ASI_ITSB_PTR, %g1 | |
331 | ! ASI_ITSB_PTR_1 | |
332 | mov 0x58, %g1 | |
333 | ldxa [%g1]ASI_ITSB_PTR, %g1 | |
334 | ! ASI_ITSB_PTR_2 | |
335 | mov 0x60, %g1 | |
336 | ldxa [%g1]ASI_ITSB_PTR, %g1 | |
337 | ! ASI_ITSB_PTR_3 | |
338 | mov 0x68, %g1 | |
339 | ldxa [%g1]ASI_ITSB_PTR, %g1 | |
340 | ! ASI_DTSB_PTR_0 | |
341 | mov 0x70, %g1 | |
342 | ldxa [%g1]ASI_DTSB_PTR, %g1 | |
343 | ! ASI_DTSB_PTR_1 | |
344 | mov 0x78, %g1 | |
345 | ldxa [%g1]ASI_DTSB_PTR, %g1 | |
346 | ! ASI_DTSB_PTR_2 | |
347 | mov 0x80, %g1 | |
348 | ldxa [%g1]ASI_DTSB_PTR, %g1 | |
349 | ! ASI_DTSB_PTR_3 | |
350 | mov 0x88, %g1 | |
351 | ldxa [%g1]ASI_DTSB_PTR, %g1 | |
352 | ! ASI_DMMU_SFSR | |
353 | mov 0x18, %g1 | |
354 | ldxa [%g1]ASI_DMMU, %g1 | |
355 | ! ASI_DMMU_SFAR | |
356 | mov 0x20, %g1 | |
357 | ldxa [%g1]ASI_DMMU, %g1 | |
358 | ! ASI_DTLB_TAG_ACCESS | |
359 | mov 0x30, %g1 | |
360 | ldxa [%g1]ASI_DMMU, %g1 | |
361 | ! ASI_DMMU_WATCHPOINT | |
362 | mov 0x38, %g1 | |
363 | ldxa [%g1]ASI_DMMU, %g1 | |
364 | ! ASI_HWTW_CONFIG | |
365 | mov 0x40, %g1 | |
366 | ldxa [%g1]ASI_DMMU, %g1 | |
367 | ! ASI_PARTITION_ID | |
368 | mov 0x80, %g1 | |
369 | ldxa [%g1]ASI_DMMU, %g1 | |
370 | ! ASI_INTR_RECEIVE | |
371 | ldxa [%g0]ASI_INTR_RECEIVE, %g1 | |
372 | ||
373 | finished_por_rdchk: | |
374 | nop | |
375 | nop | |
376 | #ifndef __HBOOT_S__ | |
377 | good_trap: | |
378 | ba good_trap | |
379 | nop | |
380 | #endif |