* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: spc_por_rdchk.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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* choice is available it will apply instead, Sun elects to use only
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* ========== Copyright Header End ============================================
SECTION .RED_SEC TEXT_VA = 0xfffffffff0000000
SECTION .POR_SEC TEXT_VA = 0x0
#ifndef ASI_CHECK_GOODTRAP
rdhpr %hsys_tick_cmpr, %g1
ldxa [%g0]ASI_ERROR_INJECT, %g1
stxa %g0, [%g0]ASI_ERROR_INJECT
ldxa [%g0]ASI_SCRATCHPAD, %g1
ldxa [%g1]ASI_SCRATCHPAD, %g1
ldxa [%g1]ASI_SCRATCHPAD, %g1
ldxa [%g1]ASI_SCRATCHPAD, %g1
!ldxa [%g1]ASI_SCRATCHPAD, %g1
!ldxa [%g1]ASI_SCRATCHPAD, %g1
ldxa [%g1]ASI_SCRATCHPAD, %g1
ldxa [%g1]ASI_SCRATCHPAD, %g1
ldxa [%g1]ASI_PRIMARY_CONTEXT_REG, %g1
ldxa [%g1]ASI_PRIMARY_CONTEXT_REG, %g1
! ASI_SECONDARY_CONTEXT_0
ldxa [%g1]ASI_PRIMARY_CONTEXT_REG, %g1
! ASI_SECONDARY_CONTEXT_1
ldxa [%g1]ASI_PRIMARY_CONTEXT_REG, %g1
! ASI_CPU_MONDO_QUEUE_HEAD
! ASI_CPU_MONDO_QUEUE_TAIL
! ASI_RES_ERROR_QUEUE_HEAD
! ASI_RES_ERROR_QUEUE_TAIL
ldxa [%g0]ASI_ERROR_INJECT, %g1
ldxa [%g0]ASI_LSU_CONTROL, %g1
ldxa [%g1]ASI_LSU_CONTROL, %g1
! ASI_OVERLAP_MODE - access not implemented. See bug 103105
!ldxa [%g1]ASI_LSU_CONTROL, %g1
!ldxa [%g1]ASI_LSU_CONTROL, %g1
ldxa [%g0]ASI_SPARC_PWR_MGMT, %g1
! ASI_HYP_SCRATCHPAD_0_REG
ldxa [%g0]ASI_HYP_SCRATCHPAD, %g1
! ASI_HYP_SCRATCHPAD_1_REG
ldxa [%g1]ASI_HYP_SCRATCHPAD, %g1
! ASI_HYP_SCRATCHPAD_2_REG
ldxa [%g1]ASI_HYP_SCRATCHPAD, %g1
! ASI_HYP_SCRATCHPAD_3_REG
ldxa [%g1]ASI_HYP_SCRATCHPAD, %g1
! ASI_HYP_SCRATCHPAD_4_REG
ldxa [%g1]ASI_HYP_SCRATCHPAD, %g1
! ASI_HYP_SCRATCHPAD_5_REG
ldxa [%g1]ASI_HYP_SCRATCHPAD, %g1
! ASI_HYP_SCRATCHPAD_6_REG
ldxa [%g1]ASI_HYP_SCRATCHPAD, %g1
! ASI_HYP_SCRATCHPAD_7_REG
ldxa [%g1]ASI_HYP_SCRATCHPAD, %g1
ldxa [%g0]ASI_IMMU_TAG_REG, %g1
ldxa [%g1]ASI_IMMU_TAG_REG, %g1
ldxa [%g1]ASI_IMMU_TAG_REG, %g1
ldxa [%g1]ASI_IMMU_TAG_REG, %g1
ldxa [%g1]ASI_MMU_REAL_RANGE, %g1
ldxa [%g1]ASI_MMU_REAL_RANGE, %g1
ldxa [%g1]ASI_MMU_REAL_RANGE, %g1
ldxa [%g1]ASI_MMU_REAL_RANGE, %g1
! ASI_MMU_PHYSICAL_OFFSET_0
ldxa [%g1]ASI_MMU_PHYSICAL_OFFSET, %g1
! ASI_MMU_PHYSICAL_OFFSET_1
ldxa [%g1]ASI_MMU_PHYSICAL_OFFSET, %g1
! ASI_MMU_PHYSICAL_OFFSET_2
ldxa [%g1]ASI_MMU_PHYSICAL_OFFSET, %g1
! ASI_MMU_PHYSICAL_OFFSET_3
ldxa [%g1]ASI_MMU_PHYSICAL_OFFSET, %g1
! ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0
ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1
! ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1
ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1
! ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2
ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1
! ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3
ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1
! ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0
ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1
! ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1
ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1
! ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2
ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1
! ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3
ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1
ldxa [%g1]ASI_ITSB_PTR, %g1
ldxa [%g1]ASI_ITSB_PTR, %g1
ldxa [%g1]ASI_ITSB_PTR, %g1
ldxa [%g1]ASI_ITSB_PTR, %g1
ldxa [%g1]ASI_DTSB_PTR, %g1
ldxa [%g1]ASI_DTSB_PTR, %g1
ldxa [%g1]ASI_DTSB_PTR, %g1
ldxa [%g1]ASI_DTSB_PTR, %g1
ldxa [%g0]ASI_INTR_RECEIVE, %g1