projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: itlb_wr.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | `ifdef CORE_0 | |
| 36 | ||
| 37 | module itlb_wr_c0 (); | |
| 38 | `ifndef GATESIM | |
| 39 | ||
| 40 | `include "tlb_sync.vh" | |
| 41 | `include "nas.vh" | |
| 42 | parameter NUM_TLB=64; | |
| 43 | ||
| 44 | wire [7:0] data_in; | |
| 45 | wire [7:0] tlb_wr; | |
| 46 | wire wr_en; | |
| 47 | wire [7:0] entry; | |
| 48 | wire [3:0] demap; | |
| 49 | reg [3:0] demap_1; | |
| 50 | wire demap_page; | |
| 51 | wire demap_context; | |
| 52 | wire demap_real; | |
| 53 | wire demap_all; | |
| 54 | wire skip_demap; | |
| 55 | wire demap_active; | |
| 56 | wire auto_demap; | |
| 57 | wire [2:0] demap_tid; | |
| 58 | reg [2:0] demap_tid_1; | |
| 59 | reg [5:0] demap_tnum_1; | |
| 60 | wire [7:0] asi_wr_itlb; | |
| 61 | wire [7:0] asi_wr_itlb_demap; | |
| 62 | wire [7:0] asi_wr_itlb_data_in; | |
| 63 | wire [7:0] asi_wr_itlb_data_access; | |
| 64 | ||
| 65 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 66 | reg [7:0] data_in_ready; | |
| 67 | reg hwtw; | |
| 68 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 69 | ||
| 70 | reg [2:0] mytid; | |
| 71 | reg [5:0] mytnum; | |
| 72 | wire [2:0] mycid; | |
| 73 | integer junk; | |
| 74 | integer i; | |
| 75 | reg [7:0] cnt; | |
| 76 | wire ready; | |
| 77 | ||
| 78 | assign mycid = 0; | |
| 79 | ||
| 80 | //---------------------------------------------------------- | |
| 81 | // Instantiate fifo - 1 entry per thread | |
| 82 | fifo fifo (); | |
| 83 | // Define fifo parameters | |
| 84 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 85 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 86 | defparam fifo.PTR_BITS = 4; | |
| 87 | ||
| 88 | //---------------------------------------------------------- | |
| 89 | // DUT probes | |
| 90 | ||
| 91 | assign data_in = `SPC0.mmu.asi.htc_wr_itlb_data_in; | |
| 92 | assign tlb_wr = `PROBES0.itlb_wr; | |
| 93 | assign wr_en = `SPC0.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; | |
| 94 | ||
| 95 | assign entry = `SPC0.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; | |
| 96 | ||
| 97 | assign demap_page = `SPC0.ifu_ftu.ftu_itc_ctl.itc_demap_page; | |
| 98 | assign demap_context = `SPC0.ifu_ftu.itc_demap_context; | |
| 99 | assign demap_real = `SPC0.ifu_ftu.itc_demap_real; | |
| 100 | assign demap_all = `SPC0.ifu_ftu.itc_demap_all; | |
| 101 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 102 | assign skip_demap = `SPC0.ifu_ftu.itc_wr_u_en; | |
| 103 | assign demap_tid = `SPC0.ifu_ftu.ftu_itd_dp.tte1[37:35]; | |
| 104 | ||
| 105 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 106 | assign demap_active = |demap_1 && !skip_demap; | |
| 107 | assign auto_demap = |demap_1 && skip_demap; | |
| 108 | ||
| 109 | ||
| 110 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. | |
| 111 | // Once these signals assert, the write to the TLB cannot be cancelled. | |
| 112 | // These signals assert before the MMU reorders the TLB writes. | |
| 113 | // Use these to suppress SSTEP in nas_pipe. | |
| 114 | // Best case, these signals assert 1 cycle after the previous SSTEP. | |
| 115 | assign asi_wr_itlb_demap = `SPC0.mmu.asi_wr_immu_demap; | |
| 116 | assign asi_wr_itlb_data_in = `SPC0.mmu.asi_wr_itlb_data_in; | |
| 117 | assign asi_wr_itlb_data_access = {`SPC0.mmu.asd1.asi_wr_itlb_data_access, | |
| 118 | `SPC0.mmu.asd0.asi_wr_itlb_data_access}; | |
| 119 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; | |
| 120 | ||
| 121 | //--------------------- | |
| 122 | // Probes for debugging | |
| 123 | ||
| 124 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl | |
| 125 | ||
| 126 | // n2_tlb_tl_64x59_cam.sv | |
| 127 | ||
| 128 | `define CNTX1_HI 65 | |
| 129 | `define CNTX1_LO 53 | |
| 130 | `define PID_HI 52 | |
| 131 | `define PID_LO 50 | |
| 132 | `define REAL_BIT 49 | |
| 133 | `define VA_47 48 | |
| 134 | `define VA_28 29 | |
| 135 | `define VA_27 28 | |
| 136 | `define VA_22 23 | |
| 137 | `define TTE_VALID 22 | |
| 138 | `define VA_21 21 | |
| 139 | `define VA_16 16 | |
| 140 | `define VA_15 15 | |
| 141 | `define VA_13 13 | |
| 142 | `define CNTX0_HI 12 | |
| 143 | `define CNTX0_LO 0 | |
| 144 | ||
| 145 | // n2_tlb_tl_64x59_ram.sv | |
| 146 | ||
| 147 | `define DATA_PARITY 36 | |
| 148 | `define DATA_PA_39_28_HI 35 | |
| 149 | `define DATA_PA_39_28_LO 24 | |
| 150 | `define DATA_PA_27_22_HI 23 | |
| 151 | `define DATA_PA_27_22_LO 18 | |
| 152 | `define DATA_VA_27_22_V 17 | |
| 153 | `define DATA_PA_21_16_HI 16 | |
| 154 | `define DATA_PA_21_16_LO 11 | |
| 155 | `define DATA_VA_21_16_V 10 | |
| 156 | `define DATA_PA_15_13_HI 9 | |
| 157 | `define DATA_PA_15_13_LO 7 | |
| 158 | `define DATA_VA_15_13_V 6 | |
| 159 | `define DATA_NFO 5 | |
| 160 | `define DATA_IE 4 | |
| 161 | `define DATA_CP 3 | |
| 162 | `define DATA_X 2 | |
| 163 | `define DATA_P 1 | |
| 164 | `define DATA_W 0 | |
| 165 | ||
| 166 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 167 | wire [(NUM_TLB-1):0] tlb_match; | |
| 168 | wire tte_valid; | |
| 169 | wire [47:0] tte_va; | |
| 170 | wire [12:0] tte_context; | |
| 171 | wire tte_real; | |
| 172 | wire [2:0] tte_pid; | |
| 173 | wire [2:0] tte_page_mask; | |
| 174 | wire [39:0] tte_pa; | |
| 175 | wire tte_nfo; | |
| 176 | wire tte_ie; | |
| 177 | wire tte_cp; | |
| 178 | wire tte_e; | |
| 179 | wire tte_p; | |
| 180 | wire tte_w; | |
| 181 | wire tte_ep; | |
| 182 | ||
| 183 | assign tlb_valid = `SPC0.ifu_ftu.ftu_itb_cust.array.cam.valid; | |
| 184 | assign tlb_match = `SPC0.ifu_ftu.ftu_itb_cust.array.cam.match; | |
| 185 | ||
| 186 | assign tte_va = {`SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], | |
| 187 | `SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], | |
| 188 | `SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], | |
| 189 | `SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], | |
| 190 | 13'b0 | |
| 191 | }; | |
| 192 | assign tte_context = `SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 193 | assign tte_pid = `SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 194 | assign tte_real = `SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; | |
| 195 | assign tte_valid = `SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; | |
| 196 | ||
| 197 | assign tte_page_mask = `SPC0.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; | |
| 198 | ||
| 199 | assign tte_pa = {`SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 200 | `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 201 | `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 202 | `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 203 | 13'b0 | |
| 204 | }; | |
| 205 | assign tte_nfo = `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; | |
| 206 | assign tte_ie = `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; | |
| 207 | assign tte_cp = `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; | |
| 208 | assign tte_e = `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; | |
| 209 | assign tte_p = `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; | |
| 210 | assign tte_w = `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; | |
| 211 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 | |
| 212 | ||
| 213 | assign ready = `PARGS.tlb_sync_on & !`SPC0.tcu_spc_mbist_start; | |
| 214 | ||
| 215 | //---------------------------------------------------------- | |
| 216 | initial begin // { | |
| 217 | #1; | |
| 218 | hwtw = 1'b0; | |
| 219 | data_in_ready = 8'b0; | |
| 220 | @ (posedge `SPC0.l2clk); | |
| 221 | end // } | |
| 222 | ||
| 223 | //---------------------------------------------------------- | |
| 224 | // Must use negedge to avoid race condition | |
| 225 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments | |
| 226 | ||
| 227 | always @ (negedge (`SPC0.l2clk & ready)) begin // { | |
| 228 | ||
| 229 | tstamp = `TOP.core_cycle_cnt; | |
| 230 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 231 | ||
| 232 | // Delay by 1 cycle to align with skip_demap | |
| 233 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 234 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 235 | demap_1 <= demap; | |
| 236 | ||
| 237 | // Signal to nas_pipe to suppress SSTEP | |
| 238 | if (asi_wr_itlb!=8'b0) begin // | |
| 239 | for (i=0;i<=7;i=i+1) begin // { | |
| 240 | if (asi_wr_itlb[i]) begin // | |
| 241 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 242 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 243 | `NASTOP.sstep_sent[(mycid * 8) + i] <= 1'b1; // suppress SSTEP | |
| 244 | end // } | |
| 245 | end // } | |
| 246 | end // } | |
| 247 | ||
| 248 | //---------------------------------------------------------- | |
| 249 | // Send I/DTLBWRITE due to demap | |
| 250 | // | |
| 251 | ||
| 252 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 253 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 254 | "C%0d T%0d Illegal Back to Back ITLB demap", | |
| 255 | mycid,demap_tid_1); | |
| 256 | end // } | |
| 257 | ||
| 258 | if (demap_active) begin // { | |
| 259 | fifo.pop_fifo ({hwtw,mytid}); | |
| 260 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 261 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 262 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 263 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 264 | mycid,demap_tid_1,demap_tnum_1,tstamp); | |
| 265 | junk = $sim_send(`PLI_ITLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 266 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 267 | ||
| 268 | // Check to see if sstep was sent early | |
| 269 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 270 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 271 | end //} | |
| 272 | end //} | |
| 273 | end //} | |
| 274 | ||
| 275 | //-------------------- | |
| 276 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 277 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 278 | ||
| 279 | if (demap_active) begin | |
| 280 | case (demap_1) | |
| 281 | 4'b0001: $write ("type=real "); | |
| 282 | 4'b0010: $write ("type=cntx "); | |
| 283 | 4'b0100: $write ("type=page "); | |
| 284 | 4'b1000: $write ("type=all "); | |
| 285 | default: | |
| 286 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 287 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 288 | endcase | |
| 289 | end | |
| 290 | else begin | |
| 291 | $write("type=autodemap "); | |
| 292 | end | |
| 293 | ||
| 294 | $display ("match=%h ts=%0d", | |
| 295 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 296 | ||
| 297 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 298 | if (tlb_match[cnt]==1'b1) begin // { | |
| 299 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 300 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 301 | end // } | |
| 302 | end // } | |
| 303 | ||
| 304 | end // } | |
| 305 | ||
| 306 | //---------------------------------------------------------- | |
| 307 | // Send I/DHWTW due to HWTW | |
| 308 | // Send I/DTLBWRITE due to ASI write | |
| 309 | ||
| 310 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 311 | // These signals will be interleaved between the threads. | |
| 312 | // Need to queue up the signals over time so they can be processed in order. | |
| 313 | // Each thread will only be doing 1 thing at a time. | |
| 314 | ||
| 315 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { | |
| 316 | ||
| 317 | for (i=0;i<=7;i=i+1) begin // { | |
| 318 | ||
| 319 | if ((data_in[i])&&(tlb_wr[i])) begin // { | |
| 320 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 321 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); | |
| 322 | end // } | |
| 323 | else begin // { | |
| 324 | ||
| 325 | // data_in[tid] determines if the write is HWTW or TLBWRITE | |
| 326 | if (data_in[i]) begin // { | |
| 327 | data_in_ready[i] <= 1'b1; | |
| 328 | end // } | |
| 329 | ||
| 330 | // tlb_wr[tid] determines which thread will write next | |
| 331 | // Use fifo to save the tids of the tlb_wr signals in order | |
| 332 | if (tlb_wr[i]) begin // { | |
| 333 | if (data_in_ready[i]) begin // { | |
| 334 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 335 | data_in_ready[i] <= 1'b0; | |
| 336 | end // } | |
| 337 | else begin // { | |
| 338 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 339 | end // } | |
| 340 | end // } | |
| 341 | ||
| 342 | end // if} | |
| 343 | end // for} | |
| 344 | ||
| 345 | end // if} | |
| 346 | ||
| 347 | //---------------------------------------------------------- | |
| 348 | // wr_en means that the write is occurring | |
| 349 | if (wr_en) begin // { | |
| 350 | fifo.pop_fifo ({hwtw,mytid}); | |
| 351 | mytnum = (mycid * 8) + mytid; | |
| 352 | ||
| 353 | if (hwtw) begin // { | |
| 354 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 355 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_IHWTW tid=%d ts=%0d va=%h entry=%h", | |
| 356 | mycid,mytid,mytnum,tstamp,tte_va,entry); | |
| 357 | junk = $sim_send(`PLI_IHWTW, mytnum, tstamp,tte_va,entry); | |
| 358 | ||
| 359 | end //} | |
| 360 | end // } | |
| 361 | else begin // { | |
| 362 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 363 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h", | |
| 364 | mycid,mytid,mytnum,tstamp,entry); | |
| 365 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 366 | mycid,mytid,mytnum,tstamp); | |
| 367 | junk = $sim_send(`PLI_ITLBWRITE, mytnum,tstamp,entry); | |
| 368 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 369 | ||
| 370 | // Check to see if sstep was sent early | |
| 371 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 372 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 373 | end //} | |
| 374 | end //} | |
| 375 | end // } | |
| 376 | ||
| 377 | //-------------------- | |
| 378 | if (`PARGS.show_tlb_on) begin // { | |
| 379 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 380 | ||
| 381 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 382 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 383 | ||
| 384 | case (tte_page_mask) | |
| 385 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 386 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 387 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 388 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 389 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 390 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 391 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 392 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 393 | endcase | |
| 394 | ||
| 395 | if (hwtw) $display (" (hwtw)"); | |
| 396 | else $display (""); | |
| 397 | ||
| 398 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 399 | ||
| 400 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", | |
| 401 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); | |
| 402 | end // } | |
| 403 | //-------------------- | |
| 404 | ||
| 405 | end // } | |
| 406 | ||
| 407 | end // always} | |
| 408 | ||
| 409 | //---------------------------------------------------------- | |
| 410 | `endif | |
| 411 | endmodule | |
| 412 | ||
| 413 | `endif | |
| 414 | `ifdef CORE_1 | |
| 415 | ||
| 416 | module itlb_wr_c1 (); | |
| 417 | `ifndef GATESIM | |
| 418 | ||
| 419 | `include "tlb_sync.vh" | |
| 420 | `include "nas.vh" | |
| 421 | parameter NUM_TLB=64; | |
| 422 | ||
| 423 | wire [7:0] data_in; | |
| 424 | wire [7:0] tlb_wr; | |
| 425 | wire wr_en; | |
| 426 | wire [7:0] entry; | |
| 427 | wire [3:0] demap; | |
| 428 | reg [3:0] demap_1; | |
| 429 | wire demap_page; | |
| 430 | wire demap_context; | |
| 431 | wire demap_real; | |
| 432 | wire demap_all; | |
| 433 | wire skip_demap; | |
| 434 | wire demap_active; | |
| 435 | wire auto_demap; | |
| 436 | wire [2:0] demap_tid; | |
| 437 | reg [2:0] demap_tid_1; | |
| 438 | reg [5:0] demap_tnum_1; | |
| 439 | wire [7:0] asi_wr_itlb; | |
| 440 | wire [7:0] asi_wr_itlb_demap; | |
| 441 | wire [7:0] asi_wr_itlb_data_in; | |
| 442 | wire [7:0] asi_wr_itlb_data_access; | |
| 443 | ||
| 444 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 445 | reg [7:0] data_in_ready; | |
| 446 | reg hwtw; | |
| 447 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 448 | ||
| 449 | reg [2:0] mytid; | |
| 450 | reg [5:0] mytnum; | |
| 451 | wire [2:0] mycid; | |
| 452 | integer junk; | |
| 453 | integer i; | |
| 454 | reg [7:0] cnt; | |
| 455 | wire ready; | |
| 456 | ||
| 457 | assign mycid = 1; | |
| 458 | ||
| 459 | //---------------------------------------------------------- | |
| 460 | // Instantiate fifo - 1 entry per thread | |
| 461 | fifo fifo (); | |
| 462 | // Define fifo parameters | |
| 463 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 464 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 465 | defparam fifo.PTR_BITS = 4; | |
| 466 | ||
| 467 | //---------------------------------------------------------- | |
| 468 | // DUT probes | |
| 469 | ||
| 470 | assign data_in = `SPC1.mmu.asi.htc_wr_itlb_data_in; | |
| 471 | assign tlb_wr = `PROBES1.itlb_wr; | |
| 472 | assign wr_en = `SPC1.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; | |
| 473 | ||
| 474 | assign entry = `SPC1.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; | |
| 475 | ||
| 476 | assign demap_page = `SPC1.ifu_ftu.ftu_itc_ctl.itc_demap_page; | |
| 477 | assign demap_context = `SPC1.ifu_ftu.itc_demap_context; | |
| 478 | assign demap_real = `SPC1.ifu_ftu.itc_demap_real; | |
| 479 | assign demap_all = `SPC1.ifu_ftu.itc_demap_all; | |
| 480 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 481 | assign skip_demap = `SPC1.ifu_ftu.itc_wr_u_en; | |
| 482 | assign demap_tid = `SPC1.ifu_ftu.ftu_itd_dp.tte1[37:35]; | |
| 483 | ||
| 484 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 485 | assign demap_active = |demap_1 && !skip_demap; | |
| 486 | assign auto_demap = |demap_1 && skip_demap; | |
| 487 | ||
| 488 | ||
| 489 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. | |
| 490 | // Once these signals assert, the write to the TLB cannot be cancelled. | |
| 491 | // These signals assert before the MMU reorders the TLB writes. | |
| 492 | // Use these to suppress SSTEP in nas_pipe. | |
| 493 | // Best case, these signals assert 1 cycle after the previous SSTEP. | |
| 494 | assign asi_wr_itlb_demap = `SPC1.mmu.asi_wr_immu_demap; | |
| 495 | assign asi_wr_itlb_data_in = `SPC1.mmu.asi_wr_itlb_data_in; | |
| 496 | assign asi_wr_itlb_data_access = {`SPC1.mmu.asd1.asi_wr_itlb_data_access, | |
| 497 | `SPC1.mmu.asd0.asi_wr_itlb_data_access}; | |
| 498 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; | |
| 499 | ||
| 500 | //--------------------- | |
| 501 | // Probes for debugging | |
| 502 | ||
| 503 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl | |
| 504 | ||
| 505 | // n2_tlb_tl_64x59_cam.sv | |
| 506 | ||
| 507 | `define CNTX1_HI 65 | |
| 508 | `define CNTX1_LO 53 | |
| 509 | `define PID_HI 52 | |
| 510 | `define PID_LO 50 | |
| 511 | `define REAL_BIT 49 | |
| 512 | `define VA_47 48 | |
| 513 | `define VA_28 29 | |
| 514 | `define VA_27 28 | |
| 515 | `define VA_22 23 | |
| 516 | `define TTE_VALID 22 | |
| 517 | `define VA_21 21 | |
| 518 | `define VA_16 16 | |
| 519 | `define VA_15 15 | |
| 520 | `define VA_13 13 | |
| 521 | `define CNTX0_HI 12 | |
| 522 | `define CNTX0_LO 0 | |
| 523 | ||
| 524 | // n2_tlb_tl_64x59_ram.sv | |
| 525 | ||
| 526 | `define DATA_PARITY 36 | |
| 527 | `define DATA_PA_39_28_HI 35 | |
| 528 | `define DATA_PA_39_28_LO 24 | |
| 529 | `define DATA_PA_27_22_HI 23 | |
| 530 | `define DATA_PA_27_22_LO 18 | |
| 531 | `define DATA_VA_27_22_V 17 | |
| 532 | `define DATA_PA_21_16_HI 16 | |
| 533 | `define DATA_PA_21_16_LO 11 | |
| 534 | `define DATA_VA_21_16_V 10 | |
| 535 | `define DATA_PA_15_13_HI 9 | |
| 536 | `define DATA_PA_15_13_LO 7 | |
| 537 | `define DATA_VA_15_13_V 6 | |
| 538 | `define DATA_NFO 5 | |
| 539 | `define DATA_IE 4 | |
| 540 | `define DATA_CP 3 | |
| 541 | `define DATA_X 2 | |
| 542 | `define DATA_P 1 | |
| 543 | `define DATA_W 0 | |
| 544 | ||
| 545 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 546 | wire [(NUM_TLB-1):0] tlb_match; | |
| 547 | wire tte_valid; | |
| 548 | wire [47:0] tte_va; | |
| 549 | wire [12:0] tte_context; | |
| 550 | wire tte_real; | |
| 551 | wire [2:0] tte_pid; | |
| 552 | wire [2:0] tte_page_mask; | |
| 553 | wire [39:0] tte_pa; | |
| 554 | wire tte_nfo; | |
| 555 | wire tte_ie; | |
| 556 | wire tte_cp; | |
| 557 | wire tte_e; | |
| 558 | wire tte_p; | |
| 559 | wire tte_w; | |
| 560 | wire tte_ep; | |
| 561 | ||
| 562 | assign tlb_valid = `SPC1.ifu_ftu.ftu_itb_cust.array.cam.valid; | |
| 563 | assign tlb_match = `SPC1.ifu_ftu.ftu_itb_cust.array.cam.match; | |
| 564 | ||
| 565 | assign tte_va = {`SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], | |
| 566 | `SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], | |
| 567 | `SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], | |
| 568 | `SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], | |
| 569 | 13'b0 | |
| 570 | }; | |
| 571 | assign tte_context = `SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 572 | assign tte_pid = `SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 573 | assign tte_real = `SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; | |
| 574 | assign tte_valid = `SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; | |
| 575 | ||
| 576 | assign tte_page_mask = `SPC1.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; | |
| 577 | ||
| 578 | assign tte_pa = {`SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 579 | `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 580 | `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 581 | `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 582 | 13'b0 | |
| 583 | }; | |
| 584 | assign tte_nfo = `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; | |
| 585 | assign tte_ie = `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; | |
| 586 | assign tte_cp = `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; | |
| 587 | assign tte_e = `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; | |
| 588 | assign tte_p = `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; | |
| 589 | assign tte_w = `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; | |
| 590 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 | |
| 591 | ||
| 592 | assign ready = `PARGS.tlb_sync_on & !`SPC1.tcu_spc_mbist_start; | |
| 593 | ||
| 594 | //---------------------------------------------------------- | |
| 595 | initial begin // { | |
| 596 | #1; | |
| 597 | hwtw = 1'b0; | |
| 598 | data_in_ready = 8'b0; | |
| 599 | @ (posedge `SPC1.l2clk); | |
| 600 | end // } | |
| 601 | ||
| 602 | //---------------------------------------------------------- | |
| 603 | // Must use negedge to avoid race condition | |
| 604 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments | |
| 605 | ||
| 606 | always @ (negedge (`SPC1.l2clk & ready)) begin // { | |
| 607 | ||
| 608 | tstamp = `TOP.core_cycle_cnt; | |
| 609 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 610 | ||
| 611 | // Delay by 1 cycle to align with skip_demap | |
| 612 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 613 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 614 | demap_1 <= demap; | |
| 615 | ||
| 616 | // Signal to nas_pipe to suppress SSTEP | |
| 617 | if (asi_wr_itlb!=8'b0) begin // | |
| 618 | for (i=0;i<=7;i=i+1) begin // { | |
| 619 | if (asi_wr_itlb[i]) begin // | |
| 620 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 621 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 622 | `NASTOP.sstep_sent[(mycid * 8) + i] <= 1'b1; // suppress SSTEP | |
| 623 | end // } | |
| 624 | end // } | |
| 625 | end // } | |
| 626 | ||
| 627 | //---------------------------------------------------------- | |
| 628 | // Send I/DTLBWRITE due to demap | |
| 629 | // | |
| 630 | ||
| 631 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 632 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 633 | "C%0d T%0d Illegal Back to Back ITLB demap", | |
| 634 | mycid,demap_tid_1); | |
| 635 | end // } | |
| 636 | ||
| 637 | if (demap_active) begin // { | |
| 638 | fifo.pop_fifo ({hwtw,mytid}); | |
| 639 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 640 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 641 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 642 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 643 | mycid,demap_tid_1,demap_tnum_1,tstamp); | |
| 644 | junk = $sim_send(`PLI_ITLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 645 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 646 | ||
| 647 | // Check to see if sstep was sent early | |
| 648 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 649 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 650 | end //} | |
| 651 | end //} | |
| 652 | end //} | |
| 653 | ||
| 654 | //-------------------- | |
| 655 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 656 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 657 | ||
| 658 | if (demap_active) begin | |
| 659 | case (demap_1) | |
| 660 | 4'b0001: $write ("type=real "); | |
| 661 | 4'b0010: $write ("type=cntx "); | |
| 662 | 4'b0100: $write ("type=page "); | |
| 663 | 4'b1000: $write ("type=all "); | |
| 664 | default: | |
| 665 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 666 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 667 | endcase | |
| 668 | end | |
| 669 | else begin | |
| 670 | $write("type=autodemap "); | |
| 671 | end | |
| 672 | ||
| 673 | $display ("match=%h ts=%0d", | |
| 674 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 675 | ||
| 676 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 677 | if (tlb_match[cnt]==1'b1) begin // { | |
| 678 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 679 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 680 | end // } | |
| 681 | end // } | |
| 682 | ||
| 683 | end // } | |
| 684 | ||
| 685 | //---------------------------------------------------------- | |
| 686 | // Send I/DHWTW due to HWTW | |
| 687 | // Send I/DTLBWRITE due to ASI write | |
| 688 | ||
| 689 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 690 | // These signals will be interleaved between the threads. | |
| 691 | // Need to queue up the signals over time so they can be processed in order. | |
| 692 | // Each thread will only be doing 1 thing at a time. | |
| 693 | ||
| 694 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { | |
| 695 | ||
| 696 | for (i=0;i<=7;i=i+1) begin // { | |
| 697 | ||
| 698 | if ((data_in[i])&&(tlb_wr[i])) begin // { | |
| 699 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 700 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); | |
| 701 | end // } | |
| 702 | else begin // { | |
| 703 | ||
| 704 | // data_in[tid] determines if the write is HWTW or TLBWRITE | |
| 705 | if (data_in[i]) begin // { | |
| 706 | data_in_ready[i] <= 1'b1; | |
| 707 | end // } | |
| 708 | ||
| 709 | // tlb_wr[tid] determines which thread will write next | |
| 710 | // Use fifo to save the tids of the tlb_wr signals in order | |
| 711 | if (tlb_wr[i]) begin // { | |
| 712 | if (data_in_ready[i]) begin // { | |
| 713 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 714 | data_in_ready[i] <= 1'b0; | |
| 715 | end // } | |
| 716 | else begin // { | |
| 717 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 718 | end // } | |
| 719 | end // } | |
| 720 | ||
| 721 | end // if} | |
| 722 | end // for} | |
| 723 | ||
| 724 | end // if} | |
| 725 | ||
| 726 | //---------------------------------------------------------- | |
| 727 | // wr_en means that the write is occurring | |
| 728 | if (wr_en) begin // { | |
| 729 | fifo.pop_fifo ({hwtw,mytid}); | |
| 730 | mytnum = (mycid * 8) + mytid; | |
| 731 | ||
| 732 | if (hwtw) begin // { | |
| 733 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 734 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_IHWTW tid=%d ts=%0d va=%h entry=%h", | |
| 735 | mycid,mytid,mytnum,tstamp,tte_va,entry); | |
| 736 | junk = $sim_send(`PLI_IHWTW, mytnum, tstamp,tte_va,entry); | |
| 737 | ||
| 738 | end //} | |
| 739 | end // } | |
| 740 | else begin // { | |
| 741 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 742 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h", | |
| 743 | mycid,mytid,mytnum,tstamp,entry); | |
| 744 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 745 | mycid,mytid,mytnum,tstamp); | |
| 746 | junk = $sim_send(`PLI_ITLBWRITE, mytnum,tstamp,entry); | |
| 747 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 748 | ||
| 749 | // Check to see if sstep was sent early | |
| 750 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 751 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 752 | end //} | |
| 753 | end //} | |
| 754 | end // } | |
| 755 | ||
| 756 | //-------------------- | |
| 757 | if (`PARGS.show_tlb_on) begin // { | |
| 758 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 759 | ||
| 760 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 761 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 762 | ||
| 763 | case (tte_page_mask) | |
| 764 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 765 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 766 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 767 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 768 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 769 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 770 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 771 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 772 | endcase | |
| 773 | ||
| 774 | if (hwtw) $display (" (hwtw)"); | |
| 775 | else $display (""); | |
| 776 | ||
| 777 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 778 | ||
| 779 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", | |
| 780 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); | |
| 781 | end // } | |
| 782 | //-------------------- | |
| 783 | ||
| 784 | end // } | |
| 785 | ||
| 786 | end // always} | |
| 787 | ||
| 788 | //---------------------------------------------------------- | |
| 789 | `endif | |
| 790 | endmodule | |
| 791 | ||
| 792 | `endif | |
| 793 | `ifdef CORE_2 | |
| 794 | ||
| 795 | module itlb_wr_c2 (); | |
| 796 | `ifndef GATESIM | |
| 797 | ||
| 798 | `include "tlb_sync.vh" | |
| 799 | `include "nas.vh" | |
| 800 | parameter NUM_TLB=64; | |
| 801 | ||
| 802 | wire [7:0] data_in; | |
| 803 | wire [7:0] tlb_wr; | |
| 804 | wire wr_en; | |
| 805 | wire [7:0] entry; | |
| 806 | wire [3:0] demap; | |
| 807 | reg [3:0] demap_1; | |
| 808 | wire demap_page; | |
| 809 | wire demap_context; | |
| 810 | wire demap_real; | |
| 811 | wire demap_all; | |
| 812 | wire skip_demap; | |
| 813 | wire demap_active; | |
| 814 | wire auto_demap; | |
| 815 | wire [2:0] demap_tid; | |
| 816 | reg [2:0] demap_tid_1; | |
| 817 | reg [5:0] demap_tnum_1; | |
| 818 | wire [7:0] asi_wr_itlb; | |
| 819 | wire [7:0] asi_wr_itlb_demap; | |
| 820 | wire [7:0] asi_wr_itlb_data_in; | |
| 821 | wire [7:0] asi_wr_itlb_data_access; | |
| 822 | ||
| 823 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 824 | reg [7:0] data_in_ready; | |
| 825 | reg hwtw; | |
| 826 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 827 | ||
| 828 | reg [2:0] mytid; | |
| 829 | reg [5:0] mytnum; | |
| 830 | wire [2:0] mycid; | |
| 831 | integer junk; | |
| 832 | integer i; | |
| 833 | reg [7:0] cnt; | |
| 834 | wire ready; | |
| 835 | ||
| 836 | assign mycid = 2; | |
| 837 | ||
| 838 | //---------------------------------------------------------- | |
| 839 | // Instantiate fifo - 1 entry per thread | |
| 840 | fifo fifo (); | |
| 841 | // Define fifo parameters | |
| 842 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 843 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 844 | defparam fifo.PTR_BITS = 4; | |
| 845 | ||
| 846 | //---------------------------------------------------------- | |
| 847 | // DUT probes | |
| 848 | ||
| 849 | assign data_in = `SPC2.mmu.asi.htc_wr_itlb_data_in; | |
| 850 | assign tlb_wr = `PROBES2.itlb_wr; | |
| 851 | assign wr_en = `SPC2.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; | |
| 852 | ||
| 853 | assign entry = `SPC2.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; | |
| 854 | ||
| 855 | assign demap_page = `SPC2.ifu_ftu.ftu_itc_ctl.itc_demap_page; | |
| 856 | assign demap_context = `SPC2.ifu_ftu.itc_demap_context; | |
| 857 | assign demap_real = `SPC2.ifu_ftu.itc_demap_real; | |
| 858 | assign demap_all = `SPC2.ifu_ftu.itc_demap_all; | |
| 859 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 860 | assign skip_demap = `SPC2.ifu_ftu.itc_wr_u_en; | |
| 861 | assign demap_tid = `SPC2.ifu_ftu.ftu_itd_dp.tte1[37:35]; | |
| 862 | ||
| 863 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 864 | assign demap_active = |demap_1 && !skip_demap; | |
| 865 | assign auto_demap = |demap_1 && skip_demap; | |
| 866 | ||
| 867 | ||
| 868 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. | |
| 869 | // Once these signals assert, the write to the TLB cannot be cancelled. | |
| 870 | // These signals assert before the MMU reorders the TLB writes. | |
| 871 | // Use these to suppress SSTEP in nas_pipe. | |
| 872 | // Best case, these signals assert 1 cycle after the previous SSTEP. | |
| 873 | assign asi_wr_itlb_demap = `SPC2.mmu.asi_wr_immu_demap; | |
| 874 | assign asi_wr_itlb_data_in = `SPC2.mmu.asi_wr_itlb_data_in; | |
| 875 | assign asi_wr_itlb_data_access = {`SPC2.mmu.asd1.asi_wr_itlb_data_access, | |
| 876 | `SPC2.mmu.asd0.asi_wr_itlb_data_access}; | |
| 877 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; | |
| 878 | ||
| 879 | //--------------------- | |
| 880 | // Probes for debugging | |
| 881 | ||
| 882 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl | |
| 883 | ||
| 884 | // n2_tlb_tl_64x59_cam.sv | |
| 885 | ||
| 886 | `define CNTX1_HI 65 | |
| 887 | `define CNTX1_LO 53 | |
| 888 | `define PID_HI 52 | |
| 889 | `define PID_LO 50 | |
| 890 | `define REAL_BIT 49 | |
| 891 | `define VA_47 48 | |
| 892 | `define VA_28 29 | |
| 893 | `define VA_27 28 | |
| 894 | `define VA_22 23 | |
| 895 | `define TTE_VALID 22 | |
| 896 | `define VA_21 21 | |
| 897 | `define VA_16 16 | |
| 898 | `define VA_15 15 | |
| 899 | `define VA_13 13 | |
| 900 | `define CNTX0_HI 12 | |
| 901 | `define CNTX0_LO 0 | |
| 902 | ||
| 903 | // n2_tlb_tl_64x59_ram.sv | |
| 904 | ||
| 905 | `define DATA_PARITY 36 | |
| 906 | `define DATA_PA_39_28_HI 35 | |
| 907 | `define DATA_PA_39_28_LO 24 | |
| 908 | `define DATA_PA_27_22_HI 23 | |
| 909 | `define DATA_PA_27_22_LO 18 | |
| 910 | `define DATA_VA_27_22_V 17 | |
| 911 | `define DATA_PA_21_16_HI 16 | |
| 912 | `define DATA_PA_21_16_LO 11 | |
| 913 | `define DATA_VA_21_16_V 10 | |
| 914 | `define DATA_PA_15_13_HI 9 | |
| 915 | `define DATA_PA_15_13_LO 7 | |
| 916 | `define DATA_VA_15_13_V 6 | |
| 917 | `define DATA_NFO 5 | |
| 918 | `define DATA_IE 4 | |
| 919 | `define DATA_CP 3 | |
| 920 | `define DATA_X 2 | |
| 921 | `define DATA_P 1 | |
| 922 | `define DATA_W 0 | |
| 923 | ||
| 924 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 925 | wire [(NUM_TLB-1):0] tlb_match; | |
| 926 | wire tte_valid; | |
| 927 | wire [47:0] tte_va; | |
| 928 | wire [12:0] tte_context; | |
| 929 | wire tte_real; | |
| 930 | wire [2:0] tte_pid; | |
| 931 | wire [2:0] tte_page_mask; | |
| 932 | wire [39:0] tte_pa; | |
| 933 | wire tte_nfo; | |
| 934 | wire tte_ie; | |
| 935 | wire tte_cp; | |
| 936 | wire tte_e; | |
| 937 | wire tte_p; | |
| 938 | wire tte_w; | |
| 939 | wire tte_ep; | |
| 940 | ||
| 941 | assign tlb_valid = `SPC2.ifu_ftu.ftu_itb_cust.array.cam.valid; | |
| 942 | assign tlb_match = `SPC2.ifu_ftu.ftu_itb_cust.array.cam.match; | |
| 943 | ||
| 944 | assign tte_va = {`SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], | |
| 945 | `SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], | |
| 946 | `SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], | |
| 947 | `SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], | |
| 948 | 13'b0 | |
| 949 | }; | |
| 950 | assign tte_context = `SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 951 | assign tte_pid = `SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 952 | assign tte_real = `SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; | |
| 953 | assign tte_valid = `SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; | |
| 954 | ||
| 955 | assign tte_page_mask = `SPC2.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; | |
| 956 | ||
| 957 | assign tte_pa = {`SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 958 | `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 959 | `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 960 | `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 961 | 13'b0 | |
| 962 | }; | |
| 963 | assign tte_nfo = `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; | |
| 964 | assign tte_ie = `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; | |
| 965 | assign tte_cp = `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; | |
| 966 | assign tte_e = `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; | |
| 967 | assign tte_p = `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; | |
| 968 | assign tte_w = `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; | |
| 969 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 | |
| 970 | ||
| 971 | assign ready = `PARGS.tlb_sync_on & !`SPC2.tcu_spc_mbist_start; | |
| 972 | ||
| 973 | //---------------------------------------------------------- | |
| 974 | initial begin // { | |
| 975 | #1; | |
| 976 | hwtw = 1'b0; | |
| 977 | data_in_ready = 8'b0; | |
| 978 | @ (posedge `SPC2.l2clk); | |
| 979 | end // } | |
| 980 | ||
| 981 | //---------------------------------------------------------- | |
| 982 | // Must use negedge to avoid race condition | |
| 983 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments | |
| 984 | ||
| 985 | always @ (negedge (`SPC2.l2clk & ready)) begin // { | |
| 986 | ||
| 987 | tstamp = `TOP.core_cycle_cnt; | |
| 988 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 989 | ||
| 990 | // Delay by 1 cycle to align with skip_demap | |
| 991 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 992 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 993 | demap_1 <= demap; | |
| 994 | ||
| 995 | // Signal to nas_pipe to suppress SSTEP | |
| 996 | if (asi_wr_itlb!=8'b0) begin // | |
| 997 | for (i=0;i<=7;i=i+1) begin // { | |
| 998 | if (asi_wr_itlb[i]) begin // | |
| 999 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 1000 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 1001 | `NASTOP.sstep_sent[(mycid * 8) + i] <= 1'b1; // suppress SSTEP | |
| 1002 | end // } | |
| 1003 | end // } | |
| 1004 | end // } | |
| 1005 | ||
| 1006 | //---------------------------------------------------------- | |
| 1007 | // Send I/DTLBWRITE due to demap | |
| 1008 | // | |
| 1009 | ||
| 1010 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 1011 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1012 | "C%0d T%0d Illegal Back to Back ITLB demap", | |
| 1013 | mycid,demap_tid_1); | |
| 1014 | end // } | |
| 1015 | ||
| 1016 | if (demap_active) begin // { | |
| 1017 | fifo.pop_fifo ({hwtw,mytid}); | |
| 1018 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1019 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 1020 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 1021 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 1022 | mycid,demap_tid_1,demap_tnum_1,tstamp); | |
| 1023 | junk = $sim_send(`PLI_ITLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 1024 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 1025 | ||
| 1026 | // Check to see if sstep was sent early | |
| 1027 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 1028 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 1029 | end //} | |
| 1030 | end //} | |
| 1031 | end //} | |
| 1032 | ||
| 1033 | //-------------------- | |
| 1034 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 1035 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 1036 | ||
| 1037 | if (demap_active) begin | |
| 1038 | case (demap_1) | |
| 1039 | 4'b0001: $write ("type=real "); | |
| 1040 | 4'b0010: $write ("type=cntx "); | |
| 1041 | 4'b0100: $write ("type=page "); | |
| 1042 | 4'b1000: $write ("type=all "); | |
| 1043 | default: | |
| 1044 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1045 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 1046 | endcase | |
| 1047 | end | |
| 1048 | else begin | |
| 1049 | $write("type=autodemap "); | |
| 1050 | end | |
| 1051 | ||
| 1052 | $display ("match=%h ts=%0d", | |
| 1053 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 1054 | ||
| 1055 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 1056 | if (tlb_match[cnt]==1'b1) begin // { | |
| 1057 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 1058 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 1059 | end // } | |
| 1060 | end // } | |
| 1061 | ||
| 1062 | end // } | |
| 1063 | ||
| 1064 | //---------------------------------------------------------- | |
| 1065 | // Send I/DHWTW due to HWTW | |
| 1066 | // Send I/DTLBWRITE due to ASI write | |
| 1067 | ||
| 1068 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 1069 | // These signals will be interleaved between the threads. | |
| 1070 | // Need to queue up the signals over time so they can be processed in order. | |
| 1071 | // Each thread will only be doing 1 thing at a time. | |
| 1072 | ||
| 1073 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { | |
| 1074 | ||
| 1075 | for (i=0;i<=7;i=i+1) begin // { | |
| 1076 | ||
| 1077 | if ((data_in[i])&&(tlb_wr[i])) begin // { | |
| 1078 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1079 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); | |
| 1080 | end // } | |
| 1081 | else begin // { | |
| 1082 | ||
| 1083 | // data_in[tid] determines if the write is HWTW or TLBWRITE | |
| 1084 | if (data_in[i]) begin // { | |
| 1085 | data_in_ready[i] <= 1'b1; | |
| 1086 | end // } | |
| 1087 | ||
| 1088 | // tlb_wr[tid] determines which thread will write next | |
| 1089 | // Use fifo to save the tids of the tlb_wr signals in order | |
| 1090 | if (tlb_wr[i]) begin // { | |
| 1091 | if (data_in_ready[i]) begin // { | |
| 1092 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 1093 | data_in_ready[i] <= 1'b0; | |
| 1094 | end // } | |
| 1095 | else begin // { | |
| 1096 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 1097 | end // } | |
| 1098 | end // } | |
| 1099 | ||
| 1100 | end // if} | |
| 1101 | end // for} | |
| 1102 | ||
| 1103 | end // if} | |
| 1104 | ||
| 1105 | //---------------------------------------------------------- | |
| 1106 | // wr_en means that the write is occurring | |
| 1107 | if (wr_en) begin // { | |
| 1108 | fifo.pop_fifo ({hwtw,mytid}); | |
| 1109 | mytnum = (mycid * 8) + mytid; | |
| 1110 | ||
| 1111 | if (hwtw) begin // { | |
| 1112 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1113 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_IHWTW tid=%d ts=%0d va=%h entry=%h", | |
| 1114 | mycid,mytid,mytnum,tstamp,tte_va,entry); | |
| 1115 | junk = $sim_send(`PLI_IHWTW, mytnum, tstamp,tte_va,entry); | |
| 1116 | ||
| 1117 | end //} | |
| 1118 | end // } | |
| 1119 | else begin // { | |
| 1120 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1121 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h", | |
| 1122 | mycid,mytid,mytnum,tstamp,entry); | |
| 1123 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 1124 | mycid,mytid,mytnum,tstamp); | |
| 1125 | junk = $sim_send(`PLI_ITLBWRITE, mytnum,tstamp,entry); | |
| 1126 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 1127 | ||
| 1128 | // Check to see if sstep was sent early | |
| 1129 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 1130 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 1131 | end //} | |
| 1132 | end //} | |
| 1133 | end // } | |
| 1134 | ||
| 1135 | //-------------------- | |
| 1136 | if (`PARGS.show_tlb_on) begin // { | |
| 1137 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 1138 | ||
| 1139 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 1140 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 1141 | ||
| 1142 | case (tte_page_mask) | |
| 1143 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 1144 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1145 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 1146 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1147 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 1148 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1149 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 1150 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1151 | endcase | |
| 1152 | ||
| 1153 | if (hwtw) $display (" (hwtw)"); | |
| 1154 | else $display (""); | |
| 1155 | ||
| 1156 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 1157 | ||
| 1158 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", | |
| 1159 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); | |
| 1160 | end // } | |
| 1161 | //-------------------- | |
| 1162 | ||
| 1163 | end // } | |
| 1164 | ||
| 1165 | end // always} | |
| 1166 | ||
| 1167 | //---------------------------------------------------------- | |
| 1168 | `endif | |
| 1169 | endmodule | |
| 1170 | ||
| 1171 | `endif | |
| 1172 | `ifdef CORE_3 | |
| 1173 | ||
| 1174 | module itlb_wr_c3 (); | |
| 1175 | `ifndef GATESIM | |
| 1176 | ||
| 1177 | `include "tlb_sync.vh" | |
| 1178 | `include "nas.vh" | |
| 1179 | parameter NUM_TLB=64; | |
| 1180 | ||
| 1181 | wire [7:0] data_in; | |
| 1182 | wire [7:0] tlb_wr; | |
| 1183 | wire wr_en; | |
| 1184 | wire [7:0] entry; | |
| 1185 | wire [3:0] demap; | |
| 1186 | reg [3:0] demap_1; | |
| 1187 | wire demap_page; | |
| 1188 | wire demap_context; | |
| 1189 | wire demap_real; | |
| 1190 | wire demap_all; | |
| 1191 | wire skip_demap; | |
| 1192 | wire demap_active; | |
| 1193 | wire auto_demap; | |
| 1194 | wire [2:0] demap_tid; | |
| 1195 | reg [2:0] demap_tid_1; | |
| 1196 | reg [5:0] demap_tnum_1; | |
| 1197 | wire [7:0] asi_wr_itlb; | |
| 1198 | wire [7:0] asi_wr_itlb_demap; | |
| 1199 | wire [7:0] asi_wr_itlb_data_in; | |
| 1200 | wire [7:0] asi_wr_itlb_data_access; | |
| 1201 | ||
| 1202 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 1203 | reg [7:0] data_in_ready; | |
| 1204 | reg hwtw; | |
| 1205 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 1206 | ||
| 1207 | reg [2:0] mytid; | |
| 1208 | reg [5:0] mytnum; | |
| 1209 | wire [2:0] mycid; | |
| 1210 | integer junk; | |
| 1211 | integer i; | |
| 1212 | reg [7:0] cnt; | |
| 1213 | wire ready; | |
| 1214 | ||
| 1215 | assign mycid = 3; | |
| 1216 | ||
| 1217 | //---------------------------------------------------------- | |
| 1218 | // Instantiate fifo - 1 entry per thread | |
| 1219 | fifo fifo (); | |
| 1220 | // Define fifo parameters | |
| 1221 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 1222 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 1223 | defparam fifo.PTR_BITS = 4; | |
| 1224 | ||
| 1225 | //---------------------------------------------------------- | |
| 1226 | // DUT probes | |
| 1227 | ||
| 1228 | assign data_in = `SPC3.mmu.asi.htc_wr_itlb_data_in; | |
| 1229 | assign tlb_wr = `PROBES3.itlb_wr; | |
| 1230 | assign wr_en = `SPC3.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; | |
| 1231 | ||
| 1232 | assign entry = `SPC3.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; | |
| 1233 | ||
| 1234 | assign demap_page = `SPC3.ifu_ftu.ftu_itc_ctl.itc_demap_page; | |
| 1235 | assign demap_context = `SPC3.ifu_ftu.itc_demap_context; | |
| 1236 | assign demap_real = `SPC3.ifu_ftu.itc_demap_real; | |
| 1237 | assign demap_all = `SPC3.ifu_ftu.itc_demap_all; | |
| 1238 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 1239 | assign skip_demap = `SPC3.ifu_ftu.itc_wr_u_en; | |
| 1240 | assign demap_tid = `SPC3.ifu_ftu.ftu_itd_dp.tte1[37:35]; | |
| 1241 | ||
| 1242 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 1243 | assign demap_active = |demap_1 && !skip_demap; | |
| 1244 | assign auto_demap = |demap_1 && skip_demap; | |
| 1245 | ||
| 1246 | ||
| 1247 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. | |
| 1248 | // Once these signals assert, the write to the TLB cannot be cancelled. | |
| 1249 | // These signals assert before the MMU reorders the TLB writes. | |
| 1250 | // Use these to suppress SSTEP in nas_pipe. | |
| 1251 | // Best case, these signals assert 1 cycle after the previous SSTEP. | |
| 1252 | assign asi_wr_itlb_demap = `SPC3.mmu.asi_wr_immu_demap; | |
| 1253 | assign asi_wr_itlb_data_in = `SPC3.mmu.asi_wr_itlb_data_in; | |
| 1254 | assign asi_wr_itlb_data_access = {`SPC3.mmu.asd1.asi_wr_itlb_data_access, | |
| 1255 | `SPC3.mmu.asd0.asi_wr_itlb_data_access}; | |
| 1256 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; | |
| 1257 | ||
| 1258 | //--------------------- | |
| 1259 | // Probes for debugging | |
| 1260 | ||
| 1261 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl | |
| 1262 | ||
| 1263 | // n2_tlb_tl_64x59_cam.sv | |
| 1264 | ||
| 1265 | `define CNTX1_HI 65 | |
| 1266 | `define CNTX1_LO 53 | |
| 1267 | `define PID_HI 52 | |
| 1268 | `define PID_LO 50 | |
| 1269 | `define REAL_BIT 49 | |
| 1270 | `define VA_47 48 | |
| 1271 | `define VA_28 29 | |
| 1272 | `define VA_27 28 | |
| 1273 | `define VA_22 23 | |
| 1274 | `define TTE_VALID 22 | |
| 1275 | `define VA_21 21 | |
| 1276 | `define VA_16 16 | |
| 1277 | `define VA_15 15 | |
| 1278 | `define VA_13 13 | |
| 1279 | `define CNTX0_HI 12 | |
| 1280 | `define CNTX0_LO 0 | |
| 1281 | ||
| 1282 | // n2_tlb_tl_64x59_ram.sv | |
| 1283 | ||
| 1284 | `define DATA_PARITY 36 | |
| 1285 | `define DATA_PA_39_28_HI 35 | |
| 1286 | `define DATA_PA_39_28_LO 24 | |
| 1287 | `define DATA_PA_27_22_HI 23 | |
| 1288 | `define DATA_PA_27_22_LO 18 | |
| 1289 | `define DATA_VA_27_22_V 17 | |
| 1290 | `define DATA_PA_21_16_HI 16 | |
| 1291 | `define DATA_PA_21_16_LO 11 | |
| 1292 | `define DATA_VA_21_16_V 10 | |
| 1293 | `define DATA_PA_15_13_HI 9 | |
| 1294 | `define DATA_PA_15_13_LO 7 | |
| 1295 | `define DATA_VA_15_13_V 6 | |
| 1296 | `define DATA_NFO 5 | |
| 1297 | `define DATA_IE 4 | |
| 1298 | `define DATA_CP 3 | |
| 1299 | `define DATA_X 2 | |
| 1300 | `define DATA_P 1 | |
| 1301 | `define DATA_W 0 | |
| 1302 | ||
| 1303 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 1304 | wire [(NUM_TLB-1):0] tlb_match; | |
| 1305 | wire tte_valid; | |
| 1306 | wire [47:0] tte_va; | |
| 1307 | wire [12:0] tte_context; | |
| 1308 | wire tte_real; | |
| 1309 | wire [2:0] tte_pid; | |
| 1310 | wire [2:0] tte_page_mask; | |
| 1311 | wire [39:0] tte_pa; | |
| 1312 | wire tte_nfo; | |
| 1313 | wire tte_ie; | |
| 1314 | wire tte_cp; | |
| 1315 | wire tte_e; | |
| 1316 | wire tte_p; | |
| 1317 | wire tte_w; | |
| 1318 | wire tte_ep; | |
| 1319 | ||
| 1320 | assign tlb_valid = `SPC3.ifu_ftu.ftu_itb_cust.array.cam.valid; | |
| 1321 | assign tlb_match = `SPC3.ifu_ftu.ftu_itb_cust.array.cam.match; | |
| 1322 | ||
| 1323 | assign tte_va = {`SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], | |
| 1324 | `SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], | |
| 1325 | `SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], | |
| 1326 | `SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], | |
| 1327 | 13'b0 | |
| 1328 | }; | |
| 1329 | assign tte_context = `SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 1330 | assign tte_pid = `SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 1331 | assign tte_real = `SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; | |
| 1332 | assign tte_valid = `SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; | |
| 1333 | ||
| 1334 | assign tte_page_mask = `SPC3.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; | |
| 1335 | ||
| 1336 | assign tte_pa = {`SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 1337 | `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 1338 | `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 1339 | `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 1340 | 13'b0 | |
| 1341 | }; | |
| 1342 | assign tte_nfo = `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; | |
| 1343 | assign tte_ie = `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; | |
| 1344 | assign tte_cp = `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; | |
| 1345 | assign tte_e = `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; | |
| 1346 | assign tte_p = `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; | |
| 1347 | assign tte_w = `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; | |
| 1348 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 | |
| 1349 | ||
| 1350 | assign ready = `PARGS.tlb_sync_on & !`SPC3.tcu_spc_mbist_start; | |
| 1351 | ||
| 1352 | //---------------------------------------------------------- | |
| 1353 | initial begin // { | |
| 1354 | #1; | |
| 1355 | hwtw = 1'b0; | |
| 1356 | data_in_ready = 8'b0; | |
| 1357 | @ (posedge `SPC3.l2clk); | |
| 1358 | end // } | |
| 1359 | ||
| 1360 | //---------------------------------------------------------- | |
| 1361 | // Must use negedge to avoid race condition | |
| 1362 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments | |
| 1363 | ||
| 1364 | always @ (negedge (`SPC3.l2clk & ready)) begin // { | |
| 1365 | ||
| 1366 | tstamp = `TOP.core_cycle_cnt; | |
| 1367 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 1368 | ||
| 1369 | // Delay by 1 cycle to align with skip_demap | |
| 1370 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 1371 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 1372 | demap_1 <= demap; | |
| 1373 | ||
| 1374 | // Signal to nas_pipe to suppress SSTEP | |
| 1375 | if (asi_wr_itlb!=8'b0) begin // | |
| 1376 | for (i=0;i<=7;i=i+1) begin // { | |
| 1377 | if (asi_wr_itlb[i]) begin // | |
| 1378 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 1379 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 1380 | `NASTOP.sstep_sent[(mycid * 8) + i] <= 1'b1; // suppress SSTEP | |
| 1381 | end // } | |
| 1382 | end // } | |
| 1383 | end // } | |
| 1384 | ||
| 1385 | //---------------------------------------------------------- | |
| 1386 | // Send I/DTLBWRITE due to demap | |
| 1387 | // | |
| 1388 | ||
| 1389 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 1390 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1391 | "C%0d T%0d Illegal Back to Back ITLB demap", | |
| 1392 | mycid,demap_tid_1); | |
| 1393 | end // } | |
| 1394 | ||
| 1395 | if (demap_active) begin // { | |
| 1396 | fifo.pop_fifo ({hwtw,mytid}); | |
| 1397 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1398 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 1399 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 1400 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 1401 | mycid,demap_tid_1,demap_tnum_1,tstamp); | |
| 1402 | junk = $sim_send(`PLI_ITLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 1403 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 1404 | ||
| 1405 | // Check to see if sstep was sent early | |
| 1406 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 1407 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 1408 | end //} | |
| 1409 | end //} | |
| 1410 | end //} | |
| 1411 | ||
| 1412 | //-------------------- | |
| 1413 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 1414 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 1415 | ||
| 1416 | if (demap_active) begin | |
| 1417 | case (demap_1) | |
| 1418 | 4'b0001: $write ("type=real "); | |
| 1419 | 4'b0010: $write ("type=cntx "); | |
| 1420 | 4'b0100: $write ("type=page "); | |
| 1421 | 4'b1000: $write ("type=all "); | |
| 1422 | default: | |
| 1423 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1424 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 1425 | endcase | |
| 1426 | end | |
| 1427 | else begin | |
| 1428 | $write("type=autodemap "); | |
| 1429 | end | |
| 1430 | ||
| 1431 | $display ("match=%h ts=%0d", | |
| 1432 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 1433 | ||
| 1434 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 1435 | if (tlb_match[cnt]==1'b1) begin // { | |
| 1436 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 1437 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 1438 | end // } | |
| 1439 | end // } | |
| 1440 | ||
| 1441 | end // } | |
| 1442 | ||
| 1443 | //---------------------------------------------------------- | |
| 1444 | // Send I/DHWTW due to HWTW | |
| 1445 | // Send I/DTLBWRITE due to ASI write | |
| 1446 | ||
| 1447 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 1448 | // These signals will be interleaved between the threads. | |
| 1449 | // Need to queue up the signals over time so they can be processed in order. | |
| 1450 | // Each thread will only be doing 1 thing at a time. | |
| 1451 | ||
| 1452 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { | |
| 1453 | ||
| 1454 | for (i=0;i<=7;i=i+1) begin // { | |
| 1455 | ||
| 1456 | if ((data_in[i])&&(tlb_wr[i])) begin // { | |
| 1457 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1458 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); | |
| 1459 | end // } | |
| 1460 | else begin // { | |
| 1461 | ||
| 1462 | // data_in[tid] determines if the write is HWTW or TLBWRITE | |
| 1463 | if (data_in[i]) begin // { | |
| 1464 | data_in_ready[i] <= 1'b1; | |
| 1465 | end // } | |
| 1466 | ||
| 1467 | // tlb_wr[tid] determines which thread will write next | |
| 1468 | // Use fifo to save the tids of the tlb_wr signals in order | |
| 1469 | if (tlb_wr[i]) begin // { | |
| 1470 | if (data_in_ready[i]) begin // { | |
| 1471 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 1472 | data_in_ready[i] <= 1'b0; | |
| 1473 | end // } | |
| 1474 | else begin // { | |
| 1475 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 1476 | end // } | |
| 1477 | end // } | |
| 1478 | ||
| 1479 | end // if} | |
| 1480 | end // for} | |
| 1481 | ||
| 1482 | end // if} | |
| 1483 | ||
| 1484 | //---------------------------------------------------------- | |
| 1485 | // wr_en means that the write is occurring | |
| 1486 | if (wr_en) begin // { | |
| 1487 | fifo.pop_fifo ({hwtw,mytid}); | |
| 1488 | mytnum = (mycid * 8) + mytid; | |
| 1489 | ||
| 1490 | if (hwtw) begin // { | |
| 1491 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1492 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_IHWTW tid=%d ts=%0d va=%h entry=%h", | |
| 1493 | mycid,mytid,mytnum,tstamp,tte_va,entry); | |
| 1494 | junk = $sim_send(`PLI_IHWTW, mytnum, tstamp,tte_va,entry); | |
| 1495 | ||
| 1496 | end //} | |
| 1497 | end // } | |
| 1498 | else begin // { | |
| 1499 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1500 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h", | |
| 1501 | mycid,mytid,mytnum,tstamp,entry); | |
| 1502 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 1503 | mycid,mytid,mytnum,tstamp); | |
| 1504 | junk = $sim_send(`PLI_ITLBWRITE, mytnum,tstamp,entry); | |
| 1505 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 1506 | ||
| 1507 | // Check to see if sstep was sent early | |
| 1508 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 1509 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 1510 | end //} | |
| 1511 | end //} | |
| 1512 | end // } | |
| 1513 | ||
| 1514 | //-------------------- | |
| 1515 | if (`PARGS.show_tlb_on) begin // { | |
| 1516 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 1517 | ||
| 1518 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 1519 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 1520 | ||
| 1521 | case (tte_page_mask) | |
| 1522 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 1523 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1524 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 1525 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1526 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 1527 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1528 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 1529 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1530 | endcase | |
| 1531 | ||
| 1532 | if (hwtw) $display (" (hwtw)"); | |
| 1533 | else $display (""); | |
| 1534 | ||
| 1535 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 1536 | ||
| 1537 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", | |
| 1538 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); | |
| 1539 | end // } | |
| 1540 | //-------------------- | |
| 1541 | ||
| 1542 | end // } | |
| 1543 | ||
| 1544 | end // always} | |
| 1545 | ||
| 1546 | //---------------------------------------------------------- | |
| 1547 | `endif | |
| 1548 | endmodule | |
| 1549 | ||
| 1550 | `endif | |
| 1551 | `ifdef CORE_4 | |
| 1552 | ||
| 1553 | module itlb_wr_c4 (); | |
| 1554 | `ifndef GATESIM | |
| 1555 | ||
| 1556 | `include "tlb_sync.vh" | |
| 1557 | `include "nas.vh" | |
| 1558 | parameter NUM_TLB=64; | |
| 1559 | ||
| 1560 | wire [7:0] data_in; | |
| 1561 | wire [7:0] tlb_wr; | |
| 1562 | wire wr_en; | |
| 1563 | wire [7:0] entry; | |
| 1564 | wire [3:0] demap; | |
| 1565 | reg [3:0] demap_1; | |
| 1566 | wire demap_page; | |
| 1567 | wire demap_context; | |
| 1568 | wire demap_real; | |
| 1569 | wire demap_all; | |
| 1570 | wire skip_demap; | |
| 1571 | wire demap_active; | |
| 1572 | wire auto_demap; | |
| 1573 | wire [2:0] demap_tid; | |
| 1574 | reg [2:0] demap_tid_1; | |
| 1575 | reg [5:0] demap_tnum_1; | |
| 1576 | wire [7:0] asi_wr_itlb; | |
| 1577 | wire [7:0] asi_wr_itlb_demap; | |
| 1578 | wire [7:0] asi_wr_itlb_data_in; | |
| 1579 | wire [7:0] asi_wr_itlb_data_access; | |
| 1580 | ||
| 1581 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 1582 | reg [7:0] data_in_ready; | |
| 1583 | reg hwtw; | |
| 1584 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 1585 | ||
| 1586 | reg [2:0] mytid; | |
| 1587 | reg [5:0] mytnum; | |
| 1588 | wire [2:0] mycid; | |
| 1589 | integer junk; | |
| 1590 | integer i; | |
| 1591 | reg [7:0] cnt; | |
| 1592 | wire ready; | |
| 1593 | ||
| 1594 | assign mycid = 4; | |
| 1595 | ||
| 1596 | //---------------------------------------------------------- | |
| 1597 | // Instantiate fifo - 1 entry per thread | |
| 1598 | fifo fifo (); | |
| 1599 | // Define fifo parameters | |
| 1600 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 1601 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 1602 | defparam fifo.PTR_BITS = 4; | |
| 1603 | ||
| 1604 | //---------------------------------------------------------- | |
| 1605 | // DUT probes | |
| 1606 | ||
| 1607 | assign data_in = `SPC4.mmu.asi.htc_wr_itlb_data_in; | |
| 1608 | assign tlb_wr = `PROBES4.itlb_wr; | |
| 1609 | assign wr_en = `SPC4.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; | |
| 1610 | ||
| 1611 | assign entry = `SPC4.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; | |
| 1612 | ||
| 1613 | assign demap_page = `SPC4.ifu_ftu.ftu_itc_ctl.itc_demap_page; | |
| 1614 | assign demap_context = `SPC4.ifu_ftu.itc_demap_context; | |
| 1615 | assign demap_real = `SPC4.ifu_ftu.itc_demap_real; | |
| 1616 | assign demap_all = `SPC4.ifu_ftu.itc_demap_all; | |
| 1617 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 1618 | assign skip_demap = `SPC4.ifu_ftu.itc_wr_u_en; | |
| 1619 | assign demap_tid = `SPC4.ifu_ftu.ftu_itd_dp.tte1[37:35]; | |
| 1620 | ||
| 1621 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 1622 | assign demap_active = |demap_1 && !skip_demap; | |
| 1623 | assign auto_demap = |demap_1 && skip_demap; | |
| 1624 | ||
| 1625 | ||
| 1626 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. | |
| 1627 | // Once these signals assert, the write to the TLB cannot be cancelled. | |
| 1628 | // These signals assert before the MMU reorders the TLB writes. | |
| 1629 | // Use these to suppress SSTEP in nas_pipe. | |
| 1630 | // Best case, these signals assert 1 cycle after the previous SSTEP. | |
| 1631 | assign asi_wr_itlb_demap = `SPC4.mmu.asi_wr_immu_demap; | |
| 1632 | assign asi_wr_itlb_data_in = `SPC4.mmu.asi_wr_itlb_data_in; | |
| 1633 | assign asi_wr_itlb_data_access = {`SPC4.mmu.asd1.asi_wr_itlb_data_access, | |
| 1634 | `SPC4.mmu.asd0.asi_wr_itlb_data_access}; | |
| 1635 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; | |
| 1636 | ||
| 1637 | //--------------------- | |
| 1638 | // Probes for debugging | |
| 1639 | ||
| 1640 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl | |
| 1641 | ||
| 1642 | // n2_tlb_tl_64x59_cam.sv | |
| 1643 | ||
| 1644 | `define CNTX1_HI 65 | |
| 1645 | `define CNTX1_LO 53 | |
| 1646 | `define PID_HI 52 | |
| 1647 | `define PID_LO 50 | |
| 1648 | `define REAL_BIT 49 | |
| 1649 | `define VA_47 48 | |
| 1650 | `define VA_28 29 | |
| 1651 | `define VA_27 28 | |
| 1652 | `define VA_22 23 | |
| 1653 | `define TTE_VALID 22 | |
| 1654 | `define VA_21 21 | |
| 1655 | `define VA_16 16 | |
| 1656 | `define VA_15 15 | |
| 1657 | `define VA_13 13 | |
| 1658 | `define CNTX0_HI 12 | |
| 1659 | `define CNTX0_LO 0 | |
| 1660 | ||
| 1661 | // n2_tlb_tl_64x59_ram.sv | |
| 1662 | ||
| 1663 | `define DATA_PARITY 36 | |
| 1664 | `define DATA_PA_39_28_HI 35 | |
| 1665 | `define DATA_PA_39_28_LO 24 | |
| 1666 | `define DATA_PA_27_22_HI 23 | |
| 1667 | `define DATA_PA_27_22_LO 18 | |
| 1668 | `define DATA_VA_27_22_V 17 | |
| 1669 | `define DATA_PA_21_16_HI 16 | |
| 1670 | `define DATA_PA_21_16_LO 11 | |
| 1671 | `define DATA_VA_21_16_V 10 | |
| 1672 | `define DATA_PA_15_13_HI 9 | |
| 1673 | `define DATA_PA_15_13_LO 7 | |
| 1674 | `define DATA_VA_15_13_V 6 | |
| 1675 | `define DATA_NFO 5 | |
| 1676 | `define DATA_IE 4 | |
| 1677 | `define DATA_CP 3 | |
| 1678 | `define DATA_X 2 | |
| 1679 | `define DATA_P 1 | |
| 1680 | `define DATA_W 0 | |
| 1681 | ||
| 1682 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 1683 | wire [(NUM_TLB-1):0] tlb_match; | |
| 1684 | wire tte_valid; | |
| 1685 | wire [47:0] tte_va; | |
| 1686 | wire [12:0] tte_context; | |
| 1687 | wire tte_real; | |
| 1688 | wire [2:0] tte_pid; | |
| 1689 | wire [2:0] tte_page_mask; | |
| 1690 | wire [39:0] tte_pa; | |
| 1691 | wire tte_nfo; | |
| 1692 | wire tte_ie; | |
| 1693 | wire tte_cp; | |
| 1694 | wire tte_e; | |
| 1695 | wire tte_p; | |
| 1696 | wire tte_w; | |
| 1697 | wire tte_ep; | |
| 1698 | ||
| 1699 | assign tlb_valid = `SPC4.ifu_ftu.ftu_itb_cust.array.cam.valid; | |
| 1700 | assign tlb_match = `SPC4.ifu_ftu.ftu_itb_cust.array.cam.match; | |
| 1701 | ||
| 1702 | assign tte_va = {`SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], | |
| 1703 | `SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], | |
| 1704 | `SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], | |
| 1705 | `SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], | |
| 1706 | 13'b0 | |
| 1707 | }; | |
| 1708 | assign tte_context = `SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 1709 | assign tte_pid = `SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 1710 | assign tte_real = `SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; | |
| 1711 | assign tte_valid = `SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; | |
| 1712 | ||
| 1713 | assign tte_page_mask = `SPC4.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; | |
| 1714 | ||
| 1715 | assign tte_pa = {`SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 1716 | `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 1717 | `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 1718 | `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 1719 | 13'b0 | |
| 1720 | }; | |
| 1721 | assign tte_nfo = `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; | |
| 1722 | assign tte_ie = `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; | |
| 1723 | assign tte_cp = `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; | |
| 1724 | assign tte_e = `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; | |
| 1725 | assign tte_p = `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; | |
| 1726 | assign tte_w = `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; | |
| 1727 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 | |
| 1728 | ||
| 1729 | assign ready = `PARGS.tlb_sync_on & !`SPC4.tcu_spc_mbist_start; | |
| 1730 | ||
| 1731 | //---------------------------------------------------------- | |
| 1732 | initial begin // { | |
| 1733 | #1; | |
| 1734 | hwtw = 1'b0; | |
| 1735 | data_in_ready = 8'b0; | |
| 1736 | @ (posedge `SPC4.l2clk); | |
| 1737 | end // } | |
| 1738 | ||
| 1739 | //---------------------------------------------------------- | |
| 1740 | // Must use negedge to avoid race condition | |
| 1741 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments | |
| 1742 | ||
| 1743 | always @ (negedge (`SPC4.l2clk & ready)) begin // { | |
| 1744 | ||
| 1745 | tstamp = `TOP.core_cycle_cnt; | |
| 1746 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 1747 | ||
| 1748 | // Delay by 1 cycle to align with skip_demap | |
| 1749 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 1750 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 1751 | demap_1 <= demap; | |
| 1752 | ||
| 1753 | // Signal to nas_pipe to suppress SSTEP | |
| 1754 | if (asi_wr_itlb!=8'b0) begin // | |
| 1755 | for (i=0;i<=7;i=i+1) begin // { | |
| 1756 | if (asi_wr_itlb[i]) begin // | |
| 1757 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 1758 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 1759 | `NASTOP.sstep_sent[(mycid * 8) + i] <= 1'b1; // suppress SSTEP | |
| 1760 | end // } | |
| 1761 | end // } | |
| 1762 | end // } | |
| 1763 | ||
| 1764 | //---------------------------------------------------------- | |
| 1765 | // Send I/DTLBWRITE due to demap | |
| 1766 | // | |
| 1767 | ||
| 1768 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 1769 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1770 | "C%0d T%0d Illegal Back to Back ITLB demap", | |
| 1771 | mycid,demap_tid_1); | |
| 1772 | end // } | |
| 1773 | ||
| 1774 | if (demap_active) begin // { | |
| 1775 | fifo.pop_fifo ({hwtw,mytid}); | |
| 1776 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1777 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 1778 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 1779 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 1780 | mycid,demap_tid_1,demap_tnum_1,tstamp); | |
| 1781 | junk = $sim_send(`PLI_ITLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 1782 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 1783 | ||
| 1784 | // Check to see if sstep was sent early | |
| 1785 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 1786 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 1787 | end //} | |
| 1788 | end //} | |
| 1789 | end //} | |
| 1790 | ||
| 1791 | //-------------------- | |
| 1792 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 1793 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 1794 | ||
| 1795 | if (demap_active) begin | |
| 1796 | case (demap_1) | |
| 1797 | 4'b0001: $write ("type=real "); | |
| 1798 | 4'b0010: $write ("type=cntx "); | |
| 1799 | 4'b0100: $write ("type=page "); | |
| 1800 | 4'b1000: $write ("type=all "); | |
| 1801 | default: | |
| 1802 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1803 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 1804 | endcase | |
| 1805 | end | |
| 1806 | else begin | |
| 1807 | $write("type=autodemap "); | |
| 1808 | end | |
| 1809 | ||
| 1810 | $display ("match=%h ts=%0d", | |
| 1811 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 1812 | ||
| 1813 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 1814 | if (tlb_match[cnt]==1'b1) begin // { | |
| 1815 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 1816 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 1817 | end // } | |
| 1818 | end // } | |
| 1819 | ||
| 1820 | end // } | |
| 1821 | ||
| 1822 | //---------------------------------------------------------- | |
| 1823 | // Send I/DHWTW due to HWTW | |
| 1824 | // Send I/DTLBWRITE due to ASI write | |
| 1825 | ||
| 1826 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 1827 | // These signals will be interleaved between the threads. | |
| 1828 | // Need to queue up the signals over time so they can be processed in order. | |
| 1829 | // Each thread will only be doing 1 thing at a time. | |
| 1830 | ||
| 1831 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { | |
| 1832 | ||
| 1833 | for (i=0;i<=7;i=i+1) begin // { | |
| 1834 | ||
| 1835 | if ((data_in[i])&&(tlb_wr[i])) begin // { | |
| 1836 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1837 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); | |
| 1838 | end // } | |
| 1839 | else begin // { | |
| 1840 | ||
| 1841 | // data_in[tid] determines if the write is HWTW or TLBWRITE | |
| 1842 | if (data_in[i]) begin // { | |
| 1843 | data_in_ready[i] <= 1'b1; | |
| 1844 | end // } | |
| 1845 | ||
| 1846 | // tlb_wr[tid] determines which thread will write next | |
| 1847 | // Use fifo to save the tids of the tlb_wr signals in order | |
| 1848 | if (tlb_wr[i]) begin // { | |
| 1849 | if (data_in_ready[i]) begin // { | |
| 1850 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 1851 | data_in_ready[i] <= 1'b0; | |
| 1852 | end // } | |
| 1853 | else begin // { | |
| 1854 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 1855 | end // } | |
| 1856 | end // } | |
| 1857 | ||
| 1858 | end // if} | |
| 1859 | end // for} | |
| 1860 | ||
| 1861 | end // if} | |
| 1862 | ||
| 1863 | //---------------------------------------------------------- | |
| 1864 | // wr_en means that the write is occurring | |
| 1865 | if (wr_en) begin // { | |
| 1866 | fifo.pop_fifo ({hwtw,mytid}); | |
| 1867 | mytnum = (mycid * 8) + mytid; | |
| 1868 | ||
| 1869 | if (hwtw) begin // { | |
| 1870 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1871 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_IHWTW tid=%d ts=%0d va=%h entry=%h", | |
| 1872 | mycid,mytid,mytnum,tstamp,tte_va,entry); | |
| 1873 | junk = $sim_send(`PLI_IHWTW, mytnum, tstamp,tte_va,entry); | |
| 1874 | ||
| 1875 | end //} | |
| 1876 | end // } | |
| 1877 | else begin // { | |
| 1878 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1879 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h", | |
| 1880 | mycid,mytid,mytnum,tstamp,entry); | |
| 1881 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 1882 | mycid,mytid,mytnum,tstamp); | |
| 1883 | junk = $sim_send(`PLI_ITLBWRITE, mytnum,tstamp,entry); | |
| 1884 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 1885 | ||
| 1886 | // Check to see if sstep was sent early | |
| 1887 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 1888 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 1889 | end //} | |
| 1890 | end //} | |
| 1891 | end // } | |
| 1892 | ||
| 1893 | //-------------------- | |
| 1894 | if (`PARGS.show_tlb_on) begin // { | |
| 1895 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 1896 | ||
| 1897 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 1898 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 1899 | ||
| 1900 | case (tte_page_mask) | |
| 1901 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 1902 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1903 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 1904 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1905 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 1906 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1907 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 1908 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1909 | endcase | |
| 1910 | ||
| 1911 | if (hwtw) $display (" (hwtw)"); | |
| 1912 | else $display (""); | |
| 1913 | ||
| 1914 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 1915 | ||
| 1916 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", | |
| 1917 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); | |
| 1918 | end // } | |
| 1919 | //-------------------- | |
| 1920 | ||
| 1921 | end // } | |
| 1922 | ||
| 1923 | end // always} | |
| 1924 | ||
| 1925 | //---------------------------------------------------------- | |
| 1926 | `endif | |
| 1927 | endmodule | |
| 1928 | ||
| 1929 | `endif | |
| 1930 | `ifdef CORE_5 | |
| 1931 | ||
| 1932 | module itlb_wr_c5 (); | |
| 1933 | `ifndef GATESIM | |
| 1934 | ||
| 1935 | `include "tlb_sync.vh" | |
| 1936 | `include "nas.vh" | |
| 1937 | parameter NUM_TLB=64; | |
| 1938 | ||
| 1939 | wire [7:0] data_in; | |
| 1940 | wire [7:0] tlb_wr; | |
| 1941 | wire wr_en; | |
| 1942 | wire [7:0] entry; | |
| 1943 | wire [3:0] demap; | |
| 1944 | reg [3:0] demap_1; | |
| 1945 | wire demap_page; | |
| 1946 | wire demap_context; | |
| 1947 | wire demap_real; | |
| 1948 | wire demap_all; | |
| 1949 | wire skip_demap; | |
| 1950 | wire demap_active; | |
| 1951 | wire auto_demap; | |
| 1952 | wire [2:0] demap_tid; | |
| 1953 | reg [2:0] demap_tid_1; | |
| 1954 | reg [5:0] demap_tnum_1; | |
| 1955 | wire [7:0] asi_wr_itlb; | |
| 1956 | wire [7:0] asi_wr_itlb_demap; | |
| 1957 | wire [7:0] asi_wr_itlb_data_in; | |
| 1958 | wire [7:0] asi_wr_itlb_data_access; | |
| 1959 | ||
| 1960 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 1961 | reg [7:0] data_in_ready; | |
| 1962 | reg hwtw; | |
| 1963 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 1964 | ||
| 1965 | reg [2:0] mytid; | |
| 1966 | reg [5:0] mytnum; | |
| 1967 | wire [2:0] mycid; | |
| 1968 | integer junk; | |
| 1969 | integer i; | |
| 1970 | reg [7:0] cnt; | |
| 1971 | wire ready; | |
| 1972 | ||
| 1973 | assign mycid = 5; | |
| 1974 | ||
| 1975 | //---------------------------------------------------------- | |
| 1976 | // Instantiate fifo - 1 entry per thread | |
| 1977 | fifo fifo (); | |
| 1978 | // Define fifo parameters | |
| 1979 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 1980 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 1981 | defparam fifo.PTR_BITS = 4; | |
| 1982 | ||
| 1983 | //---------------------------------------------------------- | |
| 1984 | // DUT probes | |
| 1985 | ||
| 1986 | assign data_in = `SPC5.mmu.asi.htc_wr_itlb_data_in; | |
| 1987 | assign tlb_wr = `PROBES5.itlb_wr; | |
| 1988 | assign wr_en = `SPC5.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; | |
| 1989 | ||
| 1990 | assign entry = `SPC5.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; | |
| 1991 | ||
| 1992 | assign demap_page = `SPC5.ifu_ftu.ftu_itc_ctl.itc_demap_page; | |
| 1993 | assign demap_context = `SPC5.ifu_ftu.itc_demap_context; | |
| 1994 | assign demap_real = `SPC5.ifu_ftu.itc_demap_real; | |
| 1995 | assign demap_all = `SPC5.ifu_ftu.itc_demap_all; | |
| 1996 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 1997 | assign skip_demap = `SPC5.ifu_ftu.itc_wr_u_en; | |
| 1998 | assign demap_tid = `SPC5.ifu_ftu.ftu_itd_dp.tte1[37:35]; | |
| 1999 | ||
| 2000 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 2001 | assign demap_active = |demap_1 && !skip_demap; | |
| 2002 | assign auto_demap = |demap_1 && skip_demap; | |
| 2003 | ||
| 2004 | ||
| 2005 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. | |
| 2006 | // Once these signals assert, the write to the TLB cannot be cancelled. | |
| 2007 | // These signals assert before the MMU reorders the TLB writes. | |
| 2008 | // Use these to suppress SSTEP in nas_pipe. | |
| 2009 | // Best case, these signals assert 1 cycle after the previous SSTEP. | |
| 2010 | assign asi_wr_itlb_demap = `SPC5.mmu.asi_wr_immu_demap; | |
| 2011 | assign asi_wr_itlb_data_in = `SPC5.mmu.asi_wr_itlb_data_in; | |
| 2012 | assign asi_wr_itlb_data_access = {`SPC5.mmu.asd1.asi_wr_itlb_data_access, | |
| 2013 | `SPC5.mmu.asd0.asi_wr_itlb_data_access}; | |
| 2014 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; | |
| 2015 | ||
| 2016 | //--------------------- | |
| 2017 | // Probes for debugging | |
| 2018 | ||
| 2019 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl | |
| 2020 | ||
| 2021 | // n2_tlb_tl_64x59_cam.sv | |
| 2022 | ||
| 2023 | `define CNTX1_HI 65 | |
| 2024 | `define CNTX1_LO 53 | |
| 2025 | `define PID_HI 52 | |
| 2026 | `define PID_LO 50 | |
| 2027 | `define REAL_BIT 49 | |
| 2028 | `define VA_47 48 | |
| 2029 | `define VA_28 29 | |
| 2030 | `define VA_27 28 | |
| 2031 | `define VA_22 23 | |
| 2032 | `define TTE_VALID 22 | |
| 2033 | `define VA_21 21 | |
| 2034 | `define VA_16 16 | |
| 2035 | `define VA_15 15 | |
| 2036 | `define VA_13 13 | |
| 2037 | `define CNTX0_HI 12 | |
| 2038 | `define CNTX0_LO 0 | |
| 2039 | ||
| 2040 | // n2_tlb_tl_64x59_ram.sv | |
| 2041 | ||
| 2042 | `define DATA_PARITY 36 | |
| 2043 | `define DATA_PA_39_28_HI 35 | |
| 2044 | `define DATA_PA_39_28_LO 24 | |
| 2045 | `define DATA_PA_27_22_HI 23 | |
| 2046 | `define DATA_PA_27_22_LO 18 | |
| 2047 | `define DATA_VA_27_22_V 17 | |
| 2048 | `define DATA_PA_21_16_HI 16 | |
| 2049 | `define DATA_PA_21_16_LO 11 | |
| 2050 | `define DATA_VA_21_16_V 10 | |
| 2051 | `define DATA_PA_15_13_HI 9 | |
| 2052 | `define DATA_PA_15_13_LO 7 | |
| 2053 | `define DATA_VA_15_13_V 6 | |
| 2054 | `define DATA_NFO 5 | |
| 2055 | `define DATA_IE 4 | |
| 2056 | `define DATA_CP 3 | |
| 2057 | `define DATA_X 2 | |
| 2058 | `define DATA_P 1 | |
| 2059 | `define DATA_W 0 | |
| 2060 | ||
| 2061 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 2062 | wire [(NUM_TLB-1):0] tlb_match; | |
| 2063 | wire tte_valid; | |
| 2064 | wire [47:0] tte_va; | |
| 2065 | wire [12:0] tte_context; | |
| 2066 | wire tte_real; | |
| 2067 | wire [2:0] tte_pid; | |
| 2068 | wire [2:0] tte_page_mask; | |
| 2069 | wire [39:0] tte_pa; | |
| 2070 | wire tte_nfo; | |
| 2071 | wire tte_ie; | |
| 2072 | wire tte_cp; | |
| 2073 | wire tte_e; | |
| 2074 | wire tte_p; | |
| 2075 | wire tte_w; | |
| 2076 | wire tte_ep; | |
| 2077 | ||
| 2078 | assign tlb_valid = `SPC5.ifu_ftu.ftu_itb_cust.array.cam.valid; | |
| 2079 | assign tlb_match = `SPC5.ifu_ftu.ftu_itb_cust.array.cam.match; | |
| 2080 | ||
| 2081 | assign tte_va = {`SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], | |
| 2082 | `SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], | |
| 2083 | `SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], | |
| 2084 | `SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], | |
| 2085 | 13'b0 | |
| 2086 | }; | |
| 2087 | assign tte_context = `SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 2088 | assign tte_pid = `SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 2089 | assign tte_real = `SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; | |
| 2090 | assign tte_valid = `SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; | |
| 2091 | ||
| 2092 | assign tte_page_mask = `SPC5.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; | |
| 2093 | ||
| 2094 | assign tte_pa = {`SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 2095 | `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 2096 | `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 2097 | `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 2098 | 13'b0 | |
| 2099 | }; | |
| 2100 | assign tte_nfo = `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; | |
| 2101 | assign tte_ie = `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; | |
| 2102 | assign tte_cp = `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; | |
| 2103 | assign tte_e = `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; | |
| 2104 | assign tte_p = `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; | |
| 2105 | assign tte_w = `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; | |
| 2106 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 | |
| 2107 | ||
| 2108 | assign ready = `PARGS.tlb_sync_on & !`SPC5.tcu_spc_mbist_start; | |
| 2109 | ||
| 2110 | //---------------------------------------------------------- | |
| 2111 | initial begin // { | |
| 2112 | #1; | |
| 2113 | hwtw = 1'b0; | |
| 2114 | data_in_ready = 8'b0; | |
| 2115 | @ (posedge `SPC5.l2clk); | |
| 2116 | end // } | |
| 2117 | ||
| 2118 | //---------------------------------------------------------- | |
| 2119 | // Must use negedge to avoid race condition | |
| 2120 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments | |
| 2121 | ||
| 2122 | always @ (negedge (`SPC5.l2clk & ready)) begin // { | |
| 2123 | ||
| 2124 | tstamp = `TOP.core_cycle_cnt; | |
| 2125 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 2126 | ||
| 2127 | // Delay by 1 cycle to align with skip_demap | |
| 2128 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 2129 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 2130 | demap_1 <= demap; | |
| 2131 | ||
| 2132 | // Signal to nas_pipe to suppress SSTEP | |
| 2133 | if (asi_wr_itlb!=8'b0) begin // | |
| 2134 | for (i=0;i<=7;i=i+1) begin // { | |
| 2135 | if (asi_wr_itlb[i]) begin // | |
| 2136 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 2137 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 2138 | `NASTOP.sstep_sent[(mycid * 8) + i] <= 1'b1; // suppress SSTEP | |
| 2139 | end // } | |
| 2140 | end // } | |
| 2141 | end // } | |
| 2142 | ||
| 2143 | //---------------------------------------------------------- | |
| 2144 | // Send I/DTLBWRITE due to demap | |
| 2145 | // | |
| 2146 | ||
| 2147 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 2148 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2149 | "C%0d T%0d Illegal Back to Back ITLB demap", | |
| 2150 | mycid,demap_tid_1); | |
| 2151 | end // } | |
| 2152 | ||
| 2153 | if (demap_active) begin // { | |
| 2154 | fifo.pop_fifo ({hwtw,mytid}); | |
| 2155 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 2156 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 2157 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 2158 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 2159 | mycid,demap_tid_1,demap_tnum_1,tstamp); | |
| 2160 | junk = $sim_send(`PLI_ITLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 2161 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 2162 | ||
| 2163 | // Check to see if sstep was sent early | |
| 2164 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 2165 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 2166 | end //} | |
| 2167 | end //} | |
| 2168 | end //} | |
| 2169 | ||
| 2170 | //-------------------- | |
| 2171 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 2172 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 2173 | ||
| 2174 | if (demap_active) begin | |
| 2175 | case (demap_1) | |
| 2176 | 4'b0001: $write ("type=real "); | |
| 2177 | 4'b0010: $write ("type=cntx "); | |
| 2178 | 4'b0100: $write ("type=page "); | |
| 2179 | 4'b1000: $write ("type=all "); | |
| 2180 | default: | |
| 2181 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2182 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 2183 | endcase | |
| 2184 | end | |
| 2185 | else begin | |
| 2186 | $write("type=autodemap "); | |
| 2187 | end | |
| 2188 | ||
| 2189 | $display ("match=%h ts=%0d", | |
| 2190 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 2191 | ||
| 2192 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 2193 | if (tlb_match[cnt]==1'b1) begin // { | |
| 2194 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 2195 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 2196 | end // } | |
| 2197 | end // } | |
| 2198 | ||
| 2199 | end // } | |
| 2200 | ||
| 2201 | //---------------------------------------------------------- | |
| 2202 | // Send I/DHWTW due to HWTW | |
| 2203 | // Send I/DTLBWRITE due to ASI write | |
| 2204 | ||
| 2205 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 2206 | // These signals will be interleaved between the threads. | |
| 2207 | // Need to queue up the signals over time so they can be processed in order. | |
| 2208 | // Each thread will only be doing 1 thing at a time. | |
| 2209 | ||
| 2210 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { | |
| 2211 | ||
| 2212 | for (i=0;i<=7;i=i+1) begin // { | |
| 2213 | ||
| 2214 | if ((data_in[i])&&(tlb_wr[i])) begin // { | |
| 2215 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2216 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); | |
| 2217 | end // } | |
| 2218 | else begin // { | |
| 2219 | ||
| 2220 | // data_in[tid] determines if the write is HWTW or TLBWRITE | |
| 2221 | if (data_in[i]) begin // { | |
| 2222 | data_in_ready[i] <= 1'b1; | |
| 2223 | end // } | |
| 2224 | ||
| 2225 | // tlb_wr[tid] determines which thread will write next | |
| 2226 | // Use fifo to save the tids of the tlb_wr signals in order | |
| 2227 | if (tlb_wr[i]) begin // { | |
| 2228 | if (data_in_ready[i]) begin // { | |
| 2229 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 2230 | data_in_ready[i] <= 1'b0; | |
| 2231 | end // } | |
| 2232 | else begin // { | |
| 2233 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 2234 | end // } | |
| 2235 | end // } | |
| 2236 | ||
| 2237 | end // if} | |
| 2238 | end // for} | |
| 2239 | ||
| 2240 | end // if} | |
| 2241 | ||
| 2242 | //---------------------------------------------------------- | |
| 2243 | // wr_en means that the write is occurring | |
| 2244 | if (wr_en) begin // { | |
| 2245 | fifo.pop_fifo ({hwtw,mytid}); | |
| 2246 | mytnum = (mycid * 8) + mytid; | |
| 2247 | ||
| 2248 | if (hwtw) begin // { | |
| 2249 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 2250 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_IHWTW tid=%d ts=%0d va=%h entry=%h", | |
| 2251 | mycid,mytid,mytnum,tstamp,tte_va,entry); | |
| 2252 | junk = $sim_send(`PLI_IHWTW, mytnum, tstamp,tte_va,entry); | |
| 2253 | ||
| 2254 | end //} | |
| 2255 | end // } | |
| 2256 | else begin // { | |
| 2257 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 2258 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h", | |
| 2259 | mycid,mytid,mytnum,tstamp,entry); | |
| 2260 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 2261 | mycid,mytid,mytnum,tstamp); | |
| 2262 | junk = $sim_send(`PLI_ITLBWRITE, mytnum,tstamp,entry); | |
| 2263 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 2264 | ||
| 2265 | // Check to see if sstep was sent early | |
| 2266 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 2267 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 2268 | end //} | |
| 2269 | end //} | |
| 2270 | end // } | |
| 2271 | ||
| 2272 | //-------------------- | |
| 2273 | if (`PARGS.show_tlb_on) begin // { | |
| 2274 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 2275 | ||
| 2276 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 2277 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 2278 | ||
| 2279 | case (tte_page_mask) | |
| 2280 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 2281 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2282 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 2283 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2284 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 2285 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2286 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 2287 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2288 | endcase | |
| 2289 | ||
| 2290 | if (hwtw) $display (" (hwtw)"); | |
| 2291 | else $display (""); | |
| 2292 | ||
| 2293 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 2294 | ||
| 2295 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", | |
| 2296 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); | |
| 2297 | end // } | |
| 2298 | //-------------------- | |
| 2299 | ||
| 2300 | end // } | |
| 2301 | ||
| 2302 | end // always} | |
| 2303 | ||
| 2304 | //---------------------------------------------------------- | |
| 2305 | `endif | |
| 2306 | endmodule | |
| 2307 | ||
| 2308 | `endif | |
| 2309 | `ifdef CORE_6 | |
| 2310 | ||
| 2311 | module itlb_wr_c6 (); | |
| 2312 | `ifndef GATESIM | |
| 2313 | ||
| 2314 | `include "tlb_sync.vh" | |
| 2315 | `include "nas.vh" | |
| 2316 | parameter NUM_TLB=64; | |
| 2317 | ||
| 2318 | wire [7:0] data_in; | |
| 2319 | wire [7:0] tlb_wr; | |
| 2320 | wire wr_en; | |
| 2321 | wire [7:0] entry; | |
| 2322 | wire [3:0] demap; | |
| 2323 | reg [3:0] demap_1; | |
| 2324 | wire demap_page; | |
| 2325 | wire demap_context; | |
| 2326 | wire demap_real; | |
| 2327 | wire demap_all; | |
| 2328 | wire skip_demap; | |
| 2329 | wire demap_active; | |
| 2330 | wire auto_demap; | |
| 2331 | wire [2:0] demap_tid; | |
| 2332 | reg [2:0] demap_tid_1; | |
| 2333 | reg [5:0] demap_tnum_1; | |
| 2334 | wire [7:0] asi_wr_itlb; | |
| 2335 | wire [7:0] asi_wr_itlb_demap; | |
| 2336 | wire [7:0] asi_wr_itlb_data_in; | |
| 2337 | wire [7:0] asi_wr_itlb_data_access; | |
| 2338 | ||
| 2339 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 2340 | reg [7:0] data_in_ready; | |
| 2341 | reg hwtw; | |
| 2342 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 2343 | ||
| 2344 | reg [2:0] mytid; | |
| 2345 | reg [5:0] mytnum; | |
| 2346 | wire [2:0] mycid; | |
| 2347 | integer junk; | |
| 2348 | integer i; | |
| 2349 | reg [7:0] cnt; | |
| 2350 | wire ready; | |
| 2351 | ||
| 2352 | assign mycid = 6; | |
| 2353 | ||
| 2354 | //---------------------------------------------------------- | |
| 2355 | // Instantiate fifo - 1 entry per thread | |
| 2356 | fifo fifo (); | |
| 2357 | // Define fifo parameters | |
| 2358 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 2359 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 2360 | defparam fifo.PTR_BITS = 4; | |
| 2361 | ||
| 2362 | //---------------------------------------------------------- | |
| 2363 | // DUT probes | |
| 2364 | ||
| 2365 | assign data_in = `SPC6.mmu.asi.htc_wr_itlb_data_in; | |
| 2366 | assign tlb_wr = `PROBES6.itlb_wr; | |
| 2367 | assign wr_en = `SPC6.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; | |
| 2368 | ||
| 2369 | assign entry = `SPC6.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; | |
| 2370 | ||
| 2371 | assign demap_page = `SPC6.ifu_ftu.ftu_itc_ctl.itc_demap_page; | |
| 2372 | assign demap_context = `SPC6.ifu_ftu.itc_demap_context; | |
| 2373 | assign demap_real = `SPC6.ifu_ftu.itc_demap_real; | |
| 2374 | assign demap_all = `SPC6.ifu_ftu.itc_demap_all; | |
| 2375 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 2376 | assign skip_demap = `SPC6.ifu_ftu.itc_wr_u_en; | |
| 2377 | assign demap_tid = `SPC6.ifu_ftu.ftu_itd_dp.tte1[37:35]; | |
| 2378 | ||
| 2379 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 2380 | assign demap_active = |demap_1 && !skip_demap; | |
| 2381 | assign auto_demap = |demap_1 && skip_demap; | |
| 2382 | ||
| 2383 | ||
| 2384 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. | |
| 2385 | // Once these signals assert, the write to the TLB cannot be cancelled. | |
| 2386 | // These signals assert before the MMU reorders the TLB writes. | |
| 2387 | // Use these to suppress SSTEP in nas_pipe. | |
| 2388 | // Best case, these signals assert 1 cycle after the previous SSTEP. | |
| 2389 | assign asi_wr_itlb_demap = `SPC6.mmu.asi_wr_immu_demap; | |
| 2390 | assign asi_wr_itlb_data_in = `SPC6.mmu.asi_wr_itlb_data_in; | |
| 2391 | assign asi_wr_itlb_data_access = {`SPC6.mmu.asd1.asi_wr_itlb_data_access, | |
| 2392 | `SPC6.mmu.asd0.asi_wr_itlb_data_access}; | |
| 2393 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; | |
| 2394 | ||
| 2395 | //--------------------- | |
| 2396 | // Probes for debugging | |
| 2397 | ||
| 2398 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl | |
| 2399 | ||
| 2400 | // n2_tlb_tl_64x59_cam.sv | |
| 2401 | ||
| 2402 | `define CNTX1_HI 65 | |
| 2403 | `define CNTX1_LO 53 | |
| 2404 | `define PID_HI 52 | |
| 2405 | `define PID_LO 50 | |
| 2406 | `define REAL_BIT 49 | |
| 2407 | `define VA_47 48 | |
| 2408 | `define VA_28 29 | |
| 2409 | `define VA_27 28 | |
| 2410 | `define VA_22 23 | |
| 2411 | `define TTE_VALID 22 | |
| 2412 | `define VA_21 21 | |
| 2413 | `define VA_16 16 | |
| 2414 | `define VA_15 15 | |
| 2415 | `define VA_13 13 | |
| 2416 | `define CNTX0_HI 12 | |
| 2417 | `define CNTX0_LO 0 | |
| 2418 | ||
| 2419 | // n2_tlb_tl_64x59_ram.sv | |
| 2420 | ||
| 2421 | `define DATA_PARITY 36 | |
| 2422 | `define DATA_PA_39_28_HI 35 | |
| 2423 | `define DATA_PA_39_28_LO 24 | |
| 2424 | `define DATA_PA_27_22_HI 23 | |
| 2425 | `define DATA_PA_27_22_LO 18 | |
| 2426 | `define DATA_VA_27_22_V 17 | |
| 2427 | `define DATA_PA_21_16_HI 16 | |
| 2428 | `define DATA_PA_21_16_LO 11 | |
| 2429 | `define DATA_VA_21_16_V 10 | |
| 2430 | `define DATA_PA_15_13_HI 9 | |
| 2431 | `define DATA_PA_15_13_LO 7 | |
| 2432 | `define DATA_VA_15_13_V 6 | |
| 2433 | `define DATA_NFO 5 | |
| 2434 | `define DATA_IE 4 | |
| 2435 | `define DATA_CP 3 | |
| 2436 | `define DATA_X 2 | |
| 2437 | `define DATA_P 1 | |
| 2438 | `define DATA_W 0 | |
| 2439 | ||
| 2440 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 2441 | wire [(NUM_TLB-1):0] tlb_match; | |
| 2442 | wire tte_valid; | |
| 2443 | wire [47:0] tte_va; | |
| 2444 | wire [12:0] tte_context; | |
| 2445 | wire tte_real; | |
| 2446 | wire [2:0] tte_pid; | |
| 2447 | wire [2:0] tte_page_mask; | |
| 2448 | wire [39:0] tte_pa; | |
| 2449 | wire tte_nfo; | |
| 2450 | wire tte_ie; | |
| 2451 | wire tte_cp; | |
| 2452 | wire tte_e; | |
| 2453 | wire tte_p; | |
| 2454 | wire tte_w; | |
| 2455 | wire tte_ep; | |
| 2456 | ||
| 2457 | assign tlb_valid = `SPC6.ifu_ftu.ftu_itb_cust.array.cam.valid; | |
| 2458 | assign tlb_match = `SPC6.ifu_ftu.ftu_itb_cust.array.cam.match; | |
| 2459 | ||
| 2460 | assign tte_va = {`SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], | |
| 2461 | `SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], | |
| 2462 | `SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], | |
| 2463 | `SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], | |
| 2464 | 13'b0 | |
| 2465 | }; | |
| 2466 | assign tte_context = `SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 2467 | assign tte_pid = `SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 2468 | assign tte_real = `SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; | |
| 2469 | assign tte_valid = `SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; | |
| 2470 | ||
| 2471 | assign tte_page_mask = `SPC6.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; | |
| 2472 | ||
| 2473 | assign tte_pa = {`SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 2474 | `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 2475 | `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 2476 | `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 2477 | 13'b0 | |
| 2478 | }; | |
| 2479 | assign tte_nfo = `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; | |
| 2480 | assign tte_ie = `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; | |
| 2481 | assign tte_cp = `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; | |
| 2482 | assign tte_e = `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; | |
| 2483 | assign tte_p = `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; | |
| 2484 | assign tte_w = `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; | |
| 2485 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 | |
| 2486 | ||
| 2487 | assign ready = `PARGS.tlb_sync_on & !`SPC6.tcu_spc_mbist_start; | |
| 2488 | ||
| 2489 | //---------------------------------------------------------- | |
| 2490 | initial begin // { | |
| 2491 | #1; | |
| 2492 | hwtw = 1'b0; | |
| 2493 | data_in_ready = 8'b0; | |
| 2494 | @ (posedge `SPC6.l2clk); | |
| 2495 | end // } | |
| 2496 | ||
| 2497 | //---------------------------------------------------------- | |
| 2498 | // Must use negedge to avoid race condition | |
| 2499 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments | |
| 2500 | ||
| 2501 | always @ (negedge (`SPC6.l2clk & ready)) begin // { | |
| 2502 | ||
| 2503 | tstamp = `TOP.core_cycle_cnt; | |
| 2504 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 2505 | ||
| 2506 | // Delay by 1 cycle to align with skip_demap | |
| 2507 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 2508 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 2509 | demap_1 <= demap; | |
| 2510 | ||
| 2511 | // Signal to nas_pipe to suppress SSTEP | |
| 2512 | if (asi_wr_itlb!=8'b0) begin // | |
| 2513 | for (i=0;i<=7;i=i+1) begin // { | |
| 2514 | if (asi_wr_itlb[i]) begin // | |
| 2515 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 2516 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 2517 | `NASTOP.sstep_sent[(mycid * 8) + i] <= 1'b1; // suppress SSTEP | |
| 2518 | end // } | |
| 2519 | end // } | |
| 2520 | end // } | |
| 2521 | ||
| 2522 | //---------------------------------------------------------- | |
| 2523 | // Send I/DTLBWRITE due to demap | |
| 2524 | // | |
| 2525 | ||
| 2526 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 2527 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2528 | "C%0d T%0d Illegal Back to Back ITLB demap", | |
| 2529 | mycid,demap_tid_1); | |
| 2530 | end // } | |
| 2531 | ||
| 2532 | if (demap_active) begin // { | |
| 2533 | fifo.pop_fifo ({hwtw,mytid}); | |
| 2534 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 2535 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 2536 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 2537 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 2538 | mycid,demap_tid_1,demap_tnum_1,tstamp); | |
| 2539 | junk = $sim_send(`PLI_ITLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 2540 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 2541 | ||
| 2542 | // Check to see if sstep was sent early | |
| 2543 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 2544 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 2545 | end //} | |
| 2546 | end //} | |
| 2547 | end //} | |
| 2548 | ||
| 2549 | //-------------------- | |
| 2550 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 2551 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 2552 | ||
| 2553 | if (demap_active) begin | |
| 2554 | case (demap_1) | |
| 2555 | 4'b0001: $write ("type=real "); | |
| 2556 | 4'b0010: $write ("type=cntx "); | |
| 2557 | 4'b0100: $write ("type=page "); | |
| 2558 | 4'b1000: $write ("type=all "); | |
| 2559 | default: | |
| 2560 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2561 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 2562 | endcase | |
| 2563 | end | |
| 2564 | else begin | |
| 2565 | $write("type=autodemap "); | |
| 2566 | end | |
| 2567 | ||
| 2568 | $display ("match=%h ts=%0d", | |
| 2569 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 2570 | ||
| 2571 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 2572 | if (tlb_match[cnt]==1'b1) begin // { | |
| 2573 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 2574 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 2575 | end // } | |
| 2576 | end // } | |
| 2577 | ||
| 2578 | end // } | |
| 2579 | ||
| 2580 | //---------------------------------------------------------- | |
| 2581 | // Send I/DHWTW due to HWTW | |
| 2582 | // Send I/DTLBWRITE due to ASI write | |
| 2583 | ||
| 2584 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 2585 | // These signals will be interleaved between the threads. | |
| 2586 | // Need to queue up the signals over time so they can be processed in order. | |
| 2587 | // Each thread will only be doing 1 thing at a time. | |
| 2588 | ||
| 2589 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { | |
| 2590 | ||
| 2591 | for (i=0;i<=7;i=i+1) begin // { | |
| 2592 | ||
| 2593 | if ((data_in[i])&&(tlb_wr[i])) begin // { | |
| 2594 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2595 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); | |
| 2596 | end // } | |
| 2597 | else begin // { | |
| 2598 | ||
| 2599 | // data_in[tid] determines if the write is HWTW or TLBWRITE | |
| 2600 | if (data_in[i]) begin // { | |
| 2601 | data_in_ready[i] <= 1'b1; | |
| 2602 | end // } | |
| 2603 | ||
| 2604 | // tlb_wr[tid] determines which thread will write next | |
| 2605 | // Use fifo to save the tids of the tlb_wr signals in order | |
| 2606 | if (tlb_wr[i]) begin // { | |
| 2607 | if (data_in_ready[i]) begin // { | |
| 2608 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 2609 | data_in_ready[i] <= 1'b0; | |
| 2610 | end // } | |
| 2611 | else begin // { | |
| 2612 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 2613 | end // } | |
| 2614 | end // } | |
| 2615 | ||
| 2616 | end // if} | |
| 2617 | end // for} | |
| 2618 | ||
| 2619 | end // if} | |
| 2620 | ||
| 2621 | //---------------------------------------------------------- | |
| 2622 | // wr_en means that the write is occurring | |
| 2623 | if (wr_en) begin // { | |
| 2624 | fifo.pop_fifo ({hwtw,mytid}); | |
| 2625 | mytnum = (mycid * 8) + mytid; | |
| 2626 | ||
| 2627 | if (hwtw) begin // { | |
| 2628 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 2629 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_IHWTW tid=%d ts=%0d va=%h entry=%h", | |
| 2630 | mycid,mytid,mytnum,tstamp,tte_va,entry); | |
| 2631 | junk = $sim_send(`PLI_IHWTW, mytnum, tstamp,tte_va,entry); | |
| 2632 | ||
| 2633 | end //} | |
| 2634 | end // } | |
| 2635 | else begin // { | |
| 2636 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 2637 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h", | |
| 2638 | mycid,mytid,mytnum,tstamp,entry); | |
| 2639 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 2640 | mycid,mytid,mytnum,tstamp); | |
| 2641 | junk = $sim_send(`PLI_ITLBWRITE, mytnum,tstamp,entry); | |
| 2642 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 2643 | ||
| 2644 | // Check to see if sstep was sent early | |
| 2645 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 2646 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 2647 | end //} | |
| 2648 | end //} | |
| 2649 | end // } | |
| 2650 | ||
| 2651 | //-------------------- | |
| 2652 | if (`PARGS.show_tlb_on) begin // { | |
| 2653 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 2654 | ||
| 2655 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 2656 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 2657 | ||
| 2658 | case (tte_page_mask) | |
| 2659 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 2660 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2661 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 2662 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2663 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 2664 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2665 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 2666 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2667 | endcase | |
| 2668 | ||
| 2669 | if (hwtw) $display (" (hwtw)"); | |
| 2670 | else $display (""); | |
| 2671 | ||
| 2672 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 2673 | ||
| 2674 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", | |
| 2675 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); | |
| 2676 | end // } | |
| 2677 | //-------------------- | |
| 2678 | ||
| 2679 | end // } | |
| 2680 | ||
| 2681 | end // always} | |
| 2682 | ||
| 2683 | //---------------------------------------------------------- | |
| 2684 | `endif | |
| 2685 | endmodule | |
| 2686 | ||
| 2687 | `endif | |
| 2688 | `ifdef CORE_7 | |
| 2689 | ||
| 2690 | module itlb_wr_c7 (); | |
| 2691 | `ifndef GATESIM | |
| 2692 | ||
| 2693 | `include "tlb_sync.vh" | |
| 2694 | `include "nas.vh" | |
| 2695 | parameter NUM_TLB=64; | |
| 2696 | ||
| 2697 | wire [7:0] data_in; | |
| 2698 | wire [7:0] tlb_wr; | |
| 2699 | wire wr_en; | |
| 2700 | wire [7:0] entry; | |
| 2701 | wire [3:0] demap; | |
| 2702 | reg [3:0] demap_1; | |
| 2703 | wire demap_page; | |
| 2704 | wire demap_context; | |
| 2705 | wire demap_real; | |
| 2706 | wire demap_all; | |
| 2707 | wire skip_demap; | |
| 2708 | wire demap_active; | |
| 2709 | wire auto_demap; | |
| 2710 | wire [2:0] demap_tid; | |
| 2711 | reg [2:0] demap_tid_1; | |
| 2712 | reg [5:0] demap_tnum_1; | |
| 2713 | wire [7:0] asi_wr_itlb; | |
| 2714 | wire [7:0] asi_wr_itlb_demap; | |
| 2715 | wire [7:0] asi_wr_itlb_data_in; | |
| 2716 | wire [7:0] asi_wr_itlb_data_access; | |
| 2717 | ||
| 2718 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 2719 | reg [7:0] data_in_ready; | |
| 2720 | reg hwtw; | |
| 2721 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 2722 | ||
| 2723 | reg [2:0] mytid; | |
| 2724 | reg [5:0] mytnum; | |
| 2725 | wire [2:0] mycid; | |
| 2726 | integer junk; | |
| 2727 | integer i; | |
| 2728 | reg [7:0] cnt; | |
| 2729 | wire ready; | |
| 2730 | ||
| 2731 | assign mycid = 7; | |
| 2732 | ||
| 2733 | //---------------------------------------------------------- | |
| 2734 | // Instantiate fifo - 1 entry per thread | |
| 2735 | fifo fifo (); | |
| 2736 | // Define fifo parameters | |
| 2737 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 2738 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 2739 | defparam fifo.PTR_BITS = 4; | |
| 2740 | ||
| 2741 | //---------------------------------------------------------- | |
| 2742 | // DUT probes | |
| 2743 | ||
| 2744 | assign data_in = `SPC7.mmu.asi.htc_wr_itlb_data_in; | |
| 2745 | assign tlb_wr = `PROBES7.itlb_wr; | |
| 2746 | assign wr_en = `SPC7.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; | |
| 2747 | ||
| 2748 | assign entry = `SPC7.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; | |
| 2749 | ||
| 2750 | assign demap_page = `SPC7.ifu_ftu.ftu_itc_ctl.itc_demap_page; | |
| 2751 | assign demap_context = `SPC7.ifu_ftu.itc_demap_context; | |
| 2752 | assign demap_real = `SPC7.ifu_ftu.itc_demap_real; | |
| 2753 | assign demap_all = `SPC7.ifu_ftu.itc_demap_all; | |
| 2754 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 2755 | assign skip_demap = `SPC7.ifu_ftu.itc_wr_u_en; | |
| 2756 | assign demap_tid = `SPC7.ifu_ftu.ftu_itd_dp.tte1[37:35]; | |
| 2757 | ||
| 2758 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 2759 | assign demap_active = |demap_1 && !skip_demap; | |
| 2760 | assign auto_demap = |demap_1 && skip_demap; | |
| 2761 | ||
| 2762 | ||
| 2763 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. | |
| 2764 | // Once these signals assert, the write to the TLB cannot be cancelled. | |
| 2765 | // These signals assert before the MMU reorders the TLB writes. | |
| 2766 | // Use these to suppress SSTEP in nas_pipe. | |
| 2767 | // Best case, these signals assert 1 cycle after the previous SSTEP. | |
| 2768 | assign asi_wr_itlb_demap = `SPC7.mmu.asi_wr_immu_demap; | |
| 2769 | assign asi_wr_itlb_data_in = `SPC7.mmu.asi_wr_itlb_data_in; | |
| 2770 | assign asi_wr_itlb_data_access = {`SPC7.mmu.asd1.asi_wr_itlb_data_access, | |
| 2771 | `SPC7.mmu.asd0.asi_wr_itlb_data_access}; | |
| 2772 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; | |
| 2773 | ||
| 2774 | //--------------------- | |
| 2775 | // Probes for debugging | |
| 2776 | ||
| 2777 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl | |
| 2778 | ||
| 2779 | // n2_tlb_tl_64x59_cam.sv | |
| 2780 | ||
| 2781 | `define CNTX1_HI 65 | |
| 2782 | `define CNTX1_LO 53 | |
| 2783 | `define PID_HI 52 | |
| 2784 | `define PID_LO 50 | |
| 2785 | `define REAL_BIT 49 | |
| 2786 | `define VA_47 48 | |
| 2787 | `define VA_28 29 | |
| 2788 | `define VA_27 28 | |
| 2789 | `define VA_22 23 | |
| 2790 | `define TTE_VALID 22 | |
| 2791 | `define VA_21 21 | |
| 2792 | `define VA_16 16 | |
| 2793 | `define VA_15 15 | |
| 2794 | `define VA_13 13 | |
| 2795 | `define CNTX0_HI 12 | |
| 2796 | `define CNTX0_LO 0 | |
| 2797 | ||
| 2798 | // n2_tlb_tl_64x59_ram.sv | |
| 2799 | ||
| 2800 | `define DATA_PARITY 36 | |
| 2801 | `define DATA_PA_39_28_HI 35 | |
| 2802 | `define DATA_PA_39_28_LO 24 | |
| 2803 | `define DATA_PA_27_22_HI 23 | |
| 2804 | `define DATA_PA_27_22_LO 18 | |
| 2805 | `define DATA_VA_27_22_V 17 | |
| 2806 | `define DATA_PA_21_16_HI 16 | |
| 2807 | `define DATA_PA_21_16_LO 11 | |
| 2808 | `define DATA_VA_21_16_V 10 | |
| 2809 | `define DATA_PA_15_13_HI 9 | |
| 2810 | `define DATA_PA_15_13_LO 7 | |
| 2811 | `define DATA_VA_15_13_V 6 | |
| 2812 | `define DATA_NFO 5 | |
| 2813 | `define DATA_IE 4 | |
| 2814 | `define DATA_CP 3 | |
| 2815 | `define DATA_X 2 | |
| 2816 | `define DATA_P 1 | |
| 2817 | `define DATA_W 0 | |
| 2818 | ||
| 2819 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 2820 | wire [(NUM_TLB-1):0] tlb_match; | |
| 2821 | wire tte_valid; | |
| 2822 | wire [47:0] tte_va; | |
| 2823 | wire [12:0] tte_context; | |
| 2824 | wire tte_real; | |
| 2825 | wire [2:0] tte_pid; | |
| 2826 | wire [2:0] tte_page_mask; | |
| 2827 | wire [39:0] tte_pa; | |
| 2828 | wire tte_nfo; | |
| 2829 | wire tte_ie; | |
| 2830 | wire tte_cp; | |
| 2831 | wire tte_e; | |
| 2832 | wire tte_p; | |
| 2833 | wire tte_w; | |
| 2834 | wire tte_ep; | |
| 2835 | ||
| 2836 | assign tlb_valid = `SPC7.ifu_ftu.ftu_itb_cust.array.cam.valid; | |
| 2837 | assign tlb_match = `SPC7.ifu_ftu.ftu_itb_cust.array.cam.match; | |
| 2838 | ||
| 2839 | assign tte_va = {`SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], | |
| 2840 | `SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], | |
| 2841 | `SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], | |
| 2842 | `SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], | |
| 2843 | 13'b0 | |
| 2844 | }; | |
| 2845 | assign tte_context = `SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 2846 | assign tte_pid = `SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 2847 | assign tte_real = `SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; | |
| 2848 | assign tte_valid = `SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; | |
| 2849 | ||
| 2850 | assign tte_page_mask = `SPC7.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; | |
| 2851 | ||
| 2852 | assign tte_pa = {`SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 2853 | `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 2854 | `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 2855 | `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 2856 | 13'b0 | |
| 2857 | }; | |
| 2858 | assign tte_nfo = `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; | |
| 2859 | assign tte_ie = `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; | |
| 2860 | assign tte_cp = `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; | |
| 2861 | assign tte_e = `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; | |
| 2862 | assign tte_p = `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; | |
| 2863 | assign tte_w = `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; | |
| 2864 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 | |
| 2865 | ||
| 2866 | assign ready = `PARGS.tlb_sync_on & !`SPC7.tcu_spc_mbist_start; | |
| 2867 | ||
| 2868 | //---------------------------------------------------------- | |
| 2869 | initial begin // { | |
| 2870 | #1; | |
| 2871 | hwtw = 1'b0; | |
| 2872 | data_in_ready = 8'b0; | |
| 2873 | @ (posedge `SPC7.l2clk); | |
| 2874 | end // } | |
| 2875 | ||
| 2876 | //---------------------------------------------------------- | |
| 2877 | // Must use negedge to avoid race condition | |
| 2878 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments | |
| 2879 | ||
| 2880 | always @ (negedge (`SPC7.l2clk & ready)) begin // { | |
| 2881 | ||
| 2882 | tstamp = `TOP.core_cycle_cnt; | |
| 2883 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 2884 | ||
| 2885 | // Delay by 1 cycle to align with skip_demap | |
| 2886 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 2887 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 2888 | demap_1 <= demap; | |
| 2889 | ||
| 2890 | // Signal to nas_pipe to suppress SSTEP | |
| 2891 | if (asi_wr_itlb!=8'b0) begin // | |
| 2892 | for (i=0;i<=7;i=i+1) begin // { | |
| 2893 | if (asi_wr_itlb[i]) begin // | |
| 2894 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 2895 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 2896 | `NASTOP.sstep_sent[(mycid * 8) + i] <= 1'b1; // suppress SSTEP | |
| 2897 | end // } | |
| 2898 | end // } | |
| 2899 | end // } | |
| 2900 | ||
| 2901 | //---------------------------------------------------------- | |
| 2902 | // Send I/DTLBWRITE due to demap | |
| 2903 | // | |
| 2904 | ||
| 2905 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 2906 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2907 | "C%0d T%0d Illegal Back to Back ITLB demap", | |
| 2908 | mycid,demap_tid_1); | |
| 2909 | end // } | |
| 2910 | ||
| 2911 | if (demap_active) begin // { | |
| 2912 | fifo.pop_fifo ({hwtw,mytid}); | |
| 2913 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 2914 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 2915 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 2916 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 2917 | mycid,demap_tid_1,demap_tnum_1,tstamp); | |
| 2918 | junk = $sim_send(`PLI_ITLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 2919 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 2920 | ||
| 2921 | // Check to see if sstep was sent early | |
| 2922 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 2923 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 2924 | end //} | |
| 2925 | end //} | |
| 2926 | end //} | |
| 2927 | ||
| 2928 | //-------------------- | |
| 2929 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 2930 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 2931 | ||
| 2932 | if (demap_active) begin | |
| 2933 | case (demap_1) | |
| 2934 | 4'b0001: $write ("type=real "); | |
| 2935 | 4'b0010: $write ("type=cntx "); | |
| 2936 | 4'b0100: $write ("type=page "); | |
| 2937 | 4'b1000: $write ("type=all "); | |
| 2938 | default: | |
| 2939 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2940 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 2941 | endcase | |
| 2942 | end | |
| 2943 | else begin | |
| 2944 | $write("type=autodemap "); | |
| 2945 | end | |
| 2946 | ||
| 2947 | $display ("match=%h ts=%0d", | |
| 2948 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 2949 | ||
| 2950 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 2951 | if (tlb_match[cnt]==1'b1) begin // { | |
| 2952 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 2953 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 2954 | end // } | |
| 2955 | end // } | |
| 2956 | ||
| 2957 | end // } | |
| 2958 | ||
| 2959 | //---------------------------------------------------------- | |
| 2960 | // Send I/DHWTW due to HWTW | |
| 2961 | // Send I/DTLBWRITE due to ASI write | |
| 2962 | ||
| 2963 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 2964 | // These signals will be interleaved between the threads. | |
| 2965 | // Need to queue up the signals over time so they can be processed in order. | |
| 2966 | // Each thread will only be doing 1 thing at a time. | |
| 2967 | ||
| 2968 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { | |
| 2969 | ||
| 2970 | for (i=0;i<=7;i=i+1) begin // { | |
| 2971 | ||
| 2972 | if ((data_in[i])&&(tlb_wr[i])) begin // { | |
| 2973 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2974 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); | |
| 2975 | end // } | |
| 2976 | else begin // { | |
| 2977 | ||
| 2978 | // data_in[tid] determines if the write is HWTW or TLBWRITE | |
| 2979 | if (data_in[i]) begin // { | |
| 2980 | data_in_ready[i] <= 1'b1; | |
| 2981 | end // } | |
| 2982 | ||
| 2983 | // tlb_wr[tid] determines which thread will write next | |
| 2984 | // Use fifo to save the tids of the tlb_wr signals in order | |
| 2985 | if (tlb_wr[i]) begin // { | |
| 2986 | if (data_in_ready[i]) begin // { | |
| 2987 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 2988 | data_in_ready[i] <= 1'b0; | |
| 2989 | end // } | |
| 2990 | else begin // { | |
| 2991 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 2992 | end // } | |
| 2993 | end // } | |
| 2994 | ||
| 2995 | end // if} | |
| 2996 | end // for} | |
| 2997 | ||
| 2998 | end // if} | |
| 2999 | ||
| 3000 | //---------------------------------------------------------- | |
| 3001 | // wr_en means that the write is occurring | |
| 3002 | if (wr_en) begin // { | |
| 3003 | fifo.pop_fifo ({hwtw,mytid}); | |
| 3004 | mytnum = (mycid * 8) + mytid; | |
| 3005 | ||
| 3006 | if (hwtw) begin // { | |
| 3007 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 3008 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_IHWTW tid=%d ts=%0d va=%h entry=%h", | |
| 3009 | mycid,mytid,mytnum,tstamp,tte_va,entry); | |
| 3010 | junk = $sim_send(`PLI_IHWTW, mytnum, tstamp,tte_va,entry); | |
| 3011 | ||
| 3012 | end //} | |
| 3013 | end // } | |
| 3014 | else begin // { | |
| 3015 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 3016 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_ITLBWRITE tid=%d ts=%0d entry=%h", | |
| 3017 | mycid,mytid,mytnum,tstamp,entry); | |
| 3018 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 3019 | mycid,mytid,mytnum,tstamp); | |
| 3020 | junk = $sim_send(`PLI_ITLBWRITE, mytnum,tstamp,entry); | |
| 3021 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 3022 | ||
| 3023 | // Check to see if sstep was sent early | |
| 3024 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 3025 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 3026 | end //} | |
| 3027 | end //} | |
| 3028 | end // } | |
| 3029 | ||
| 3030 | //-------------------- | |
| 3031 | if (`PARGS.show_tlb_on) begin // { | |
| 3032 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 3033 | ||
| 3034 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 3035 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 3036 | ||
| 3037 | case (tte_page_mask) | |
| 3038 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 3039 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 3040 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 3041 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 3042 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 3043 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 3044 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 3045 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 3046 | endcase | |
| 3047 | ||
| 3048 | if (hwtw) $display (" (hwtw)"); | |
| 3049 | else $display (""); | |
| 3050 | ||
| 3051 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 3052 | ||
| 3053 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", | |
| 3054 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); | |
| 3055 | end // } | |
| 3056 | //-------------------- | |
| 3057 | ||
| 3058 | end // } | |
| 3059 | ||
| 3060 | end // always} | |
| 3061 | ||
| 3062 | //---------------------------------------------------------- | |
| 3063 | `endif | |
| 3064 | endmodule | |
| 3065 | ||
| 3066 | `endif | |
| 3067 | ||
| 3068 | //---------------------------------------------------------- | |
| 3069 | //---------------------------------------------------------- |