// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_common_ccc_pkt.v
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module dmu_common_ccc_pkt
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
parameter IDLE = 2'b00, // state machine states
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
input [`FIRE_CSR_DATA_BITS] cdp2pkt_data;
input [`FIRE_CSR_SRCB_BITS] cdp2pkt_src_bus;
input [`FIRE_CSR_ADDR_BITS] cdp2pkt_addr;
output [`FIRE_CSR_RING_BITS] csr_ring_out;
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
wire [`FIRE_CSR_RING_BITS] csr_ring_out, addr_phase;
wire [`FIRE_CSR_CMND_BITS] cmnd;
reg [`FIRE_CSR_RING_BITS] ring, nxt_ring;
reg [1:0] state, nxt_state;
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
assign csr_ring_out = ring;
always @ (state or fsm2pkt_valid) begin
if (fsm2pkt_valid) nxt_state = RDMS;
if (fsm2pkt_valid) nxt_state = BUSY;
always @ (state or fsm2pkt_valid or cdp2pkt_wr) begin
select = {cdp2pkt_wr, 1'b0};
select = {cdp2pkt_wr, cdp2pkt_wr};
assign cmnd = cdp2pkt_wr ? `FIRE_CSR_CMND_WREQ : `FIRE_CSR_CMND_RREQ;
assign addr_phase[`FIRE_CSR_RING_CMND_BITS] = cmnd;
assign addr_phase[`FIRE_CSR_RING_SRCB_BITS] = cdp2pkt_src_bus;
assign addr_phase[`FIRE_CSR_RING_ADDR_BITS] = cdp2pkt_addr;
always @ (select or addr_phase or cdp2pkt_data) begin
case (select) // synopsys infer_mux
2'b01 : nxt_ring = addr_phase;
2'b10 : nxt_ring = cdp2pkt_data[`FIRE_CSR_RDMS_BITS];
2'b11 : nxt_ring = cdp2pkt_data[`FIRE_CSR_RDLS_BITS];
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
always @ (posedge clk) begin
endmodule // dmu_common_ccc_pkt