projects / OpenSPARC-T2-SAM / blame
| Commit | Line | Data |
|---|---|---|
| 920dae64 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * Hypervisor Software File: offsets.h | |
| 5 | * | |
| 6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
| 7 | * | |
| 8 | * - Do no alter or remove copyright notices | |
| 9 | * | |
| 10 | * - Redistribution and use of this software in source and binary forms, with | |
| 11 | * or without modification, are permitted provided that the following | |
| 12 | * conditions are met: | |
| 13 | * | |
| 14 | * - Redistribution of source code must retain the above copyright notice, | |
| 15 | * this list of conditions and the following disclaimer. | |
| 16 | * | |
| 17 | * - Redistribution in binary form must reproduce the above copyright notice, | |
| 18 | * this list of conditions and the following disclaimer in the | |
| 19 | * documentation and/or other materials provided with the distribution. | |
| 20 | * | |
| 21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors | |
| 22 | * may be used to endorse or promote products derived from this software | |
| 23 | * without specific prior written permission. | |
| 24 | * | |
| 25 | * This software is provided "AS IS," without a warranty of any kind. | |
| 26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, | |
| 27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A | |
| 28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN | |
| 29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR | |
| 30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR | |
| 31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN | |
| 32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR | |
| 33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE | |
| 34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, | |
| 35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF | |
| 36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. | |
| 37 | * | |
| 38 | * You acknowledge that this software is not designed, licensed or | |
| 39 | * intended for use in the design, construction, operation or maintenance of | |
| 40 | * any nuclear facility. | |
| 41 | * | |
| 42 | * ========== Copyright Header End ============================================ | |
| 43 | */ | |
| 44 | #define NAMETABLE_SIZE 0x2e8 | |
| 45 | #define HDNAME_ROOT 0x0 | |
| 46 | #define HDNAME_FWD 0x8 | |
| 47 | #define HDNAME_BACK 0x10 | |
| 48 | #define HDNAME_ID 0x18 | |
| 49 | #define HDNAME_CPUS 0x20 | |
| 50 | #define HDNAME_CPU 0x28 | |
| 51 | #define HDNAME_DEVICES 0x30 | |
| 52 | #define HDNAME_DEVICE 0x38 | |
| 53 | #define HDNAME_SERVICES 0x40 | |
| 54 | #define HDNAME_SERVICE 0x48 | |
| 55 | #define HDNAME_GUESTS 0x50 | |
| 56 | #define HDNAME_GUEST 0x58 | |
| 57 | #define HDNAME_MAU 0x60 | |
| 58 | #define HDNAME_MAUS 0x68 | |
| 59 | #define HDNAME_CWQ 0x70 | |
| 60 | #define HDNAME_CWQS 0x78 | |
| 61 | #define HDNAME_ROMSIZE 0x80 | |
| 62 | #define HDNAME_ROMBASE 0x88 | |
| 63 | #define HDNAME_MEMORY 0x90 | |
| 64 | #define HDNAME_MBLOCK 0x98 | |
| 65 | #define HDNAME_UNBIND 0xa0 | |
| 66 | #define HDNAME_MDPA 0xa8 | |
| 67 | #define HDNAME_SIZE 0xb0 | |
| 68 | #define HDNAME_UARTBASE 0xb8 | |
| 69 | #define HDNAME_BASE 0xc0 | |
| 70 | #define HDNAME_LINK 0xc8 | |
| 71 | #define HDNAME_INOBITMAP 0xd0 | |
| 72 | #define HDNAME_TOD 0xd8 | |
| 73 | #define HDNAME_TODFREQUENCY 0xe0 | |
| 74 | #define HDNAME_TODOFFSET 0xe8 | |
| 75 | #define HDNAME_VID 0xf0 | |
| 76 | #define HDNAME_XID 0xf8 | |
| 77 | #define HDNAME_PID 0x100 | |
| 78 | #define HDNAME_SID 0x108 | |
| 79 | #define HDNAME_GID 0x110 | |
| 80 | #define HDNAME_STRANDID 0x118 | |
| 81 | #define HDNAME_PARTTAG 0x120 | |
| 82 | #define HDNAME_IGN 0x128 | |
| 83 | #define HDNAME_INO 0x130 | |
| 84 | #define HDNAME_MTU 0x138 | |
| 85 | #define HDNAME_MEMOFFSET 0x140 | |
| 86 | #define HDNAME_MEMSIZE 0x148 | |
| 87 | #define HDNAME_MEMBASE 0x150 | |
| 88 | #define HDNAME_REALBASE 0x158 | |
| 89 | #define HDNAME_HYPERVISOR 0x160 | |
| 90 | #define HDNAME_PERFCTRACCESS 0x168 | |
| 91 | #define HDNAME_PERFCTRHTACCESS 0x170 | |
| 92 | #define HDNAME_RNGCTLACCESSIBLE 0x178 | |
| 93 | #define HDNAME_VPCIDEVICE 0x180 | |
| 94 | #define HDNAME_PCIREGS 0x188 | |
| 95 | #define HDNAME_CFGHANDLE 0x190 | |
| 96 | #define HDNAME_CFGBASE 0x198 | |
| 97 | #define HDNAME_DISKPA 0x1a0 | |
| 98 | #define HDNAME_DIAGPRIV 0x1a8 | |
| 99 | #define HDNAME_DEBUGPRINTFLAGS 0x1b0 | |
| 100 | #define HDNAME_IOBASE 0x1b8 | |
| 101 | #define HDNAME_HVUART 0x1c0 | |
| 102 | #define HDNAME_FLAGS 0x1c8 | |
| 103 | #define HDNAME_STICKFREQUENCY 0x1d0 | |
| 104 | #define HDNAME_CEBLACKOUTSEC 0x1d8 | |
| 105 | #define HDNAME_CEPOLLSEC 0x1e0 | |
| 106 | #define HDNAME_MEMSCRUBMAX 0x1e8 | |
| 107 | #define HDNAME_ERPT_PA 0x1f0 | |
| 108 | #define HDNAME_ERPT_SIZE 0x1f8 | |
| 109 | #define HDNAME_VDEVS 0x200 | |
| 110 | #define HDNAME_RESET_REASON 0x208 | |
| 111 | #define HDNAME_LDC_ENDPOINTS 0x210 | |
| 112 | #define HDNAME_SP_LDC_ENDPOINTS 0x218 | |
| 113 | #define HDNAME_LDC_ENDPOINT 0x220 | |
| 114 | #define HDNAME_CHANNEL 0x228 | |
| 115 | #define HDNAME_TARGET_TYPE 0x230 | |
| 116 | #define HDNAME_TARGET_GUEST 0x238 | |
| 117 | #define HDNAME_TARGET_CHANNEL 0x240 | |
| 118 | #define HDNAME_TX_INO 0x248 | |
| 119 | #define HDNAME_RX_INO 0x250 | |
| 120 | #define HDNAME_SVC_ID 0x258 | |
| 121 | #define HDNAME_SVC_ARG 0x260 | |
| 122 | #define HDNAME_SVC_VINO 0x268 | |
| 123 | #define HDNAME_PRIVATE_SVC 0x270 | |
| 124 | #define HDNAME_LDC_MAPINRABASE 0x278 | |
| 125 | #define HDNAME_LDC_MAPINSIZE 0x280 | |
| 126 | #define HDNAME_IDX 0x288 | |
| 127 | #define HDNAME_RESOURCE_ID 0x290 | |
| 128 | #define HDNAME_CONSOLES 0x298 | |
| 129 | #define HDNAME_CONSOLE 0x2a0 | |
| 130 | #define HDNAME_VIRTUAL_DEVICES 0x2a8 | |
| 131 | #define HDNAME_CHANNEL_DEVICES 0x2b0 | |
| 132 | #define HDNAME_SYS_HWTW_MODE 0x2b8 | |
| 133 | #define HDNAME_PCIE_BUS 0x2c0 | |
| 134 | #define HDNAME_ALLOW_BYPASS 0x2c8 | |
| 135 | #define HDNAME_L2SCRUB_INTERVAL 0x2d0 | |
| 136 | #define HDNAME_L2SCRUB_ENTRIES 0x2d8 | |
| 137 | #define HDNAME_CONTENT_VERSION 0x2e0 | |
| 138 | #define CONFIG_SIZE 0x570 | |
| 139 | #define CONFIG_MEMBASE 0x0 | |
| 140 | #define CONFIG_MEMSIZE 0x8 | |
| 141 | #define CONFIG_ACTIVE_HVMD 0x10 | |
| 142 | #define CONFIG_PARSE_HVMD 0x18 | |
| 143 | #define CONFIG_RELOC 0x20 | |
| 144 | #define CONFIG_GUESTS 0x28 | |
| 145 | #define CONFIG_MBLOCKS 0x30 | |
| 146 | #define CONFIG_VCPUS 0x38 | |
| 147 | #define CONFIG_STRANDS 0x40 | |
| 148 | #define CONFIG_VSTATE 0x48 | |
| 149 | #define CONFIG_PCIE_BUSSES 0x50 | |
| 150 | #define CONFIG_HV_LDCS 0x58 | |
| 151 | #define CONFIG_SP_LDCS 0x60 | |
| 152 | #define CONFIG_SP_LDC_MAX_CID 0x68 | |
| 153 | #define CONFIG_DUMMYTSB 0x70 | |
| 154 | #define CONFIG_SINGLE_STRAND_LOCK 0x78 | |
| 155 | #define CONFIG_STRAND_STARTSET 0x80 | |
| 156 | #define CONFIG_STPRES 0x88 | |
| 157 | #define CONFIG_STACTIVE 0x90 | |
| 158 | #define CONFIG_STIDLE 0x98 | |
| 159 | #define CONFIG_STHALT 0xa0 | |
| 160 | #define CONFIG_PRINT_SPINLOCK 0xa8 | |
| 161 | #define CONFIG_HEARTBEAT_CPU 0xb0 | |
| 162 | #define CONFIG_ERROR_SVCH 0xb8 | |
| 163 | #define CONFIG_SVCS 0xc0 | |
| 164 | #define CONFIG_VINTR 0xc8 | |
| 165 | #define CONFIG_HVUART_ADDR 0xd0 | |
| 166 | #define CONFIG_TOD 0xd8 | |
| 167 | #define CONFIG_TODFREQUENCY 0xe0 | |
| 168 | #define CONFIG_STICKFREQUENCY 0xe8 | |
| 169 | #define CONFIG_SYS_HWTW_MODE 0xf0 | |
| 170 | #define CONFIG_ERPT_PA 0xf8 | |
| 171 | #define CONFIG_ERPT_SIZE 0x100 | |
| 172 | #define CONFIG_SRAM_ERPT_BUF_INUSE 0x108 | |
| 173 | #define CONFIG_DEVS_DTNODE 0x118 | |
| 174 | #define CONFIG_SVCS_DTNODE 0x120 | |
| 175 | #define CONFIG_GUESTS_DTNODE 0x128 | |
| 176 | #define CONFIG_CPUS_DTNODE 0x130 | |
| 177 | #define CONFIG_HV_LDCS_DTNODE 0x138 | |
| 178 | #define CONFIG_SP_LDCS_DTNODE 0x140 | |
| 179 | #define CONFIG_ERRORLOCK 0x148 | |
| 180 | #define CONFIG_HDNAMETABLE 0x150 | |
| 181 | #define CONFIG_INTRTGT 0x438 | |
| 182 | #define CONFIG_MEMSCRUB_MAX 0x440 | |
| 183 | #define CONFIG_DEVINSTANCES 0x448 | |
| 184 | #define CONFIG_CYCLIC_MAXD 0x450 | |
| 185 | #define CONFIG_HVCTL_STATE 0x458 | |
| 186 | #define CONFIG_HVCTL_HV_SEQ 0x45a | |
| 187 | #define CONFIG_HVCTL_ZEUS_SEQ 0x45c | |
| 188 | #define CONFIG_HVCTL_RAND_NUM 0x468 | |
| 189 | #define CONFIG_HVCTL_IBUF 0x470 | |
| 190 | #define CONFIG_HVCTL_IBUF_INCR 0x8 | |
| 191 | #define CONFIG_HVCTL_OBUF 0x4b0 | |
| 192 | #define CONFIG_HVCTL_OBUF_INCR 0x8 | |
| 193 | #define CONFIG_HVCTL_IP 0x4f0 | |
| 194 | #define CONFIG_HVCTL_LDC 0x4f8 | |
| 195 | #define CONFIG_HVCTL_LDC_LOCK 0x500 | |
| 196 | #define CONFIG_CE_BLACKOUT 0x508 | |
| 197 | #define CONFIG_CE_POLL_TIME 0x510 | |
| 198 | #define CONFIG_ERRS_TO_SEND 0x518 | |
| 199 | #define CONFIG_PHYSMEMSIZE 0x520 | |
| 200 | #define CONFIG_DEL_RECONF_GID 0x528 | |
| 201 | #define CONFIG_SCRUB_SYNC 0x538 | |
| 202 | #define CONFIG_FPGA_STATUS_LOCK 0x540 | |
| 203 | #define CONFIG_L2SCRUB_INTERVAL 0x548 | |
| 204 | #define CONFIG_L2SCRUB_ENTRIES 0x550 | |
| 205 | #define CONFIG_MCONFIG 0x558 | |
| 206 | #define MAU_SIZE 0xd0 | |
| 207 | #define MAU_PID 0x0 | |
| 208 | #define MAU_STATE 0x8 | |
| 209 | #define MAU_HANDLE 0x10 | |
| 210 | #define MAU_INO 0x18 | |
| 211 | #define MAU_STORE_IN_PROGR 0x20 | |
| 212 | #define MAU_ENABLE_CWQ 0x28 | |
| 213 | #define MAU_CPUSET 0x30 | |
| 214 | #define MAU_CPU_ACTIVE 0x38 | |
| 215 | #define MAU_CPU_ACTIVE_INCR 0x1 | |
| 216 | #define MAU_QUEUE 0x40 | |
| 217 | #define MAU_IHDLR 0x90 | |
| 218 | #define CWQ_SIZE 0x1140 | |
| 219 | #define CWQ_PID 0x0 | |
| 220 | #define CWQ_STATE 0x8 | |
| 221 | #define CWQ_HANDLE 0x10 | |
| 222 | #define CWQ_INO 0x18 | |
| 223 | #define CWQ_CPUSET 0x20 | |
| 224 | #define CWQ_CPU_ACTIVE 0x28 | |
| 225 | #define CWQ_CPU_ACTIVE_INCR 0x1 | |
| 226 | #define CWQ_IHDLR 0x30 | |
| 227 | #define CWQ_QUEUE 0x70 | |
| 228 | #define RNG_SIZE 0x40 | |
| 229 | #define RNG_LOCK 0x0 | |
| 230 | #define RNG_CTL 0x8 | |
| 231 | #define RWINDOW_SIZE 0x80 | |
| 232 | #define INS 0x0 | |
| 233 | #define INS_INCR 0x8 | |
| 234 | #define OUTS 0x40 | |
| 235 | #define OUTS_INCR 0x8 | |
| 236 | #define VCPUTRAPSTATE_SIZE 0x28 | |
| 237 | #define VCTS_TPC 0x0 | |
| 238 | #define VCTS_TNPC 0x8 | |
| 239 | #define VCTS_TSTATE 0x10 | |
| 240 | #define VCTS_TT 0x18 | |
| 241 | #define VCTS_HTSTATE 0x20 | |
| 242 | #define VCPU_GLOBALS_SIZE 0x38 | |
| 243 | #define VCPU_GLOBALS_G 0x0 | |
| 244 | #define VCPU_GLOBALS_G_INCR 0x8 | |
| 245 | #define VCPUSTATE_SIZE 0x670 | |
| 246 | #define VS_TL 0x0 | |
| 247 | #define VS_TRAPSTACK 0x8 | |
| 248 | #define VS_TRAPSTACK_INCR 0x28 | |
| 249 | #define VS_GL 0xf8 | |
| 250 | #define VS_GLOBALS 0x100 | |
| 251 | #define VS_GLOBALS_INCR 0x38 | |
| 252 | #define VS_TBA 0x1a8 | |
| 253 | #define VS_Y 0x1b0 | |
| 254 | #define VS_ASI 0x1b8 | |
| 255 | #define VS_SOFTINT 0x1c0 | |
| 256 | #define VS_PIL 0x1c8 | |
| 257 | #define VS_GSR 0x1d0 | |
| 258 | #define VS_TICK 0x1d8 | |
| 259 | #define VS_STICK 0x1e0 | |
| 260 | #define VS_STICKCOMPARE 0x1e8 | |
| 261 | #define VS_SCRATCHPAD 0x1f0 | |
| 262 | #define VS_SCRATCHPAD_INCR 0x8 | |
| 263 | #define VS_CWP 0x230 | |
| 264 | #define VS_WSTATE 0x238 | |
| 265 | #define VS_CANSAVE 0x240 | |
| 266 | #define VS_CANRESTORE 0x248 | |
| 267 | #define VS_OTHERWIN 0x250 | |
| 268 | #define VS_CLEANWIN 0x258 | |
| 269 | #define VS_WINS 0x260 | |
| 270 | #define VS_WINS_INCR 0x80 | |
| 271 | #define VS_CPU_MONDO_HEAD 0x660 | |
| 272 | #define VS_CPU_MONDO_TAIL 0x662 | |
| 273 | #define VS_DEV_MONDO_HEAD 0x664 | |
| 274 | #define VS_DEV_MONDO_TAIL 0x666 | |
| 275 | #define VS_ERROR_RESUMABLE_HEAD 0x668 | |
| 276 | #define VS_ERROR_RESUMABLE_TAIL 0x66a | |
| 277 | #define VS_ERROR_NONRESUMABLE_HEAD 0x66c | |
| 278 | #define VS_ERROR_NONRESUMABLE_TAIL 0x66e | |
| 279 | #define VCPU_SIZE 0x9f8 | |
| 280 | #define CPU_GUEST 0x0 | |
| 281 | #define CPU_ROOT 0x8 | |
| 282 | #define CPU_STRAND 0x10 | |
| 283 | #define CPU_RES_ID 0x18 | |
| 284 | #define CPU_STRAND_SLOT 0x1c | |
| 285 | #define CPU_VID 0x1d | |
| 286 | #define CPU_PARTTAG 0x1e | |
| 287 | #define CPU_SCR 0x20 | |
| 288 | #define CPU_SCR_INCR 0x8 | |
| 289 | #define CPU_STATUS 0x60 | |
| 290 | #define CPU_CMD_LASTPOKE 0x80 | |
| 291 | #define CPU_COMMAND 0x88 | |
| 292 | #define CPU_CMD_ARG0 0x90 | |
| 293 | #define CPU_CMD_ARG1 0x98 | |
| 294 | #define CPU_CMD_ARG2 0xa0 | |
| 295 | #define CPU_CMD_ARG3 0xa8 | |
| 296 | #define CPU_CMD_ARG4 0xb0 | |
| 297 | #define CPU_CMD_ARG5 0xb8 | |
| 298 | #define CPU_CMD_ARG6 0xc0 | |
| 299 | #define CPU_CMD_ARG7 0xc8 | |
| 300 | #define CPU_VINTR 0xd0 | |
| 301 | #define CPU_START_PC 0xd8 | |
| 302 | #define CPU_START_ARG 0xe0 | |
| 303 | #define CPU_RTBA 0xe8 | |
| 304 | #define CPU_MMU_AREA 0xf0 | |
| 305 | #define CPU_MMU_AREA_RA 0xf8 | |
| 306 | #define CPU_CPUQ_BASE 0x100 | |
| 307 | #define CPU_CPUQ_SIZE 0x108 | |
| 308 | #define CPU_CPUQ_MASK 0x110 | |
| 309 | #define CPU_CPUQ_BASE_RA 0x118 | |
| 310 | #define CPU_DEVQ_BASE 0x120 | |
| 311 | #define CPU_DEVQ_SIZE 0x128 | |
| 312 | #define CPU_DEVQ_MASK 0x130 | |
| 313 | #define CPU_DEVQ_BASE_RA 0x138 | |
| 314 | #define CPU_DEVQ_LOCK 0x140 | |
| 315 | #define CPU_DEVQ_SHDW_TAIL 0x148 | |
| 316 | #define CPU_ERRQNR_BASE 0x150 | |
| 317 | #define CPU_ERRQNR_SIZE 0x158 | |
| 318 | #define CPU_ERRQNR_MASK 0x160 | |
| 319 | #define CPU_ERRQNR_BASE_RA 0x168 | |
| 320 | #define CPU_ERRQR_BASE 0x170 | |
| 321 | #define CPU_ERRQR_SIZE 0x178 | |
| 322 | #define CPU_ERRQR_MASK 0x180 | |
| 323 | #define CPU_ERRQR_BASE_RA 0x188 | |
| 324 | #define CPU_TTRACE_OFFSET 0x190 | |
| 325 | #define CPU_TTRACEBUF_SIZE 0x198 | |
| 326 | #define CPU_TTRACEBUF_RA 0x1a0 | |
| 327 | #define CPU_TTRACEBUF_PA 0x1a8 | |
| 328 | #define CPU_NTSBS_CTX0 0x1b0 | |
| 329 | #define CPU_NTSBS_CTXN 0x1b8 | |
| 330 | #define CPU_TSBDS_CTX0 0x1c0 | |
| 331 | #define CPU_TSBDS_CTX0_INCR 0x1 | |
| 332 | #define CPU_TSBDS_CTXN 0x240 | |
| 333 | #define CPU_TSBDS_CTXN_INCR 0x1 | |
| 334 | #define CPU_MMUSTAT_AREA 0x2c0 | |
| 335 | #define CPU_MMUSTAT_AREA_RA 0x2c8 | |
| 336 | #define CPU_MAU 0x2d0 | |
| 337 | #define CPU_CWQ 0x2d8 | |
| 338 | #define CPU_RNG 0x2e0 | |
| 339 | #define CPU_SVCREGS 0x2e8 | |
| 340 | #define CPU_SVCREGS_INCR 0x8 | |
| 341 | #define CPU_LDC_INTR_PEND 0x318 | |
| 342 | #define CPU_LDC_ENDPOINT 0x320 | |
| 343 | #define CPU_STATE_SAVE_AREA 0x350 | |
| 344 | #define CPU_LAUNCH_WITH_RETRY 0x9c0 | |
| 345 | #define CPU_UTIL 0x9d0 | |
| 346 | #define CPU_SCR0 (CPU_SCR + (0 * CPU_SCR_INCR)) | |
| 347 | #define CPU_SCR1 (CPU_SCR + (1 * CPU_SCR_INCR)) | |
| 348 | #define CPU_SCR2 (CPU_SCR + (2 * CPU_SCR_INCR)) | |
| 349 | #define CPU_SCR3 (CPU_SCR + (3 * CPU_SCR_INCR)) | |
| 350 | #define VCPU_UTIL_SIZE 0x28 | |
| 351 | #define VCUTIL_STICK_LAST 0x0 | |
| 352 | #define VCUTIL_YIELD_COUNT 0x8 | |
| 353 | #define VCUTIL_YIELD_START 0x10 | |
| 354 | #define CPU_UTIL_STICK_LAST (CPU_UTIL + VCUTIL_STICK_LAST) | |
| 355 | #define CPU_UTIL_YIELD_COUNT (CPU_UTIL + VCUTIL_YIELD_COUNT) | |
| 356 | #define CPU_UTIL_YIELD_START (CPU_UTIL + VCUTIL_YIELD_START) | |
| 357 | #define SCHED_SLOT_SIZE 0x10 | |
| 358 | #define SCHED_SLOT_ACTION 0x0 | |
| 359 | #define SCHED_SLOT_ARG 0x8 | |
| 360 | #define HVCTL_HEADER_SIZE 0x8 | |
| 361 | #define HVCTL_HEADER_OP 0x0 | |
| 362 | #define HVCTL_MSG_SIZE 0x40 | |
| 363 | #define HVCTL_MSG_HDR 0x0 | |
| 364 | #define HVCTL_MSG_MSG 0x8 | |
| 365 | #define HVM_SCHED_SIZE 0x8 | |
| 366 | #define HVM_SCHED_VCPUP 0x0 | |
| 367 | #define HVM_SCRUB_SIZE 0x10 | |
| 368 | #define HVM_SCRUB_START_PA 0x0 | |
| 369 | #define HVM_SCRUB_START_LEN 0x8 | |
| 370 | #define HVM_GUESTCMD_SIZE 0x10 | |
| 371 | #define HVM_GUESTCMD_VCPUP 0x0 | |
| 372 | #define HVM_GUESTCMD_ARG 0x8 | |
| 373 | #define HVM_STOPGUEST_SIZE 0x8 | |
| 374 | #define HVM_STOPGUEST_GUESTP 0x0 | |
| 375 | #define HVM_SIZE 0x40 | |
| 376 | #define HVM_CMD 0x0 | |
| 377 | #define HVM_FROM_STRANDP 0x8 | |
| 378 | #define HVM_ARGS 0x10 | |
| 379 | #define XCALL_MBOX_SIZE 0x48 | |
| 380 | #define XCMB_COMMAND 0x0 | |
| 381 | #define XCMB_MONDOBUF 0x8 | |
| 382 | #define XCMB_MONDOBUF_INCR 0x8 | |
| 383 | #define MINI_STACK_SIZE 0x188 | |
| 384 | #define MINI_STACK_PTR 0x0 | |
| 385 | #define MINI_STACK_VAL 0x8 | |
| 386 | #define MINI_STACK_VAL_INCR 0x8 | |
| 387 | #define PCIE_DEVICE_SIZE 0x20 | |
| 388 | #define PCIE_DEVICE_GUESTP 0x8 | |
| 389 | #define STRAND_SIZE 0x10ad0 | |
| 390 | #define STRAND_ID 0x0 | |
| 391 | #define STRAND_CONFIGP 0x8 | |
| 392 | #define STRAND_CURRENT_SLOT 0x10 | |
| 393 | #define STRAND_SLOT 0x18 | |
| 394 | #define STRAND_SLOT_INCR 0x10 | |
| 395 | #define STRAND_XCALL_MBOX 0x38 | |
| 396 | #define STRAND_HV_TXMONDO 0x80 | |
| 397 | #define STRAND_HV_TXMONDO_INCR 0x8 | |
| 398 | #define STRAND_HV_RXMONDO 0xc0 | |
| 399 | #define STRAND_HV_RXMONDO_INCR 0x8 | |
| 400 | #define STRAND_SCRUB_BASEPA 0x100 | |
| 401 | #define STRAND_SCRUB_SIZE 0x108 | |
| 402 | #define STRAND_MINI_STACK 0x110 | |
| 403 | #define STRAND_SCR 0x298 | |
| 404 | #define STRAND_SCR_INCR 0x8 | |
| 405 | #define STRAND_CYCLIC 0x2d8 | |
| 406 | #define STRAND_UE_TMP1 0x520 | |
| 407 | #define STRAND_UE_TMP2 0x528 | |
| 408 | #define STRAND_UE_TMP3 0x530 | |
| 409 | #define STRAND_UE_GLOBALS 0x538 | |
| 410 | #define STRAND_UE_GLOBALS_INCR 0x40 | |
| 411 | #define STRAND_ERR_SEQ_NO 0x6b8 | |
| 412 | #define STRAND_ERR_FLAG 0x6c0 | |
| 413 | #define STRAND_DIAG_BUF 0x6c8 | |
| 414 | #define STRAND_DIAG_BUF_INCR 0x8 | |
| 415 | #define STRAND_SUN4V_RPRT_BUF 0x6f8 | |
| 416 | #define STRAND_SUN4V_RPRT_BUF_INCR 0x8 | |
| 417 | #define STRAND_ERR_TABLE_ENTRY 0x728 | |
| 418 | #define STRAND_ERR_TABLE_ENTRY_INCR 0x8 | |
| 419 | #define STRAND_ERR_ISFSR 0x758 | |
| 420 | #define STRAND_ERR_ISFSR_INCR 0x8 | |
| 421 | #define STRAND_ERR_DSFSR 0x788 | |
| 422 | #define STRAND_ERR_DSFSR_INCR 0x8 | |
| 423 | #define STRAND_ERR_DSFAR 0x7b8 | |
| 424 | #define STRAND_ERR_DSFAR_INCR 0x8 | |
| 425 | #define STRAND_ERR_DESR 0x7e8 | |
| 426 | #define STRAND_ERR_DESR_INCR 0x8 | |
| 427 | #define STRAND_ERR_DFESR 0x818 | |
| 428 | #define STRAND_ERR_DFESR_INCR 0x8 | |
| 429 | #define STRAND_ERR_RETURN_ADDR 0x848 | |
| 430 | #define STRAND_ERR_RETURN_ADDR_INCR 0x8 | |
| 431 | #define STRAND_IO_PROT 0x878 | |
| 432 | #define STRAND_IO_ERROR 0x880 | |
| 433 | #define STRAND_NRPENDING 0x888 | |
| 434 | #define STRAND_REROUTED_CPU 0x890 | |
| 435 | #define STRAND_REROUTED_EHDL 0x898 | |
| 436 | #define STRAND_REROUTED_ADDR 0x8a0 | |
| 437 | #define STRAND_REROUTED_STICK 0x8a8 | |
| 438 | #define STRAND_REROUTED_ATTR 0x8b0 | |
| 439 | #define STRAND_ABORT_PC 0x8b8 | |
| 440 | #define STRAND_ERR_GLOBALS_SAVED 0x8c0 | |
| 441 | #define STRAND_FAIL_TL 0x8d0 | |
| 442 | #define STRAND_FAIL_GL 0x8d8 | |
| 443 | #define STRAND_FAIL_TRAPSTATE 0x8e0 | |
| 444 | #define STRAND_FAIL_TRAPSTATE_INCR 0x28 | |
| 445 | #define STRAND_FAIL_TRAPGLOBALS 0x9d0 | |
| 446 | #define STRAND_FAIL_TRAPGLOBALS_INCR 0x40 | |
| 447 | #define STRAND_MRA 0xa90 | |
| 448 | #define STRAND_MRA_INCR 0x8 | |
| 449 | #define STRAND_STACK 0xad0 | |
| 450 | #define STRAND_STACK_INCR 0x8 | |
| 451 | #define STRAND_SCR0 (STRAND_SCR + (0 * STRAND_SCR_INCR)) | |
| 452 | #define STRAND_SCR1 (STRAND_SCR + (1 * STRAND_SCR_INCR)) | |
| 453 | #define STRAND_SCR2 (STRAND_SCR + (2 * STRAND_SCR_INCR)) | |
| 454 | #define STRAND_SCR3 (STRAND_SCR + (3 * STRAND_SCR_INCR)) | |
| 455 | #define STRAND_FP_TMP1 STRAND_UE_TMP1 | |
| 456 | #define STRAND_FP_TMP2 STRAND_UE_TMP2 | |
| 457 | #define STRAND_FP_TMP3 STRAND_UE_TMP3 | |
| 458 | #define STRAND_ERR_ESR_INCR STRAND_ERR_ISFSR_INCR | |
| 459 | #define CPU_SCR0 (CPU_SCR + (0 * CPU_SCR_INCR)) | |
| 460 | #define CPU_SCR1 (CPU_SCR + (1 * CPU_SCR_INCR)) | |
| 461 | #define CPU_SCR2 (CPU_SCR + (2 * CPU_SCR_INCR)) | |
| 462 | #define CPU_SCR3 (CPU_SCR + (3 * CPU_SCR_INCR)) | |
| 463 | #define ENDOFSTACK (STACK_VAL_INCR * (STACKDEPTH + 1)) | |
| 464 | #define TOP (CPU_STACK + STACK_TOP) | |
| 465 | #define MAPPING_SIZE 0x20 | |
| 466 | #define MAPPING_ENTRY_ALIGNED 0x0 | |
| 467 | #define MAPPING_ICPUSET 0x10 | |
| 468 | #define MAPPING_ICPUSET_INCR 0x8 | |
| 469 | #define MAPPING_DCPUSET 0x18 | |
| 470 | #define MAPPING_DCPUSET_INCR 0x8 | |
| 471 | #define MAP_ENTRY_ALIGNED_DATA 0x0 | |
| 472 | #define MAP_DATA_VA 0x0 | |
| 473 | #define MAP_DATA_TTE 0x8 | |
| 474 | #define MAPPING_VA (MAPPING_ENTRY_ALIGNED + MAP_ENTRY_ALIGNED_DATA + MAP_DATA_VA) | |
| 475 | #define MAPPING_TTE (MAPPING_ENTRY_ALIGNED + MAP_ENTRY_ALIGNED_DATA + MAP_DATA_TTE) | |
| 476 | #define STACK_SIZE 0x68 | |
| 477 | #define STACK_TOP 0x0 | |
| 478 | #define STACK_VAL 0x8 | |
| 479 | #define STACK_VAL_INCR 0x8 | |
| 480 | #define BANK_SHIFT 6 | |
| 481 | #define CPU_EVBSC_L2_AFSR(n) CPU_VBSC_ERPT + EVBSC_L2_AFSR + (n * EVBSC_L2_AFSR_INCR) | |
| 482 | #define CPU_EVBSC_L2_AFAR(n) CPU_VBSC_ERPT + EVBSC_L2_AFAR + (n * EVBSC_L2_AFAR_INCR) | |
| 483 | #define CPU_EVBSC_DRAM_AFSR(n) CPU_VBSC_ERPT + EVBSC_DRAM_AFSR + (n * EVBSC_DRAM_AFSR_INCR) | |
| 484 | #define CPU_EVBSC_DRAM_AFAR(n) CPU_VBSC_ERPT + EVBSC_DRAM_AFAR + (n * EVBSC_DRAM_AFAR_INCR) | |
| 485 | #define CPU_EVBSC_DRAM_CNTR(n) CPU_VBSC_ERPT + EVBSC_DRAM_CNTR + (n * EVBSC_DRAM_CNTR_INCR) | |
| 486 | #define CPU_EVBSC_DRAM_LOC(n) CPU_VBSC_ERPT + EVBSC_DRAM_LOC + (n * EVBSC_DRAM_LOC_INCR) | |
| 487 | #define CPU_EVBSC_DCACHE_DATA(n) DCACHE_DATA + (n * DCACHE_DATA_INCR) | |
| 488 | #define CPU_EVBSC_ICACHE_DIAG_DATA(n) DIAG_BUF_ICACHE + ICACHE_DIAG_DATA + (n * ICACHE_DIAG_DATA_INCR) | |
| 489 | #define EPKTSIZE 0x40 | |
| 490 | #define PCIERPT_SYSINO 0x0 | |
| 491 | #define PCIERPT_SUN4V_EHDL 0x8 | |
| 492 | #define PCIERPT_SUN4V_STICK 0x10 | |
| 493 | #define PCIERPT_SUN4V_DESC 0x18 | |
| 494 | #define PCIERPT_SUN4V_SPECFIC 0x1c | |
| 495 | #define PCIERPT_WORD4 0x20 | |
| 496 | #define PCIERPT_HDR1 0x28 | |
| 497 | #define PCIERPT_HDR2 0x30 | |
| 498 | #define DMU_ERR_SIZE 0xa0 | |
| 499 | #define DMU_ERR_REPORT_TYPE_62 0x0 | |
| 500 | #define DMU_ERR_FPGA_TOD 0x8 | |
| 501 | #define DMU_ERR_EHDL 0x10 | |
| 502 | #define DMU_ERR_STICK 0x18 | |
| 503 | #define DMU_ERR_CPUVER 0x20 | |
| 504 | #define DMU_ERR_AGENTID 0x28 | |
| 505 | #define DMU_ERR_MONDO_NUM 0x2c | |
| 506 | #define DMU_ERR_DMU_CORE_AND_BLOCK_ERR_STATUS 0x30 | |
| 507 | #define DMU_ERR_IMU_ERR_LOG_ENABLE 0x38 | |
| 508 | #define DMU_ERR_IMU_INTERRUPT_ENABLE 0x40 | |
| 509 | #define DMU_ERR_IMU_ENABLED_ERR_STATUS 0x48 | |
| 510 | #define DMU_ERR_IMU_ERR_STATUS_SET 0x50 | |
| 511 | #define DMU_ERR_IMU_SCS_ERR_LOG 0x58 | |
| 512 | #define DMU_ERR_IMU_EQS_ERR_LOG 0x60 | |
| 513 | #define DMU_ERR_IMU_RDS_ERR_LOG 0x68 | |
| 514 | #define DMU_ERR_MMU_ERR_LOG_ENABLE 0x70 | |
| 515 | #define DMU_ERR_MMU_INTR_ENABLE 0x78 | |
| 516 | #define DMU_ERR_MMU_INTR_STATUS 0x80 | |
| 517 | #define DMU_ERR_MMU_ERR_STATUS_SET 0x88 | |
| 518 | #define DMU_ERR_MMU_TRANSLATION_FAULT_ADDRESS 0x90 | |
| 519 | #define DMU_ERR_MMU_TRANSLATION_FAULT_STATUS 0x98 | |
| 520 | #define PEU_ERR_SIZE 0x120 | |
| 521 | #define PCIE_ERR_REPORT_TYPE_63 0x0 | |
| 522 | #define PEU_ERR_PEU_CORE_AND_BLOCK_INTR_ENABLE 0x30 | |
| 523 | #define PEU_ERR_PEU_CORE_AND_BLOCK_INTR_STATUS 0x38 | |
| 524 | #define PEU_ERR_ILU_ERR_LOG_ENABLE 0x40 | |
| 525 | #define PEU_ERR_ILU_INTR_ENABLE 0x48 | |
| 526 | #define PEU_ERR_ILU_INTR_STATUS 0x50 | |
| 527 | #define PEU_ERR_ILU_ERR_STATUS_SET 0x58 | |
| 528 | #define PEU_ERR_PEU_OTHER_EVENT_LOG_ENABLE 0x60 | |
| 529 | #define PEU_ERR_PEU_OTHER_EVENT_INTR_ENABLE 0x68 | |
| 530 | #define PEU_ERR_PEU_OTHER_EVENT_INTR_STATUS 0x70 | |
| 531 | #define PEU_ERR_PEU_OTHER_EVENT_STATUS_SET 0x78 | |
| 532 | #define PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER1_LOG 0x80 | |
| 533 | #define PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER2_LOG 0x88 | |
| 534 | #define PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER1_LOG 0x90 | |
| 535 | #define PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER2_LOG 0x98 | |
| 536 | #define PEU_ERR_PEU_UE_LOG_ENABLE 0xa0 | |
| 537 | #define PEU_ERR_PEU_UE_INTERRUPT_ENABLE 0xa8 | |
| 538 | #define PEU_ERR_PEU_UE_STATUS 0xb0 | |
| 539 | #define PEU_ERR_PEU_UE_STATUS_SET 0xb8 | |
| 540 | #define PEU_ERR_PEU_RECEIVE_UE_HEADER1_LOG 0xc0 | |
| 541 | #define PEU_ERR_PEU_RECEIVE_UE_HEADER2_LOG 0xc8 | |
| 542 | #define PEU_ERR_PEU_TRANSMIT_UE_HEADER1_LOG 0xd0 | |
| 543 | #define PEU_ERR_PEU_TRANSMIT_UE_HEADER2_LOG 0xd8 | |
| 544 | #define PEU_ERR_PEU_CE_LOG_ENABLE 0xe0 | |
| 545 | #define PEU_ERR_PEU_CE_INTERRUPT_ENABLE 0xe8 | |
| 546 | #define PEU_ERR_PEU_CE_INTERRUPT_STATUS 0xf0 | |
| 547 | #define PEU_ERR_PEU_CE_STATUS_SET 0xf8 | |
| 548 | #define PEU_ERR_PEU_CXPL_EVENT_ERROR_LOG_ENABLE 0x100 | |
| 549 | #define PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_ENABLE 0x108 | |
| 550 | #define PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_STATUS 0x110 | |
| 551 | #define PEU_ERR_PEU_CXPL_EVENT_ERROR_STATUS_SET 0x118 | |
| 552 | #define PCIERPT_SIZE 0x168 | |
| 553 | #define PCI_ERPT_PCIEPKT 0x0 | |
| 554 | #define PCI_ERPT_U 0x40 | |
| 555 | #define PCI_UNSENT_PKT 0x160 | |
| 556 | #define PCIERPT_REPORT_TYPE_62 (PCI_ERPT_U + DMU_ERR_REPORT_TYPE_62) | |
| 557 | #define PCIERPT_FPGA_TOD (PCI_ERPT_U + DMU_ERR_FPGA_TOD) | |
| 558 | #define PCIERPT_EHDL (PCI_ERPT_U + DMU_ERR_EHDL) | |
| 559 | #define PCIERPT_STICK (PCI_ERPT_U + DMU_ERR_STICK) | |
| 560 | #define PCIERPT_CPUVER (PCI_ERPT_U + DMU_ERR_CPUVER ) | |
| 561 | #define PCIERPT_AGENTID (PCI_ERPT_U + DMU_ERR_AGENTID) | |
| 562 | #define PCIERPT_MONDO_NUM (PCI_ERPT_U + DMU_ERR_MONDO_NUM) | |
| 563 | #define PCIERPT_DMU_CORE_AND_BLOCK_ERR_STATUS (PCI_ERPT_U + DMU_ERR_DMU_CORE_AND_BLOCK_ERR_STATUS) | |
| 564 | #define PCIERPT_IMU_ERR_LOG_ENABLE (PCI_ERPT_U + DMU_ERR_IMU_ERR_LOG_ENABLE) | |
| 565 | #define PCIERPT_IMU_INTERRUPT_ENABLE (PCI_ERPT_U + DMU_ERR_IMU_INTERRUPT_ENABLE) | |
| 566 | #define PCIERPT_IMU_ENABLED_ERR_STATUS (PCI_ERPT_U + DMU_ERR_IMU_ENABLED_ERR_STATUS) | |
| 567 | #define PCIERPT_IMU_ERR_STATUS_SET (PCI_ERPT_U + DMU_ERR_IMU_ERR_STATUS_SET) | |
| 568 | #define PCIERPT_IMU_SCS_ERR_LOG (PCI_ERPT_U + DMU_ERR_IMU_SCS_ERR_LOG) | |
| 569 | #define PCIERPT_IMU_EQS_ERR_LOG (PCI_ERPT_U + DMU_ERR_IMU_EQS_ERR_LOG) | |
| 570 | #define PCIERPT_IMU_RDS_ERR_LOG (PCI_ERPT_U + DMU_ERR_IMU_RDS_ERR_LOG) | |
| 571 | #define PCIERPT_MMU_ERR_LOG_ENABLE (PCI_ERPT_U + DMU_ERR_MMU_ERR_LOG_ENABLE) | |
| 572 | #define PCIERPT_MMU_INTR_ENABLE (PCI_ERPT_U + DMU_ERR_MMU_INTR_ENABLE) | |
| 573 | #define PCIERPT_MMU_INTR_STATUS (PCI_ERPT_U + DMU_ERR_MMU_INTR_STATUS) | |
| 574 | #define PCIERPT_MMU_ERR_STATUS_SET (PCI_ERPT_U + DMU_ERR_MMU_ERR_STATUS_SET) | |
| 575 | #define PCIERPT_MMU_TRANSLATION_FAULT_ADDRESS (PCI_ERPT_U + DMU_ERR_MMU_TRANSLATION_FAULT_ADDRESS) | |
| 576 | #define PCIERPT_MMU_TRANSLATION_FAULT_STATUS (PCI_ERPT_U + DMU_ERR_MMU_TRANSLATION_FAULT_STATUS) | |
| 577 | #define PCIERPT_REPORT_TYPE_63 (PCI_ERPT_U + PCIE_ERR_REPORT_TYPE_63) | |
| 578 | #define PCIERPT_PEU_CORE_AND_BLOCK_INTR_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CORE_AND_BLOCK_INTR_ENABLE) | |
| 579 | #define PCIERPT_PEU_CORE_AND_BLOCK_INTR_STATUS (PCI_ERPT_U + PEU_ERR_PEU_CORE_AND_BLOCK_INTR_STATUS) | |
| 580 | #define PCIERPT_ILU_ERR_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_ILU_ERR_LOG_ENABLE) | |
| 581 | #define PCIERPT_ILU_INTR_ENABLE (PCI_ERPT_U + PEU_ERR_ILU_INTR_ENABLE) | |
| 582 | #define PCIERPT_ILU_INTR_STATUS (PCI_ERPT_U + PEU_ERR_ILU_INTR_STATUS) | |
| 583 | #define PCIERPT_ILU_ERR_STATUS_SET (PCI_ERPT_U + PEU_ERR_ILU_ERR_STATUS_SET) | |
| 584 | #define PCIERPT_PEU_OTHER_EVENT_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_LOG_ENABLE) | |
| 585 | #define PCIERPT_PEU_OTHER_EVENT_INTR_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_INTR_ENABLE) | |
| 586 | #define PCIERPT_PEU_OTHER_EVENT_INTR_STATUS (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_INTR_STATUS) | |
| 587 | #define PCIERPT_PEU_OTHER_EVENT_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_STATUS_SET) | |
| 588 | #define PCIERPT_PEU_RECEIVE_OTHER_EVENT_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER1_LOG) | |
| 589 | #define PCIERPT_PEU_RECEIVE_OTHER_EVENT_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER2_LOG) | |
| 590 | #define PCIERPT_PEU_TRANSMIT_OTHER_EVENT_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER1_LOG) | |
| 591 | #define PCIERPT_PEU_TRANSMIT_OTHER_EVENT_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER2_LOG) | |
| 592 | #define PCIERPT_PEU_UE_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_UE_LOG_ENABLE) | |
| 593 | #define PCIERPT_PEU_UE_INTERRUPT_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_UE_INTERRUPT_ENABLE) | |
| 594 | #define PCIERPT_PEU_UE_STATUS (PCI_ERPT_U + PEU_ERR_PEU_UE_STATUS) | |
| 595 | #define PCIERPT_PEU_UE_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_UE_STATUS_SET) | |
| 596 | #define PCIERPT_PEU_RECEIVE_UE_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_UE_HEADER1_LOG) | |
| 597 | #define PCIERPT_PEU_RECEIVE_UE_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_UE_HEADER2_LOG) | |
| 598 | #define PCIERPT_PEU_TRANSMIT_UE_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_UE_HEADER1_LOG) | |
| 599 | #define PCIERPT_PEU_TRANSMIT_UE_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_UE_HEADER2_LOG) | |
| 600 | #define PCIERPT_PEU_CE_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CE_LOG_ENABLE) | |
| 601 | #define PCIERPT_PEU_CE_INTERRUPT_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CE_INTERRUPT_ENABLE) | |
| 602 | #define PCIERPT_PEU_CE_INTERRUPT_STATUS (PCI_ERPT_U + PEU_ERR_PEU_CE_INTERRUPT_STATUS) | |
| 603 | #define PCIERPT_PEU_CE_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_CE_STATUS_SET) | |
| 604 | #define PCIERPT_PEU_CXPL_EVENT_ERROR_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_LOG_ENABLE) | |
| 605 | #define PCIERPT_PEU_CXPL_EVENT_ERROR_INT_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_ENABLE) | |
| 606 | #define PCIERPT_PEU_CXPL_EVENT_ERROR_INT_STATUS (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_STATUS) | |
| 607 | #define PCIERPT_PEU_CXPL_EVENT_ERROR_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_STATUS_SET) | |
| 608 | #define LDC_CONSPKT_SIZE 0x40 | |
| 609 | #define LDC_CONS_TYPE 0x0 | |
| 610 | #define LDC_CONS_SIZE 0x1 | |
| 611 | #define LDC_CONS_CTRL_MSG 0x4 | |
| 612 | #define LDC_CONS_PAYLOAD 0x8 | |
| 613 | #define LDC_CONS_PAYLOAD_INCR 0x1 | |
| 614 | #define CONSOLE_SIZE 0x248 | |
| 615 | #define CONS_TYPE 0x0 | |
| 616 | #define CONS_UARTBASE 0x18 | |
| 617 | #define CONS_STATUS 0x20 | |
| 618 | #define CONS_ENDPT 0x28 | |
| 619 | #define CONS_INHEAD 0x30 | |
| 620 | #define CONS_INTAIL 0x38 | |
| 621 | #define CONS_VINTR_MAPREG 0x40 | |
| 622 | #define CONS_INBUF 0x48 | |
| 623 | #define CONS_INBUF_INCR 0x8 | |
| 624 | #define HVDISK_SIZE 0x10 | |
| 625 | #define DISK_PA 0x0 | |
| 626 | #define DISK_SIZE 0x8 | |
| 627 | #define LDC_ENDPOINT_SIZE 0x110 | |
| 628 | #define LDC_IS_LIVE 0x1 | |
| 629 | #define LDC_IS_PRIVATE 0x2 | |
| 630 | #define LDC_IS_SVC_ID 0x3 | |
| 631 | #define LDC_RX_UPDATED 0x4 | |
| 632 | #define LDC_TXQ_FULL 0x5 | |
| 633 | #define LDC_TX_QBASE_RA 0x8 | |
| 634 | #define LDC_TX_QBASE_PA 0x10 | |
| 635 | #define LDC_TX_QSIZE 0x18 | |
| 636 | #define LDC_TX_QHEAD 0x20 | |
| 637 | #define LDC_TX_QTAIL 0x24 | |
| 638 | #define LDC_TX_CB 0x28 | |
| 639 | #define LDC_TX_CBARG 0x30 | |
| 640 | #define LDC_TX_MAPREG 0x38 | |
| 641 | #define LDC_RX_QBASE_RA 0x60 | |
| 642 | #define LDC_RX_QBASE_PA 0x68 | |
| 643 | #define LDC_RX_QSIZE 0x70 | |
| 644 | #define LDC_RX_QHEAD 0x78 | |
| 645 | #define LDC_RX_QTAIL 0x7c | |
| 646 | #define LDC_RX_CB 0x80 | |
| 647 | #define LDC_RX_CBARG 0x88 | |
| 648 | #define LDC_RX_MAPREG 0x90 | |
| 649 | #define LDC_RX_VINTR_COOKIE 0xb8 | |
| 650 | #define LDC_TARGET_TYPE 0xc0 | |
| 651 | #define LDC_TARGET_GUEST 0xc8 | |
| 652 | #define LDC_TARGET_CHANNEL 0xd0 | |
| 653 | #define LDC_MAP_TABLE_RA 0xd8 | |
| 654 | #define LDC_MAP_TABLE_PA 0xe0 | |
| 655 | #define LDC_MAP_TABLE_NENTRIES 0xe8 | |
| 656 | #define LDC_MAP_TABLE_SZ 0xf0 | |
| 657 | #define VERSION_SIZE 0x10 | |
| 658 | #define VERSION_NUM 0x0 | |
| 659 | #define VERSION_PTR 0x8 | |
| 660 | #define VERSION_MAJOR (VERSION_NUM+MAJOR_OFF) | |
| 661 | #define VERSION_MINOR (VERSION_NUM+MINOR_OFF) | |
| 662 | #define LDC_MAPREG_SIZE 0x28 | |
| 663 | #define LDC_MAPREG_STATE 0x0 | |
| 664 | #define LDC_MAPREG_VALID 0x4 | |
| 665 | #define LDC_MAPREG_INO 0x8 | |
| 666 | #define LDC_MAPREG_CPUP 0x10 | |
| 667 | #define LDC_MAPREG_COOKIE 0x18 | |
| 668 | #define LDC_MAPREG_ENDPOINT 0x20 | |
| 669 | #define WATCHDOG_TICKS 0x0 | |
| 670 | #define LDC_I2E_SIZE 0x10 | |
| 671 | #define LDC_I2E_ENDPOINT 0x0 | |
| 672 | #define LDC_I2E_MAPREG 0x8 | |
| 673 | #define SP_LDC_ENDPOINT_SIZE 0xe8 | |
| 674 | #define LDC_CHANNEL_IDX 0x0 | |
| 675 | #define SP_LDC_IS_LIVE 0x1 | |
| 676 | #define SP_LDC_TARGET_TYPE 0x2 | |
| 677 | #define SP_LDC_TX_QD_PA 0x8 | |
| 678 | #define SP_LDC_RX_QD_PA 0x10 | |
| 679 | #define SP_LDC_TARGET_GUEST 0x18 | |
| 680 | #define SP_LDC_TARGET_CHANNEL 0x20 | |
| 681 | #define SP_LDC_TX_LOCK 0x28 | |
| 682 | #define SP_LDC_RX_LOCK 0x30 | |
| 683 | #define SP_LDC_TX_SCR_TXHEAD 0x38 | |
| 684 | #define SP_LDC_TX_SCR_TXTAIL 0x3c | |
| 685 | #define SP_LDC_TX_SCR_TXSIZE 0x40 | |
| 686 | #define SP_LDC_TX_SCR_TX_QPA 0x48 | |
| 687 | #define SP_LDC_TX_SCR_RXHEAD 0x50 | |
| 688 | #define SP_LDC_TX_SCR_RXTAIL 0x54 | |
| 689 | #define SP_LDC_TX_SCR_RXSIZE 0x58 | |
| 690 | #define SP_LDC_TX_SCR_RX_QPA 0x60 | |
| 691 | #define SP_LDC_TX_SCR_TARGET 0x68 | |
| 692 | #define SP_LDC_RX_SCR_TXHEAD 0x70 | |
| 693 | #define SP_LDC_RX_SCR_TXTAIL 0x74 | |
| 694 | #define SP_LDC_RX_SCR_TXSIZE 0x78 | |
| 695 | #define SP_LDC_RX_SCR_TX_QPA 0x80 | |
| 696 | #define SP_LDC_RX_SCR_RXHEAD 0x88 | |
| 697 | #define SP_LDC_RX_SCR_RXTAIL 0x8c | |
| 698 | #define SP_LDC_RX_SCR_RXSIZE 0x90 | |
| 699 | #define SP_LDC_RX_SCR_RX_QPA 0x98 | |
| 700 | #define SP_LDC_RX_SCR_TARGET 0xa0 | |
| 701 | #define SP_LDC_RX_SCR_PKT 0xa8 | |
| 702 | #define SRAM_LDC_QENTRY_SIZE 0x40 | |
| 703 | #define SRAM_LDC_PKT_DATA 0x0 | |
| 704 | #define SRAM_LDC_PKT_DATA_INCR 0x8 | |
| 705 | #define SRAM_LDC_QD_SIZE 0x140 | |
| 706 | #define SRAM_LDC_HEAD 0x100 | |
| 707 | #define SRAM_LDC_TAIL 0x101 | |
| 708 | #define SRAM_LDC_STATE 0x102 | |
| 709 | #define SRAM_LDC_STATE_UPDATED 0x103 | |
| 710 | #define SRAM_LDC_STATE_NOTIFY 0x104 | |
| 711 | #define LDC_MAPIN_SIZE 0x30 | |
| 712 | #define LDC_MI_PA 0x0 | |
| 713 | #define LDC_MI_MMU_MAP 0x8 | |
| 714 | #define LDC_MI_IO_VA 0x10 | |
| 715 | #define LDC_MI_VA 0x18 | |
| 716 | #define LDC_MI_VA_CTX 0x20 | |
| 717 | #define LDC_MI_LOCAL_ENDPOINT 0x22 | |
| 718 | #define LDC_MI_PG_SIZE 0x24 | |
| 719 | #define LDC_MI_PERMS 0x25 | |
| 720 | #define LDC_MI_MAP_TABLE_IDX 0x28 | |
| 721 | #define LDC_MI_NEXT_IDX 0 /* clobber 1st word when free */ | |
| 722 | #define MIE_VA_MMU_SHIFT 0 | |
| 723 | #define MIE_RA_MMU_SHIFT 8 | |
| 724 | #define MIE_IO_MMU_SHIFT 16 | |
| 725 | #define LDC_MI_VA_MMU_MAP (LDC_MI_MMU_MAP + 7) | |
| 726 | #define LDC_MI_RA_MMU_MAP (LDC_MI_MMU_MAP + 6) | |
| 727 | #define LDC_MI_IO_MMU_MAP (LDC_MI_MMU_MAP + 5) | |
| 728 | #define GUEST_CONS_QUEUES_SIZE 0x4000 | |
| 729 | #define GUEST_CONS_RXQ 0x0 | |
| 730 | #define GUEST_CONS_RXQ_INCR 0x1 | |
| 731 | #define GUEST_CONS_TXQ 0x2000 | |
| 732 | #define GUEST_CONS_TXQ_INCR 0x1 | |
| 733 | #define RA2PA_SEGMENT_SIZE 0x20 | |
| 734 | #define RA2PA_SEGMENT_BASE 0x0 | |
| 735 | #define RA2PA_SEGMENT_LIMIT 0x8 | |
| 736 | #define RA2PA_SEGMENT_OFFSET 0x10 | |
| 737 | #define RA2PA_SEGMENT_FLAGS 0x18 | |
| 738 | #define GUEST_SIZE 0x45910 | |
| 739 | #define GUEST_GID 0x0 | |
| 740 | #define GUEST_CONFIGP 0x8 | |
| 741 | #define GUEST_STATE 0x10 | |
| 742 | #define GUEST_STATE_LOCK 0x18 | |
| 743 | #define GUEST_SOFT_STATE 0x20 | |
| 744 | #define GUEST_SOFT_STATE_STR 0x21 | |
| 745 | #define GUEST_SOFT_STATE_STR_INCR 0x1 | |
| 746 | #define GUEST_SOFT_STATE_LOCK 0x48 | |
| 747 | #define GUEST_REAL_BASE 0x50 | |
| 748 | #define GUEST_REAL_LIMIT 0x58 | |
| 749 | #define GUEST_MEM_OFFSET 0x60 | |
| 750 | #define GUEST_RA2PA_SEGMENT 0x68 | |
| 751 | #define GUEST_RA2PA_SEGMENT_INCR 0x20 | |
| 752 | #define GUEST_LDC_MAPIN_BASERA 0x868 | |
| 753 | #define GUEST_LDC_MAPIN_SIZE 0x870 | |
| 754 | #define GUEST_PERM_MAPPINGS_LOCK 0x878 | |
| 755 | #define GUEST_PERM_MAPPINGS 0x880 | |
| 756 | #define GUEST_PERM_MAPPINGS_INCR 0x20 | |
| 757 | #define GUEST_CONSOLE 0x980 | |
| 758 | #define GUEST_TOD_OFFSET 0xbc8 | |
| 759 | #define GUEST_TTRACE_FRZ 0xbd0 | |
| 760 | #define GUEST_VCPUS 0xbd8 | |
| 761 | #define GUEST_VCPUS_INCR 0x8 | |
| 762 | #define GUEST_MAUS 0xdd8 | |
| 763 | #define GUEST_MAUS_INCR 0x8 | |
| 764 | #define GUEST_CWQS 0xe18 | |
| 765 | #define GUEST_CWQS_INCR 0x8 | |
| 766 | #define GUEST_API_GROUPS 0xe58 | |
| 767 | #define GUEST_API_GROUPS_INCR 0x10 | |
| 768 | #define GUEST_HCALL_TABLE 0xf28 | |
| 769 | #define GUEST_DEV2INST 0xf30 | |
| 770 | #define GUEST_DEV2INST_INCR 0x1 | |
| 771 | #define GUEST_VINO2INST 0xf50 | |
| 772 | #define GUEST_VDEV_STATE 0x1750 | |
| 773 | #define GUEST_MD_PA 0x2760 | |
| 774 | #define GUEST_MD_SIZE 0x2768 | |
| 775 | #define GUEST_DUMPBUF_PA 0x2770 | |
| 776 | #define GUEST_DUMPBUF_RA 0x2778 | |
| 777 | #define GUEST_DUMPBUF_SIZE 0x2780 | |
| 778 | #define GUEST_ENTRY 0x2788 | |
| 779 | #define GUEST_ROM_BASE 0x2790 | |
| 780 | #define GUEST_ROM_SIZE 0x2798 | |
| 781 | #define GUEST_PERFREG_ACCESSIBLE 0x27a0 | |
| 782 | #define GUEST_DIAGPRIV 0x27a8 | |
| 783 | #define GUEST_RESET_REASON 0x27b0 | |
| 784 | #define GUEST_PERFREGHT_ACCESSIBLE 0x27b8 | |
| 785 | #define GUEST_RNG_CTL_ACCESSIBLE 0x27c0 | |
| 786 | #define GUEST_WATCHDOG 0x27c8 | |
| 787 | #define GUEST_DISK 0x27d0 | |
| 788 | #define GUEST_LDC_MAX_CHANNEL_IDX 0x27e0 | |
| 789 | #define GUEST_LDC_MAPIN_FREE_IDX 0x27e8 | |
| 790 | #define GUEST_LDC_ENDPOINT 0x27f0 | |
| 791 | #define GUEST_LDC_ENDPOINT_INCR 0x110 | |
| 792 | #define GUEST_LDC_MAPIN 0x137f0 | |
| 793 | #define GUEST_LDC_MAPIN_INCR 0x30 | |
| 794 | #define GUEST_LDC_I2E 0x437f0 | |
| 795 | #define GUEST_LDC_I2E_INCR 0x10 | |
| 796 | #define GUEST_ASYNC_BUSY 0x45878 | |
| 797 | #define GUEST_ASYNC_BUSY_INCR 0x1 | |
| 798 | #define GUEST_ASYNC_LOCK 0x45880 | |
| 799 | #define GUEST_ASYNC_LOCK_INCR 0x8 | |
| 800 | #define GUEST_ASYNC_BUF 0x458a0 | |
| 801 | #define GUEST_ASYNC_BUF_INCR 0x8 | |
| 802 | #define GUEST_START_STICK 0x458e0 | |
| 803 | #define GUEST_UTIL 0x458e8 | |
| 804 | #define GUEST_MGUEST 0x45908 | |
| 805 | #define GUEST_UTIL_SIZE 0x10 | |
| 806 | #define GUTIL_STICK_LAST 0x0 | |
| 807 | #define GUTIL_STOPPED_CYCLES 0x8 | |
| 808 | #define HVCTL_RES_STATUS_SIZE 0x38 | |
| 809 | #define HVCTL_RES_STATUS_RES 0x0 | |
| 810 | #define HVCTL_RES_STATUS_RESID 0x4 | |
| 811 | #define HVCTL_RES_STATUS_INFOID 0x8 | |
| 812 | #define HVCTL_RES_STATUS_CODE 0xc | |
| 813 | #define HVCTL_RES_STATUS_DATA 0x10 | |
| 814 | #define HVCTL_RES_STATUS_DATA_INCR 0x1 | |
| 815 | #define RS_GUEST_SOFT_STATE_SIZE 0x21 | |
| 816 | #define RS_GUEST_SOFT_STATE 0x0 | |
| 817 | #define RS_GUEST_SOFT_STATE_STR 0x1 | |
| 818 | #define RS_GUEST_SOFT_STATE_STR_INCR 0x1 | |
| 819 | #define DEVOPSVEC_SIZE 0x180 | |
| 820 | #define DEVOPSVEC_DEVINO2VINO 0x0 | |
| 821 | #define DEVOPSVEC_MONDO_RECEIVE 0x8 | |
| 822 | #define DEVOPSVEC_GETVALID 0x10 | |
| 823 | #define DEVOPSVEC_SETVALID 0x18 | |
| 824 | #define DEVOPSVEC_GETSTATE 0x20 | |
| 825 | #define DEVOPSVEC_SETSTATE 0x28 | |
| 826 | #define DEVOPSVEC_GETTARGET 0x30 | |
| 827 | #define DEVOPSVEC_SETTARGET 0x38 | |
| 828 | #define DEVOPSVEC_MAP 0x40 | |
| 829 | #define DEVOPSVEC_MAP_V2 0x48 | |
| 830 | #define DEVOPSVEC_GETMAP 0x50 | |
| 831 | #define DEVOPSVEC_GETMAP_V2 0x58 | |
| 832 | #define DEVOPSVEC_UNMAP 0x60 | |
| 833 | #define DEVOPSVEC_GETBYPASS 0x68 | |
| 834 | #define DEVOPSVEC_CONFIGGET 0x70 | |
| 835 | #define DEVOPSVEC_CONFIGPUT 0x78 | |
| 836 | #define DEVOPSVEC_IOPEEK 0x80 | |
| 837 | #define DEVOPSVEC_IOPOKE 0x88 | |
| 838 | #define DEVOPSVEC_DMASYNC 0x90 | |
| 839 | #define DEVOPSVEC_MSIQ_CONF 0x98 | |
| 840 | #define DEVOPSVEC_MSIQ_INFO 0xa0 | |
| 841 | #define DEVOPSVEC_MSIQ_GETVALID 0xa8 | |
| 842 | #define DEVOPSVEC_MSIQ_SETVALID 0xb0 | |
| 843 | #define DEVOPSVEC_MSIQ_GETSTATE 0xb8 | |
| 844 | #define DEVOPSVEC_MSIQ_SETSTATE 0xc0 | |
| 845 | #define DEVOPSVEC_MSIQ_GETHEAD 0xc8 | |
| 846 | #define DEVOPSVEC_MSIQ_SETHEAD 0xd0 | |
| 847 | #define DEVOPSVEC_MSIQ_GETTAIL 0xd8 | |
| 848 | #define DEVOPSVEC_MSI_GETVALID 0xe0 | |
| 849 | #define DEVOPSVEC_MSI_SETVALID 0xe8 | |
| 850 | #define DEVOPSVEC_MSI_GETSTATE 0xf0 | |
| 851 | #define DEVOPSVEC_MSI_SETSTATE 0xf8 | |
| 852 | #define DEVOPSVEC_MSI_GETMSIQ 0x100 | |
| 853 | #define DEVOPSVEC_MSI_SETMSIQ 0x108 | |
| 854 | #define DEVOPSVEC_MSI_MSG_GETMSIQ 0x110 | |
| 855 | #define DEVOPSVEC_MSI_MSG_SETMSIQ 0x118 | |
| 856 | #define DEVOPSVEC_MSI_MSG_GETVALID 0x120 | |
| 857 | #define DEVOPSVEC_MSI_MSG_SETVALID 0x128 | |
| 858 | #define DEVOPSVEC_GETPERFREG 0x130 | |
| 859 | #define DEVOPSVEC_SETPERFREG 0x138 | |
| 860 | #define DEVOPSVEC_VGETCOOKIE 0x140 | |
| 861 | #define DEVOPSVEC_VSETCOOKIE 0x148 | |
| 862 | #define DEVOPSVEC_VGETVALID 0x150 | |
| 863 | #define DEVOPSVEC_VSETVALID 0x158 | |
| 864 | #define DEVOPSVEC_VGETTARGET 0x160 | |
| 865 | #define DEVOPSVEC_VSETTARGET 0x168 | |
| 866 | #define DEVOPSVEC_VGETSTATE 0x170 | |
| 867 | #define DEVOPSVEC_VSETSTATE 0x178 | |
| 868 | #define VINO2INST_SIZE 0x800 | |
| 869 | #define VINO2INST_VINO 0x0 | |
| 870 | #define VINO2INST_VINO_INCR 0x1 | |
| 871 | #define PIU_COOKIE_SIZE 0x3c0 | |
| 872 | #define PIU_COOKIE_HANDLE 0x0 | |
| 873 | #define PIU_COOKIE_NCU 0x8 | |
| 874 | #define PIU_COOKIE_PCIE 0x10 | |
| 875 | #define PIU_COOKIE_CFG 0x18 | |
| 876 | #define PIU_COOKIE_PERFREGS 0x30 | |
| 877 | #define PIU_COOKIE_EQCTLSET 0x38 | |
| 878 | #define PIU_COOKIE_EQCTLCLR 0x40 | |
| 879 | #define PIU_COOKIE_EQSTATE 0x48 | |
| 880 | #define PIU_COOKIE_EQTAIL 0x50 | |
| 881 | #define PIU_COOKIE_EQHEAD 0x58 | |
| 882 | #define PIU_COOKIE_MSIMAP 0x60 | |
| 883 | #define PIU_COOKIE_MSICLR 0x68 | |
| 884 | #define PIU_COOKIE_MSGMAP 0x70 | |
| 885 | #define PIU_COOKIE_MMUFLUSH 0x80 | |
| 886 | #define PIU_COOKIE_INTCLR 0x88 | |
| 887 | #define PIU_COOKIE_INTMAP 0x90 | |
| 888 | #define PIU_COOKIE_VIRTUAL_INTMAP 0x98 | |
| 889 | #define PIU_COOKIE_ERR_LOCK 0xa0 | |
| 890 | #define PIU_COOKIE_ERR_LOCK_COUNTER 0xa8 | |
| 891 | #define PIU_COOKIE_OE_STATUS 0xb0 | |
| 892 | #define PIU_COOKIE_INOMAX 0xb8 | |
| 893 | #define PIU_COOKIE_VINO 0xba | |
| 894 | #define PIU_COOKIE_IOTSB0 0xc0 | |
| 895 | #define PIU_COOKIE_IOTSB1 0xc8 | |
| 896 | #define PIU_COOKIE_MSIEQBASE 0xd0 | |
| 897 | #define PIU_COOKIE_MSICOOKIE 0xd8 | |
| 898 | #define PIU_COOKIE_ERRCOOKIE 0xe0 | |
| 899 | #define PIU_COOKIE_DMU_ERPT 0xe8 | |
| 900 | #define PIU_COOKIE_PEU_ERPT 0x250 | |
| 901 | #define PIU_COOKIE_BLACKLIST 0x3b8 | |
| 902 | #define PIU_MSIEQ_SIZE 0x28 | |
| 903 | #define PIU_MSIEQ_EQMASK 0x0 | |
| 904 | #define PIU_MSIEQ_BASE 0x8 | |
| 905 | #define PIU_MSIEQ_GUEST 0x10 | |
| 906 | #define PIU_MSIEQ_WORD0 0x18 | |
| 907 | #define PIU_MSIEQ_WORD1 0x20 | |
| 908 | #define PIU_MSI_COOKIE_SIZE 0x5a8 | |
| 909 | #define PIU_MSI_COOKIE_PIU 0x0 | |
| 910 | #define PIU_MSI_COOKIE_EQ 0x8 | |
| 911 | #define PIU_MSI_COOKIE_EQ_INCR 0x28 | |
| 912 | #define PIU_ERR_COOKIE_SIZE 0x18 | |
| 913 | #define PIU_ERR_COOKIE_PIU 0x0 | |
| 914 | #define PIU_ERR_COOKIE_STATE 0x8 | |
| 915 | #define PIU_ERR_COOKIE_STATE_INCR 0x8 | |
| 916 | #define VDEV_STATE_SIZE 0x1010 | |
| 917 | #define VDEV_STATE_HANDLE 0x0 | |
| 918 | #define VDEV_STATE_MAPREG 0x8 | |
| 919 | #define VDEV_STATE_MAPREG_INCR 0x40 | |
| 920 | #define VDEV_STATE_INOMAX 0x1008 | |
| 921 | #define VDEV_STATE_VINOBASE 0x100a | |
| 922 | #define SVC_LINK_SIZE 0x0 | |
| 923 | #define SVC_LINK_PA 0x8 | |
| 924 | #define SVC_LINK_NEXT 0x10 | |
| 925 | #define SVC_CALLBACK_RX 0x0 | |
| 926 | #define SVC_CALLBACK_TX 0x8 | |
| 927 | #define SVC_CALLBACK_COOKIE 0x10 | |
| 928 | #define SVC_CTRL_SIZE 0x80 | |
| 929 | #define SVC_CTRL_XID 0x0 | |
| 930 | #define SVC_CTRL_SID 0x4 | |
| 931 | #define SVC_CTRL_INO 0x8 | |
| 932 | #define SVC_CTRL_MTU 0xc | |
| 933 | #define SVC_CTRL_CONFIG 0x10 | |
| 934 | #define SVC_CTRL_STATE 0x14 | |
| 935 | #define SVC_CTRL_COUNT 0x18 | |
| 936 | #define SVC_CTRL_DSTATE 0x1c | |
| 937 | #define SVC_CTRL_LOCK 0x20 | |
| 938 | #define SVC_CTRL_INTR_COOKIE 0x28 | |
| 939 | #define SVC_CTRL_CALLBACK 0x30 | |
| 940 | #define SVC_CTRL_LINK 0x48 | |
| 941 | #define SVC_CTRL_RECV 0x50 | |
| 942 | #define SVC_CTRL_SEND 0x68 | |
| 943 | #define HV_SVC_DATA_SIZE 0x4e0 | |
| 944 | #define HV_SVC_DATA_RXBASE 0x0 | |
| 945 | #define HV_SVC_DATA_TXBASE 0x8 | |
| 946 | #define HV_SVC_DATA_RXCHANNEL 0x10 | |
| 947 | #define HV_SVC_DATA_TXCHANNEL 0x18 | |
| 948 | #define HV_SVC_DATA_SCR 0x20 | |
| 949 | #define HV_SVC_DATA_SCR_INCR 0x8 | |
| 950 | #define HV_SVC_DATA_NUM_SVCS 0x30 | |
| 951 | #define HV_SVC_DATA_SENDBUSY 0x34 | |
| 952 | #define HV_SVC_DATA_SENDH 0x38 | |
| 953 | #define HV_SVC_DATA_SENDT 0x40 | |
| 954 | #define HV_SVC_DATA_SENDDH 0x48 | |
| 955 | #define HV_SVC_DATA_SENDDT 0x50 | |
| 956 | #define HV_SVC_DATA_LOCK 0x58 | |
| 957 | #define HV_SVC_DATA_SVC 0x60 | |
| 958 | #define HV_SVC_DATA_SVC_INCR 0x80 | |
| 959 | #define SVC_PKT_SIZE 0x8 | |
| 960 | #define SVC_PKT_XID 0x0 | |
| 961 | #define SVC_PKT_SUM 0x4 | |
| 962 | #define SVC_PKT_SID 0x6 | |
| 963 | #define MAPREG_SIZE 0x40 | |
| 964 | #define MAPREG_SHIFT 0x6 | |
| 965 | #define MAPREG_STATE 0x0 | |
| 966 | #define MAPREG_VALID 0x1 | |
| 967 | #define MAPREG_PCPU 0x2 | |
| 968 | #define MAPREG_VCPU 0x4 | |
| 969 | #define MAPREG_INO 0x6 | |
| 970 | #define MAPREG_DATA0 0x8 | |
| 971 | #define MAPREG_DEVCOOKIE 0x10 | |
| 972 | #define MAPREG_GETSTATE 0x18 | |
| 973 | #define MAPREG_SETSTATE 0x20 | |
| 974 | #define DTHDR_SIZE 0x10 | |
| 975 | #define DTHDR_VER 0x0 | |
| 976 | #define DTHDR_NODESZ 0x4 | |
| 977 | #define DTHDR_NAMES 0x8 | |
| 978 | #define DTHDR_DATA 0xc | |
| 979 | #define DTNODE_SIZE 0x10 | |
| 980 | #define DTNODE_TAG 0x0 | |
| 981 | #define DTNODE_DATA 0x8 | |
| 982 | #define TRAPGLOBALS_SIZE 0x40 | |
| 983 | #define TRAPGLOBALS_SHIFT 0x6 | |
| 984 | #define G 0x0 | |
| 985 | #define G_INCR 0x8 | |
| 986 | #define TRAPSTATE_SIZE 0x28 | |
| 987 | #define TRAPSTATE_HTSTATE 0x0 | |
| 988 | #define TRAPSTATE_TSTATE 0x8 | |
| 989 | #define TRAPSTATE_TT 0x10 | |
| 990 | #define TRAPSTATE_TPC 0x18 | |
| 991 | #define TRAPSTATE_TNPC 0x20 | |
| 992 | #define DBGERROR_PAYLOAD_SIZE 0x1f8 | |
| 993 | #define DBGERROR_DATA 0x0 | |
| 994 | #define DBGERROR_DATA_INCR 0x8 | |
| 995 | #define DBGERROR_SIZE 0x200 | |
| 996 | #define DBGERROR_ERROR_SVCH 0x0 | |
| 997 | #define DBGERROR_PAYLOAD 0x8 | |
| 998 | #define DEVINST_SIZE 0x10 | |
| 999 | #define DEVINST_SIZE_SHIFT 0x4 | |
| 1000 | #define DEVINST_COOKIE 0x0 | |
| 1001 | #define DEVINST_OPS 0x8 | |
| 1002 | #define ERPT_SVC_PKT_SIZE 0x10 | |
| 1003 | #define ERPT_PKT_ADDR 0x0 | |
| 1004 | #define ERPT_PKT_SIZE 0x8 | |
| 1005 | #define MAU_QUEUE_SIZE 0x50 | |
| 1006 | #define MQ_LOCK 0x0 | |
| 1007 | #define MQ_STATE 0x8 | |
| 1008 | #define MQ_BUSY 0xc | |
| 1009 | #define MQ_BASE 0x10 | |
| 1010 | #define MQ_BASE_RA 0x18 | |
| 1011 | #define MQ_END 0x20 | |
| 1012 | #define MQ_HEAD 0x28 | |
| 1013 | #define MQ_HEAD_MARKER 0x30 | |
| 1014 | #define MQ_TAIL 0x38 | |
| 1015 | #define MQ_NENTRIES 0x40 | |
| 1016 | #define MQ_CPU_PID 0x48 | |
| 1017 | #define CWQ_QUEUE_SIZE 0x10d0 | |
| 1018 | #define CQ_LOCK 0x0 | |
| 1019 | #define CQ_STATE 0x8 | |
| 1020 | #define CQ_BUSY 0xc | |
| 1021 | #define CQ_DR_BASE_RA 0x10 | |
| 1022 | #define CQ_DR_BASE 0x18 | |
| 1023 | #define CQ_DR_LAST 0x20 | |
| 1024 | #define CQ_DR_HEAD 0x28 | |
| 1025 | #define CQ_DR_TAIL 0x30 | |
| 1026 | #define CQ_BASE 0x38 | |
| 1027 | #define CQ_LAST 0x40 | |
| 1028 | #define CQ_HEAD 0x48 | |
| 1029 | #define CQ_HEAD_MARKER 0x50 | |
| 1030 | #define CQ_TAIL 0x58 | |
| 1031 | #define CQ_NENTRIES 0x60 | |
| 1032 | #define CQ_CPU_PID 0x68 | |
| 1033 | #define CQ_SCR1 0x70 | |
| 1034 | #define CQ_SCR2 0x78 | |
| 1035 | #define CQ_SCR3 0x80 | |
| 1036 | #define CQ_DR_HV_OFFSET 0x88 | |
| 1037 | #define CQ_HV_CWS 0x90 | |
| 1038 | #define CQ_HV_CWS_INCR 0x40 | |
| 1039 | #define NCS_HVDESC_SIZE 0x40 | |
| 1040 | #define NCS_HVDESC_SHIFT 0x6 | |
| 1041 | #define NHD_STATE 0x0 | |
| 1042 | #define NHD_TYPE 0x8 | |
| 1043 | #define NHD_REGS 0x10 | |
| 1044 | #define NHD_ERRSTATUS 0x30 | |
| 1045 | #define MA_REGS_SIZE 0x20 | |
| 1046 | #define MR_CTL 0x0 | |
| 1047 | #define MR_MPA 0x8 | |
| 1048 | #define MR_MA 0x10 | |
| 1049 | #define MR_NP 0x18 | |
| 1050 | #define NCS_QCONF_ARG_SIZE 0x20 | |
| 1051 | #define NQ_MID 0x0 | |
| 1052 | #define NQ_BASE 0x8 | |
| 1053 | #define NQ_END 0x10 | |
| 1054 | #define NQ_NENTRIES 0x18 | |
| 1055 | #define NCS_QTAIL_UPDATE_ARG_SIZE 0x18 | |
| 1056 | #define NU_MID 0x0 | |
| 1057 | #define NU_TAIL 0x8 | |
| 1058 | #define NU_SYNCFLAG 0x10 | |
| 1059 | #define CWQ_CW_RET_SIZE 0x8 | |
| 1060 | #define CW_RET_DST_ADDR 0x0 | |
| 1061 | #define CW_RET_CSR 0x0 | |
| 1062 | #define CWQ_CW_SIZE 0x40 | |
| 1063 | #define CWQ_CW_SHIFT 0x6 | |
| 1064 | #define CW_CTLBITS 0x0 | |
| 1065 | #define CW_SRC_ADDR 0x8 | |
| 1066 | #define CW_AUTH_KEY_ADDR 0x10 | |
| 1067 | #define CW_AUTH_IV_ADDR 0x18 | |
| 1068 | #define CW_FINAL_AUTH_STATE_ADDR 0x20 | |
| 1069 | #define CW_ENC_KEY_ADDR 0x28 | |
| 1070 | #define CW_ENC_IV_ADDR 0x30 | |
| 1071 | #define CW_RET 0x38 | |
| 1072 | #define CW_DST_ADDR (CW_RET + CW_RET_DST_ADDR) | |
| 1073 | #define CW_CSR (CW_RET + CW_RET_DST_ADDR) | |
| 1074 | #define CRYPTO_INTR_SIZE 0x18 | |
| 1075 | #define CI_COOKIE 0x0 | |
| 1076 | #define CI_ACTIVE 0x8 | |
| 1077 | #define CI_DATA 0x10 | |
| 1078 | #define RNG_CTLREGS_SIZE 0x20 | |
| 1079 | #define RNG_CTLREGS_REG0 0x0 | |
| 1080 | #define RNG_CTLREGS_REG1 0x8 | |
| 1081 | #define RNG_CTLREGS_REG2 0x10 | |
| 1082 | #define RNG_CTLREGS_REG3 0x18 | |
| 1083 | #define RNG_CTLDATA_SIZE 0x38 | |
| 1084 | #define RNG_CTLDATA_REGS 0x0 | |
| 1085 | #define RNG_CTLDATA_STATE 0x20 | |
| 1086 | #define RNG_CTLDATA_GUESTID 0x28 | |
| 1087 | #define RNG_CTLDATA_READYTIME 0x30 | |
| 1088 | #define SVCCN_PKT_SIZE 0x3 | |
| 1089 | #define SVCCN_PKT_TYPE 0x0 | |
| 1090 | #define SVCCN_PKT_LEN 0x1 | |
| 1091 | #define SVCCN_PKT_DATA 0x2 | |
| 1092 | #define SVCCN_PKT_DATA_INCR 0x1 | |
| 1093 | #define VBSC_CTRL_PKT_SIZE 0x20 | |
| 1094 | #define VBSC_PKT_CMD 0x0 | |
| 1095 | #define VBSC_PKT_ARG0 0x8 | |
| 1096 | #define VBSC_PKT_ARG1 0x10 | |
| 1097 | #define VBSC_PKT_ARG2 0x18 | |
| 1098 | #define CB_SIZE 0x20 | |
| 1099 | #define CB_TICK 0x0 | |
| 1100 | #define CB_HANDLER 0x8 | |
| 1101 | #define CB_ARG0 0x10 | |
| 1102 | #define CB_ARG1 0x18 | |
| 1103 | #define CY_SIZE 0x248 | |
| 1104 | #define CY_T0 0x0 | |
| 1105 | #define CY_CB 0x8 | |
| 1106 | #define CY_CB_INCR 0x20 | |
| 1107 | #define CY_TICK 0x228 | |
| 1108 | #define CY_HANDLER 0x230 | |
| 1109 | #define CY_ARG0 0x238 | |
| 1110 | #define CY_ARG1 0x240 | |
| 1111 | #define STRAND_CY_T0 (STRAND_CYCLIC + CY_T0) | |
| 1112 | #define STRAND_CY_CB (STRAND_CYCLIC + CY_CB) | |
| 1113 | #define STRAND_CY_TICK (STRAND_CYCLIC + CY_TICK) | |
| 1114 | #define STRAND_CY_HANDLER (STRAND_CYCLIC + CY_HANDLER) | |
| 1115 | #define STRAND_CY_ARG0 (STRAND_CYCLIC + CY_ARG0) | |
| 1116 | #define STRAND_CY_ARG1 (STRAND_CYCLIC + CY_ARG1) | |
| 1117 | #define STRAND_CY_CB_TICK (STRAND_CYCLIC + CY_CB + CB_TICK) | |
| 1118 | #define STRAND_CY_CB_HANDLER (STRAND_CYCLIC + CY_CB + CB_HANDLER) | |
| 1119 | #define STRAND_CY_CB_ARG0 (STRAND_CYCLIC + CY_CB + CB_ARG0) | |
| 1120 | #define STRAND_CY_CB_ARG1 (STRAND_CYCLIC + CY_CB + CB_ARG1) | |
| 1121 | #define CB_LAST ((N_CB - 1) * CB_SIZE) | |
| 1122 | #define STRAND_CY_CB_LAST_TICK (STRAND_CY_CB_TICK + CB_LAST) | |
| 1123 | #define ERROR_TABLE_ENTRY_SIZE 0x48 | |
| 1124 | #define ERR_NAME 0x0 | |
| 1125 | #define ERR_NAME_INCR 0x1 | |
| 1126 | #define ERR_REPORT_FCN 0x10 | |
| 1127 | #define ERR_GUEST_REPORT_FCN 0x18 | |
| 1128 | #define ERR_CORRECT_FCN 0x20 | |
| 1129 | #define ERR_STORM_FCN 0x28 | |
| 1130 | #define ERR_PRINT_FCN 0x30 | |
| 1131 | #define ERR_FLAGS 0x38 | |
| 1132 | #define ERR_SUN4V_RPRT_TYPE 0x3c | |
| 1133 | #define ERR_SUN4V_EDESC 0x3d | |
| 1134 | #define ERR_REPORT_SIZE 0x40 | |
| 1135 | #define ERR_WAY_SIZE 0x88 | |
| 1136 | #define ERR_WAY_TAG_AND_ECC 0x0 | |
| 1137 | #define ERR_WAY_DATA_AND_ECC 0x8 | |
| 1138 | #define ERR_WAY_DATA_AND_ECC_INCR 0x8 | |
| 1139 | #define ERR_L2_SIZE 0x8d0 | |
| 1140 | #define ERR_L2_VDBITS 0x0 | |
| 1141 | #define ERR_L2_UABITS 0x8 | |
| 1142 | #define ERR_L2_WAYS 0x10 | |
| 1143 | #define ERR_L2_WAYS_INCR 0x88 | |
| 1144 | #define ERR_DRAM_CONTENTS 0x890 | |
| 1145 | #define ERR_DRAM_CONTENTS_INCR 0x8 | |
| 1146 | #define ERR_TLB_SIZE 0x10 | |
| 1147 | #define ERR_TLB_TAG 0x0 | |
| 1148 | #define ERR_TLB_DATA 0x8 | |
| 1149 | #define ERR_ICACHE_WAY_SIZE 0x48 | |
| 1150 | #define ERR_ICACHE_WAY_INSTR 0x0 | |
| 1151 | #define ERR_ICACHE_WAY_INSTR_INCR 0x8 | |
| 1152 | #define ERR_ICACHE_WAY_TAG 0x40 | |
| 1153 | #define ERR_ICACHE_SIZE 0x240 | |
| 1154 | #define ERR_ICACHE_WAY 0x0 | |
| 1155 | #define ERR_ICACHE_WAY_INCR 0x48 | |
| 1156 | #define ERR_DCACHE_WAY_SIZE 0x18 | |
| 1157 | #define ERR_DCACHE_WAY_DATA 0x0 | |
| 1158 | #define ERR_DCACHE_WAY_DATA_INCR 0x8 | |
| 1159 | #define ERR_DCACHE_WAY_TAG 0x10 | |
| 1160 | #define ERR_DCACHE_SIZE 0x60 | |
| 1161 | #define ERR_DCACHE_WAY 0x0 | |
| 1162 | #define ERR_DCACHE_WAY_INCR 0x18 | |
| 1163 | #define ERR_SSI_SIZE 0x10 | |
| 1164 | #define ERR_SSI_TIMEOUT 0x0 | |
| 1165 | #define ERR_SSI_LOG 0x8 | |
| 1166 | #define ERR_STB_SIZE 0x28 | |
| 1167 | #define ERR_STB_DATA 0x0 | |
| 1168 | #define ERR_STB_DATA_ECC 0x8 | |
| 1169 | #define ERR_STB_PARITY 0x10 | |
| 1170 | #define ERR_STB_MARKS 0x18 | |
| 1171 | #define ERR_STB_CURR_PTR 0x20 | |
| 1172 | #define ERR_SCRATCHPAD_SIZE 0x10 | |
| 1173 | #define ERR_SCRATCHPAD_DATA 0x0 | |
| 1174 | #define ERR_SCRATCHPAD_ECC 0x8 | |
| 1175 | #define ERR_TCA_SIZE 0x10 | |
| 1176 | #define ERR_TCA_DATA 0x0 | |
| 1177 | #define ERR_TCA_ECC 0x8 | |
| 1178 | #define ERR_REG_SIZE 0x8 | |
| 1179 | #define ERR_REG_ECC 0x0 | |
| 1180 | #define ERR_TSA_SIZE 0x78 | |
| 1181 | #define ERR_TSA_ECC 0x0 | |
| 1182 | #define ERR_TSA_TL 0x8 | |
| 1183 | #define ERR_TSA_TT 0x10 | |
| 1184 | #define ERR_TSA_TSTATE 0x18 | |
| 1185 | #define ERR_TSA_HTSTATE 0x20 | |
| 1186 | #define ERR_TSA_TPC 0x28 | |
| 1187 | #define ERR_TSA_TNPC 0x30 | |
| 1188 | #define ERR_TSA_CPU_MONDO_QHEAD 0x38 | |
| 1189 | #define ERR_TSA_CPU_MONDO_QTAIL 0x40 | |
| 1190 | #define ERR_TSA_DEV_MONDO_QHEAD 0x48 | |
| 1191 | #define ERR_TSA_DEV_MONDO_QTAIL 0x50 | |
| 1192 | #define ERR_TSA_ERR_RES_QHEAD 0x58 | |
| 1193 | #define ERR_TSA_ERR_RES_QTAIL 0x60 | |
| 1194 | #define ERR_TSA_ERR_NONRES_QHEAD 0x68 | |
| 1195 | #define ERR_TSA_ERR_NONRES_QTAIL 0x70 | |
| 1196 | #define ERR_MMU_ERR_REGS_SIZE 0x88 | |
| 1197 | #define ERR_MMU_PARITY 0x0 | |
| 1198 | #define ERR_MMU_PARITY_INCR 0x1 | |
| 1199 | #define ERR_MMU_TSB_CFG_CTX0 0x8 | |
| 1200 | #define ERR_MMU_TSB_CFG_CTX0_INCR 0x8 | |
| 1201 | #define ERR_MMU_TSB_CFG_CTXNZ 0x28 | |
| 1202 | #define ERR_MMU_TSB_CFG_CTXNZ_INCR 0x8 | |
| 1203 | #define ERR_MMU_REAL_RANGE 0x48 | |
| 1204 | #define ERR_MMU_REAL_RANGE_INCR 0x8 | |
| 1205 | #define ERR_MMU_PHYS_OFFSET 0x68 | |
| 1206 | #define ERR_MMU_PHYS_OFFSET_INCR 0x8 | |
| 1207 | #define ERR_MAMU_SIZE 0x28 | |
| 1208 | #define ERR_MA_PA 0x0 | |
| 1209 | #define ERR_MA_ADDR 0x8 | |
| 1210 | #define ERR_MA_NP 0x10 | |
| 1211 | #define ERR_MA_CTL 0x18 | |
| 1212 | #define ERR_MA_SYNC 0x20 | |
| 1213 | #define ERR_TRAP_REGS_SIZE 0x28 | |
| 1214 | #define ERR_TT 0x0 | |
| 1215 | #define ERR_TPC 0x8 | |
| 1216 | #define ERR_TNPC 0x10 | |
| 1217 | #define ERR_TSTATE 0x18 | |
| 1218 | #define ERR_HTSTATE 0x20 | |
| 1219 | #define ERR_SOC_SIZE 0x48 | |
| 1220 | #define ERR_SOC_ESR 0x0 | |
| 1221 | #define ERR_SOC_ELER 0x8 | |
| 1222 | #define ERR_SOC_EIER 0x10 | |
| 1223 | #define ERR_SOC_VCID 0x18 | |
| 1224 | #define ERR_SOC_FEER 0x20 | |
| 1225 | #define ERR_SOC_PESR 0x28 | |
| 1226 | #define ERR_SOC_EIR 0x30 | |
| 1227 | #define ERR_SOC_SII_SYND 0x38 | |
| 1228 | #define ERR_SOC_NCU_SYND 0x40 | |
| 1229 | #define ERR_DIAG_DATA_SIZE 0x8d0 | |
| 1230 | #define ERR_DIAG_DATA_DTLB 0x0 | |
| 1231 | #define ERR_DIAG_DATA_DTLB_INCR 0x10 | |
| 1232 | #define ERR_DIAG_DATA_ITLB 0x0 | |
| 1233 | #define ERR_DIAG_DATA_ITLB_INCR 0x10 | |
| 1234 | #define ERR_DIAG_DATA_ICACHE 0x0 | |
| 1235 | #define ERR_DIAG_DATA_DCACHE 0x0 | |
| 1236 | #define ERR_DIAG_DATA_SSI_INFO 0x0 | |
| 1237 | #define ERR_DIAG_DATA_STB 0x0 | |
| 1238 | #define ERR_DIAG_DATA_SCRATCHPAD 0x0 | |
| 1239 | #define ERR_DIAG_DATA_TSA 0x0 | |
| 1240 | #define ERR_DIAG_DATA_MMU_REGS 0x0 | |
| 1241 | #define ERR_DIAG_DATA_MAMU 0x0 | |
| 1242 | #define ERR_DIAG_DATA_SOC 0x0 | |
| 1243 | #define ERR_DIAG_DATA_TCA 0x0 | |
| 1244 | #define ERR_DIAG_DATA_REG 0x0 | |
| 1245 | #define ERR_DIAG_DATA_L2_CACHE 0x0 | |
| 1246 | #define ERR_DIAG_DATA_TRAP_REGS 0x0 | |
| 1247 | #define ERR_DIAG_DATA_TRAP_REGS_INCR 0x28 | |
| 1248 | #define ERR_DIAG_DATA_REG_INFO 0x0 | |
| 1249 | #define ERR_ABORT_DATA_SIZE 0x800 | |
| 1250 | #define ERR_ABORT_VERSION 0x0 | |
| 1251 | #define ERR_ABORT_VERSION_INCR 0x1 | |
| 1252 | #define ERR_ABORT_PC 0x40 | |
| 1253 | #define ERR_ABORT_CWP 0x48 | |
| 1254 | #define ERR_ABORT_TRAP_REGS 0x50 | |
| 1255 | #define ERR_ABORT_TRAP_REGS_INCR 0x28 | |
| 1256 | #define ERR_ABORT_GLOBAL_REGS 0x140 | |
| 1257 | #define ERR_ABORT_GLOBAL_REGS_INCR 0x8 | |
| 1258 | #define ERR_ABORT_REG_WINDOWS 0x200 | |
| 1259 | #define ERR_ABORT_REG_WINDOWS_INCR 0x8 | |
| 1260 | #define ERR_DIAG_BUF_SIZE 0xa98 | |
| 1261 | #define ERR_DIAG_BUF_SPARC_ISFSR 0x0 | |
| 1262 | #define ERR_DIAG_BUF_SPARC_DSFSR 0x8 | |
| 1263 | #define ERR_DIAG_BUF_SPARC_DSFAR 0x10 | |
| 1264 | #define ERR_DIAG_BUF_SPARC_DESR 0x18 | |
| 1265 | #define ERR_DIAG_BUF_SPARC_DFESR 0x20 | |
| 1266 | #define ERR_DIAG_BUF_L2_CACHE_ESR 0x28 | |
| 1267 | #define ERR_DIAG_BUF_L2_CACHE_ESR_INCR 0x8 | |
| 1268 | #define ERR_DIAG_BUF_L2_CACHE_EAR 0x68 | |
| 1269 | #define ERR_DIAG_BUF_L2_CACHE_EAR_INCR 0x8 | |
| 1270 | #define ERR_DIAG_BUF_L2_CACHE_ND 0xa8 | |
| 1271 | #define ERR_DIAG_BUF_L2_CACHE_ND_INCR 0x8 | |
| 1272 | #define ERR_DIAG_BUF_DRAM_ESR 0xe8 | |
| 1273 | #define ERR_DIAG_BUF_DRAM_ESR_INCR 0x8 | |
| 1274 | #define ERR_DIAG_BUF_DRAM_EAR 0x108 | |
| 1275 | #define ERR_DIAG_BUF_DRAM_EAR_INCR 0x8 | |
| 1276 | #define ERR_DIAG_BUF_DRAM_CTR 0x128 | |
| 1277 | #define ERR_DIAG_BUF_DRAM_CTR_INCR 0x8 | |
| 1278 | #define ERR_DIAG_BUF_DRAM_LOC 0x148 | |
| 1279 | #define ERR_DIAG_BUF_DRAM_LOC_INCR 0x8 | |
| 1280 | #define ERR_DIAG_BUF_DRAM_FBD 0x168 | |
| 1281 | #define ERR_DIAG_BUF_DRAM_FBD_INCR 0x8 | |
| 1282 | #define ERR_DIAG_BUF_DRAM_RETRY 0x188 | |
| 1283 | #define ERR_DIAG_BUF_DRAM_RETRY_INCR 0x8 | |
| 1284 | #define ERR_DIAG_L2_BANK 0x1a8 | |
| 1285 | #define ERR_DIAG_L2_LINE_STATE 0x1b0 | |
| 1286 | #define ERR_DIAG_L2_PA 0x1b8 | |
| 1287 | #define ERR_DIAG_BUF_DIAG_DATA 0x1c0 | |
| 1288 | #define ERR_DIAG_BUF_RPRT_IN_USE 0xa90 | |
| 1289 | #define ERR_DIAG_BUF_RPRT_SIZE 0xa94 | |
| 1290 | #define CPU_SUN4V_RPRT_SIZE 0x40 | |
| 1291 | #define CPU_SUN4V_RPRT_G_EHDL 0x0 | |
| 1292 | #define CPU_SUN4V_RPRT_G_STICK 0x8 | |
| 1293 | #define CPU_SUN4V_RPRT_EDESC 0x10 | |
| 1294 | #define CPU_SUN4V_RPRT_ATTR 0x14 | |
| 1295 | #define CPU_SUN4V_RPRT_ADDR 0x18 | |
| 1296 | #define CPU_SUN4V_RPRT_SZ 0x20 | |
| 1297 | #define CPU_SUN4V_RPRT_G_CPUID 0x24 | |
| 1298 | #define CPU_SUN4V_RPRT_G_SECS 0x26 | |
| 1299 | #define CPU_SUN4V_RPRT_ASI 0x28 | |
| 1300 | #define CPU_SUN4V_RPRT_REG 0x2a | |
| 1301 | #define CPU_SUN4V_RPRT_WORD6 0x2c | |
| 1302 | #define CPU_SUN4V_RPRT_WORD7 0x30 | |
| 1303 | #define CPU_SUN4V_RPRT_WORD8 0x38 | |
| 1304 | #define ESUN4V_G_EHDL CPU_SUN4V_RPRT_G_EHDL | |
| 1305 | #define ESUN4V_G_STICK CPU_SUN4V_RPRT_G_STICK | |
| 1306 | #define ESUN4V_EDESC CPU_SUN4V_RPRT_EDESC | |
| 1307 | #define ESUN4V_ATTR CPU_SUN4V_RPRT_ATTR | |
| 1308 | #define ESUN4V_ADDR CPU_SUN4V_RPRT_ADDR | |
| 1309 | #define ESUN4V_SZ CPU_SUN4V_RPRT_SZ | |
| 1310 | #define ESUN4V_G_CPUID CPU_SUN4V_RPRT_G_CPUID | |
| 1311 | #define ESUN4V_G_SECS CPU_SUN4V_RPRT_G_SECS | |
| 1312 | #define ERR_SUN4V_RPRT_SIZE 0x48 | |
| 1313 | #define ERR_SUN4V_CPU_ERPT 0x0 | |
| 1314 | #define ERR_SUN4V_RPRT_IN_USE 0x40 | |
| 1315 | #define ERR_SUN4V_PCIE_ERPT ERR_SUN4V_CPU_ERPT | |
| 1316 | #define ERR_SUN4V_RPRT_G_EHDL (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_EHDL) | |
| 1317 | #define ERR_SUN4V_RPRT_G_STICK (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_STICK) | |
| 1318 | #define ERR_SUN4V_RPRT_EDESC (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_EDESC) | |
| 1319 | #define ERR_SUN4V_RPRT_ATTR (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_ATTR) | |
| 1320 | #define ERR_SUN4V_RPRT_ADDR (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_ADDR) | |
| 1321 | #define ERR_SUN4V_RPRT_SZ (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_SZ) | |
| 1322 | #define ERR_SUN4V_RPRT_G_CPUID (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_CPUID) | |
| 1323 | #define ERR_SUN4V_RPRT_G_SECS (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_SECS) | |
| 1324 | #define ERR_SUN4V_RPRT_ASI (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_ASI) | |
| 1325 | #define ERR_SUN4V_RPRT_REG (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_REG) | |
| 1326 | #define ERR_SUN4V_PCIE_SYSINO (ERR_SUN4V_PCIE_ERPT + PCIERPT_SYSINO) | |
| 1327 | #define ERR_SUN4V_PCIE_EHDL (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_EHDL) | |
| 1328 | #define ERR_SUN4V_PCIE_STICK (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_STICK) | |
| 1329 | #define ERR_SUN4V_PCIE_DESC (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_DESC) | |
| 1330 | #define ERR_SUN4V_PCIE_SPECIFIC (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_SPECFIC) | |
| 1331 | #define ERR_SUN4V_PCIE_WORD4 (ERR_SUN4V_PCIE_ERPT + PCIERPT_WORD4) | |
| 1332 | #define ERR_SUN4V_PCIE_HDR1 (ERR_SUN4V_PCIE_ERPT + PCIERPT_HDR1) | |
| 1333 | #define ERR_SUN4V_PCIE_HDR2 (ERR_SUN4V_PCIE_ERPT + PCIERPT_HDR2) | |
| 1334 | #define ERR_DIAG_RPRT_SIZE 0xaf0 | |
| 1335 | #define ERR_DIAG_RPRT_ERROR_TYPE 0x0 | |
| 1336 | #define ERR_DIAG_RPRT_REPORT_TYPE 0x8 | |
| 1337 | #define ERR_DIAG_RPRT_TOD 0x10 | |
| 1338 | #define ERR_DIAG_RPRT_EHDL 0x18 | |
| 1339 | #define ERR_DIAG_RPRT_ERR_STICK 0x20 | |
| 1340 | #define ERR_DIAG_RPRT_CPUVER 0x28 | |
| 1341 | #define ERR_DIAG_RPRT_SERIAL 0x30 | |
| 1342 | #define ERR_DIAG_RPRT_TSTATE 0x38 | |
| 1343 | #define ERR_DIAG_RPRT_HTSTATE 0x40 | |
| 1344 | #define ERR_DIAG_RPRT_TPC 0x48 | |
| 1345 | #define ERR_DIAG_RPRT_CPUID 0x50 | |
| 1346 | #define ERR_DIAG_RPRT_TT 0x52 | |
| 1347 | #define ERR_DIAG_RPRT_TL 0x54 | |
| 1348 | #define ERR_DIAG_RPRT_ERR_DIAG 0x58 | |
| 1349 | #define ERR_DIAG_RPRT_IN_USE (ERR_DIAG_RPRT_ERR_DIAG + ERR_DIAG_BUF_RPRT_IN_USE) | |
| 1350 | #define ERR_DIAG_ABORT_DATA ERR_DIAG_RPRT_ERR_DIAG | |
| 1351 | #define ERR_DIAG_DATA_OFFSET (ERR_DIAG_RPRT_ERR_DIAG + ERR_DIAG_BUF_DIAG_DATA) | |
| 1352 | #define ERR_DIAG_RPRT_REPORT_SIZE (ERR_DIAG_RPRT_ERR_DIAG + ERR_DIAG_BUF_RPRT_SIZE) | |
| 1353 | #define NIU_COOKIE_SIZE 0x10 | |
| 1354 | #define NIU_LDG2LDN_TABLE 0x0 | |
| 1355 | #define NIU_VEC2LDG_TABLE 0x8 | |
| 1356 | #define ECC_SYNDROME_TABLE_ENTRY_SIZE 0x1 | |
| 1357 | #define ECC_MASK_TABLE_ENTRY_SIZE 0x4 | |
| 1358 | #define FPGA_UART_COOKIE_SIZE 0x20 | |
| 1359 | #define FPGA_UART_COOKIE_STATUS 0x0 | |
| 1360 | #define FPGA_UART_COOKIE_ENABLE 0x8 | |
| 1361 | #define FPGA_UART_COOKIE_DISABLE 0x10 | |
| 1362 | #define FPGA_UART_COOKIE_VALID 0x18 | |
| 1363 | #define FPGA_UART_COOKIE_STATE 0x19 | |
| 1364 | #define FPGA_UART_COOKIE_TARGET 0x1a | |
| 1365 | ||
| 1366 | #define ENUM_HVctl_res_guest 0x0 | |
| 1367 | #define ENUM_HVctl_res_vcpu 0x1 | |
| 1368 | #define ENUM_HVctl_res_memory 0x2 | |
| 1369 | #define ENUM_HVctl_res_mau 0x3 | |
| 1370 | #define ENUM_HVctl_res_cwq 0x4 | |
| 1371 | #define ENUM_HVctl_res_ldc 0x5 | |
| 1372 | #define ENUM_HVctl_res_console 0x6 | |
| 1373 | #define ENUM_HVctl_res_hv_ldc 0x7 | |
| 1374 | #define ENUM_HVctl_res_pcie_bus 0x8 | |
| 1375 | #define ENUM_HVctl_res_guestmd 0x9 | |
| 1376 | #define ENUM_HVctl_res_network_device 0xa | |
| 1377 | ||
| 1378 | #define ENUM_HVctl_info_guest_state 0x0 | |
| 1379 | #define ENUM_HVctl_info_guest_soft_state 0x1 | |
| 1380 | #define ENUM_HVctl_info_guest_tod 0x2 | |
| 1381 | #define ENUM_HVctl_info_guest_utilisation 0x3 | |
| 1382 | #define ENUM_HVctl_info_guest_max 0x4 | |
| 1383 | #define MCONFIG_MAUS 0x0 | |
| 1384 | #define MCONFIG_CWQS 0x8 | |
| 1385 | #define MCONFIG_RNG 0x10 | |
| 1386 | #define CONFIG_MAUS (CONFIG_MCONFIG + MCONFIG_MAUS) | |
| 1387 | #define CONFIG_CWQS (CONFIG_MCONFIG + MCONFIG_CWQS) | |
| 1388 | #define CONFIG_RNG (CONFIG_MCONFIG + MCONFIG_RNG) | |
| 1389 | #define MGUEST_NIU_STATEP 0x0 | |
| 1390 | #define GUEST_NIU_STATEP (GUEST_MGUEST + MGUEST_NIU_STATEP) | |
| 1391 | #define NIUMAPREG_SIZE 0x40 | |
| 1392 | #define NIUMAPREG_SHIFT 0x6 | |
| 1393 | #define NIUMAPREG_STATE 0x0 | |
| 1394 | #define NIUMAPREG_VALID 0x4 | |
| 1395 | #define NIUMAPREG_VCPUP 0x8 | |
| 1396 | #define NIUSTATE_SIZE 0x1000 | |
| 1397 | #define NIUSTATE_MAPREG 0x0 | |
| 1398 | #define NIUSTATE_MAPREG_INCR 0x40 |