* ========== Copyright Header Begin ==========================================
* Hypervisor Software File: offsets.h
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* - Do no alter or remove copyright notices
* - Redistribution and use of this software in source and binary forms, with
* or without modification, are permitted provided that the following
* - Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* - Redistribution in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of Sun Microsystems, Inc. or the names of contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* This software is provided "AS IS," without a warranty of any kind.
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* ========== Copyright Header End ============================================
#define NAMETABLE_SIZE 0x2e8
#define HDNAME_DEVICES 0x30
#define HDNAME_DEVICE 0x38
#define HDNAME_SERVICES 0x40
#define HDNAME_SERVICE 0x48
#define HDNAME_GUESTS 0x50
#define HDNAME_GUEST 0x58
#define HDNAME_ROMSIZE 0x80
#define HDNAME_ROMBASE 0x88
#define HDNAME_MEMORY 0x90
#define HDNAME_MBLOCK 0x98
#define HDNAME_UNBIND 0xa0
#define HDNAME_UARTBASE 0xb8
#define HDNAME_INOBITMAP 0xd0
#define HDNAME_TODFREQUENCY 0xe0
#define HDNAME_TODOFFSET 0xe8
#define HDNAME_STRANDID 0x118
#define HDNAME_PARTTAG 0x120
#define HDNAME_MEMOFFSET 0x140
#define HDNAME_MEMSIZE 0x148
#define HDNAME_MEMBASE 0x150
#define HDNAME_REALBASE 0x158
#define HDNAME_HYPERVISOR 0x160
#define HDNAME_PERFCTRACCESS 0x168
#define HDNAME_PERFCTRHTACCESS 0x170
#define HDNAME_RNGCTLACCESSIBLE 0x178
#define HDNAME_VPCIDEVICE 0x180
#define HDNAME_PCIREGS 0x188
#define HDNAME_CFGHANDLE 0x190
#define HDNAME_CFGBASE 0x198
#define HDNAME_DISKPA 0x1a0
#define HDNAME_DIAGPRIV 0x1a8
#define HDNAME_DEBUGPRINTFLAGS 0x1b0
#define HDNAME_IOBASE 0x1b8
#define HDNAME_HVUART 0x1c0
#define HDNAME_FLAGS 0x1c8
#define HDNAME_STICKFREQUENCY 0x1d0
#define HDNAME_CEBLACKOUTSEC 0x1d8
#define HDNAME_CEPOLLSEC 0x1e0
#define HDNAME_MEMSCRUBMAX 0x1e8
#define HDNAME_ERPT_PA 0x1f0
#define HDNAME_ERPT_SIZE 0x1f8
#define HDNAME_VDEVS 0x200
#define HDNAME_RESET_REASON 0x208
#define HDNAME_LDC_ENDPOINTS 0x210
#define HDNAME_SP_LDC_ENDPOINTS 0x218
#define HDNAME_LDC_ENDPOINT 0x220
#define HDNAME_CHANNEL 0x228
#define HDNAME_TARGET_TYPE 0x230
#define HDNAME_TARGET_GUEST 0x238
#define HDNAME_TARGET_CHANNEL 0x240
#define HDNAME_TX_INO 0x248
#define HDNAME_RX_INO 0x250
#define HDNAME_SVC_ID 0x258
#define HDNAME_SVC_ARG 0x260
#define HDNAME_SVC_VINO 0x268
#define HDNAME_PRIVATE_SVC 0x270
#define HDNAME_LDC_MAPINRABASE 0x278
#define HDNAME_LDC_MAPINSIZE 0x280
#define HDNAME_RESOURCE_ID 0x290
#define HDNAME_CONSOLES 0x298
#define HDNAME_CONSOLE 0x2a0
#define HDNAME_VIRTUAL_DEVICES 0x2a8
#define HDNAME_CHANNEL_DEVICES 0x2b0
#define HDNAME_SYS_HWTW_MODE 0x2b8
#define HDNAME_PCIE_BUS 0x2c0
#define HDNAME_ALLOW_BYPASS 0x2c8
#define HDNAME_L2SCRUB_INTERVAL 0x2d0
#define HDNAME_L2SCRUB_ENTRIES 0x2d8
#define HDNAME_CONTENT_VERSION 0x2e0
#define CONFIG_SIZE 0x570
#define CONFIG_MEMBASE 0x0
#define CONFIG_MEMSIZE 0x8
#define CONFIG_ACTIVE_HVMD 0x10
#define CONFIG_PARSE_HVMD 0x18
#define CONFIG_RELOC 0x20
#define CONFIG_GUESTS 0x28
#define CONFIG_MBLOCKS 0x30
#define CONFIG_VCPUS 0x38
#define CONFIG_STRANDS 0x40
#define CONFIG_VSTATE 0x48
#define CONFIG_PCIE_BUSSES 0x50
#define CONFIG_HV_LDCS 0x58
#define CONFIG_SP_LDCS 0x60
#define CONFIG_SP_LDC_MAX_CID 0x68
#define CONFIG_DUMMYTSB 0x70
#define CONFIG_SINGLE_STRAND_LOCK 0x78
#define CONFIG_STRAND_STARTSET 0x80
#define CONFIG_STPRES 0x88
#define CONFIG_STACTIVE 0x90
#define CONFIG_STIDLE 0x98
#define CONFIG_STHALT 0xa0
#define CONFIG_PRINT_SPINLOCK 0xa8
#define CONFIG_HEARTBEAT_CPU 0xb0
#define CONFIG_ERROR_SVCH 0xb8
#define CONFIG_VINTR 0xc8
#define CONFIG_HVUART_ADDR 0xd0
#define CONFIG_TODFREQUENCY 0xe0
#define CONFIG_STICKFREQUENCY 0xe8
#define CONFIG_SYS_HWTW_MODE 0xf0
#define CONFIG_ERPT_PA 0xf8
#define CONFIG_ERPT_SIZE 0x100
#define CONFIG_SRAM_ERPT_BUF_INUSE 0x108
#define CONFIG_DEVS_DTNODE 0x118
#define CONFIG_SVCS_DTNODE 0x120
#define CONFIG_GUESTS_DTNODE 0x128
#define CONFIG_CPUS_DTNODE 0x130
#define CONFIG_HV_LDCS_DTNODE 0x138
#define CONFIG_SP_LDCS_DTNODE 0x140
#define CONFIG_ERRORLOCK 0x148
#define CONFIG_HDNAMETABLE 0x150
#define CONFIG_INTRTGT 0x438
#define CONFIG_MEMSCRUB_MAX 0x440
#define CONFIG_DEVINSTANCES 0x448
#define CONFIG_CYCLIC_MAXD 0x450
#define CONFIG_HVCTL_STATE 0x458
#define CONFIG_HVCTL_HV_SEQ 0x45a
#define CONFIG_HVCTL_ZEUS_SEQ 0x45c
#define CONFIG_HVCTL_RAND_NUM 0x468
#define CONFIG_HVCTL_IBUF 0x470
#define CONFIG_HVCTL_IBUF_INCR 0x8
#define CONFIG_HVCTL_OBUF 0x4b0
#define CONFIG_HVCTL_OBUF_INCR 0x8
#define CONFIG_HVCTL_IP 0x4f0
#define CONFIG_HVCTL_LDC 0x4f8
#define CONFIG_HVCTL_LDC_LOCK 0x500
#define CONFIG_CE_BLACKOUT 0x508
#define CONFIG_CE_POLL_TIME 0x510
#define CONFIG_ERRS_TO_SEND 0x518
#define CONFIG_PHYSMEMSIZE 0x520
#define CONFIG_DEL_RECONF_GID 0x528
#define CONFIG_SCRUB_SYNC 0x538
#define CONFIG_FPGA_STATUS_LOCK 0x540
#define CONFIG_L2SCRUB_INTERVAL 0x548
#define CONFIG_L2SCRUB_ENTRIES 0x550
#define CONFIG_MCONFIG 0x558
#define MAU_STORE_IN_PROGR 0x20
#define MAU_ENABLE_CWQ 0x28
#define MAU_CPU_ACTIVE 0x38
#define MAU_CPU_ACTIVE_INCR 0x1
#define CWQ_CPU_ACTIVE 0x28
#define CWQ_CPU_ACTIVE_INCR 0x1
#define RWINDOW_SIZE 0x80
#define VCPUTRAPSTATE_SIZE 0x28
#define VCTS_HTSTATE 0x20
#define VCPU_GLOBALS_SIZE 0x38
#define VCPU_GLOBALS_G 0x0
#define VCPU_GLOBALS_G_INCR 0x8
#define VCPUSTATE_SIZE 0x670
#define VS_TRAPSTACK_INCR 0x28
#define VS_GLOBALS_INCR 0x38
#define VS_STICKCOMPARE 0x1e8
#define VS_SCRATCHPAD 0x1f0
#define VS_SCRATCHPAD_INCR 0x8
#define VS_CANRESTORE 0x248
#define VS_OTHERWIN 0x250
#define VS_CLEANWIN 0x258
#define VS_WINS_INCR 0x80
#define VS_CPU_MONDO_HEAD 0x660
#define VS_CPU_MONDO_TAIL 0x662
#define VS_DEV_MONDO_HEAD 0x664
#define VS_DEV_MONDO_TAIL 0x666
#define VS_ERROR_RESUMABLE_HEAD 0x668
#define VS_ERROR_RESUMABLE_TAIL 0x66a
#define VS_ERROR_NONRESUMABLE_HEAD 0x66c
#define VS_ERROR_NONRESUMABLE_TAIL 0x66e
#define CPU_STRAND_SLOT 0x1c
#define CPU_CMD_LASTPOKE 0x80
#define CPU_CMD_ARG0 0x90
#define CPU_CMD_ARG1 0x98
#define CPU_CMD_ARG2 0xa0
#define CPU_CMD_ARG3 0xa8
#define CPU_CMD_ARG4 0xb0
#define CPU_CMD_ARG5 0xb8
#define CPU_CMD_ARG6 0xc0
#define CPU_CMD_ARG7 0xc8
#define CPU_START_PC 0xd8
#define CPU_START_ARG 0xe0
#define CPU_MMU_AREA 0xf0
#define CPU_MMU_AREA_RA 0xf8
#define CPU_CPUQ_BASE 0x100
#define CPU_CPUQ_SIZE 0x108
#define CPU_CPUQ_MASK 0x110
#define CPU_CPUQ_BASE_RA 0x118
#define CPU_DEVQ_BASE 0x120
#define CPU_DEVQ_SIZE 0x128
#define CPU_DEVQ_MASK 0x130
#define CPU_DEVQ_BASE_RA 0x138
#define CPU_DEVQ_LOCK 0x140
#define CPU_DEVQ_SHDW_TAIL 0x148
#define CPU_ERRQNR_BASE 0x150
#define CPU_ERRQNR_SIZE 0x158
#define CPU_ERRQNR_MASK 0x160
#define CPU_ERRQNR_BASE_RA 0x168
#define CPU_ERRQR_BASE 0x170
#define CPU_ERRQR_SIZE 0x178
#define CPU_ERRQR_MASK 0x180
#define CPU_ERRQR_BASE_RA 0x188
#define CPU_TTRACE_OFFSET 0x190
#define CPU_TTRACEBUF_SIZE 0x198
#define CPU_TTRACEBUF_RA 0x1a0
#define CPU_TTRACEBUF_PA 0x1a8
#define CPU_NTSBS_CTX0 0x1b0
#define CPU_NTSBS_CTXN 0x1b8
#define CPU_TSBDS_CTX0 0x1c0
#define CPU_TSBDS_CTX0_INCR 0x1
#define CPU_TSBDS_CTXN 0x240
#define CPU_TSBDS_CTXN_INCR 0x1
#define CPU_MMUSTAT_AREA 0x2c0
#define CPU_MMUSTAT_AREA_RA 0x2c8
#define CPU_SVCREGS 0x2e8
#define CPU_SVCREGS_INCR 0x8
#define CPU_LDC_INTR_PEND 0x318
#define CPU_LDC_ENDPOINT 0x320
#define CPU_STATE_SAVE_AREA 0x350
#define CPU_LAUNCH_WITH_RETRY 0x9c0
#define CPU_SCR0 (CPU_SCR + (0 * CPU_SCR_INCR))
#define CPU_SCR1 (CPU_SCR + (1 * CPU_SCR_INCR))
#define CPU_SCR2 (CPU_SCR + (2 * CPU_SCR_INCR))
#define CPU_SCR3 (CPU_SCR + (3 * CPU_SCR_INCR))
#define VCPU_UTIL_SIZE 0x28
#define VCUTIL_STICK_LAST 0x0
#define VCUTIL_YIELD_COUNT 0x8
#define VCUTIL_YIELD_START 0x10
#define CPU_UTIL_STICK_LAST (CPU_UTIL + VCUTIL_STICK_LAST)
#define CPU_UTIL_YIELD_COUNT (CPU_UTIL + VCUTIL_YIELD_COUNT)
#define CPU_UTIL_YIELD_START (CPU_UTIL + VCUTIL_YIELD_START)
#define SCHED_SLOT_SIZE 0x10
#define SCHED_SLOT_ACTION 0x0
#define SCHED_SLOT_ARG 0x8
#define HVCTL_HEADER_SIZE 0x8
#define HVCTL_HEADER_OP 0x0
#define HVCTL_MSG_SIZE 0x40
#define HVCTL_MSG_HDR 0x0
#define HVCTL_MSG_MSG 0x8
#define HVM_SCHED_SIZE 0x8
#define HVM_SCHED_VCPUP 0x0
#define HVM_SCRUB_SIZE 0x10
#define HVM_SCRUB_START_PA 0x0
#define HVM_SCRUB_START_LEN 0x8
#define HVM_GUESTCMD_SIZE 0x10
#define HVM_GUESTCMD_VCPUP 0x0
#define HVM_GUESTCMD_ARG 0x8
#define HVM_STOPGUEST_SIZE 0x8
#define HVM_STOPGUEST_GUESTP 0x0
#define HVM_FROM_STRANDP 0x8
#define XCALL_MBOX_SIZE 0x48
#define XCMB_MONDOBUF 0x8
#define XCMB_MONDOBUF_INCR 0x8
#define MINI_STACK_SIZE 0x188
#define MINI_STACK_PTR 0x0
#define MINI_STACK_VAL 0x8
#define MINI_STACK_VAL_INCR 0x8
#define PCIE_DEVICE_SIZE 0x20
#define PCIE_DEVICE_GUESTP 0x8
#define STRAND_SIZE 0x10ad0
#define STRAND_CONFIGP 0x8
#define STRAND_CURRENT_SLOT 0x10
#define STRAND_SLOT_INCR 0x10
#define STRAND_XCALL_MBOX 0x38
#define STRAND_HV_TXMONDO 0x80
#define STRAND_HV_TXMONDO_INCR 0x8
#define STRAND_HV_RXMONDO 0xc0
#define STRAND_HV_RXMONDO_INCR 0x8
#define STRAND_SCRUB_BASEPA 0x100
#define STRAND_SCRUB_SIZE 0x108
#define STRAND_MINI_STACK 0x110
#define STRAND_SCR_INCR 0x8
#define STRAND_CYCLIC 0x2d8
#define STRAND_UE_TMP1 0x520
#define STRAND_UE_TMP2 0x528
#define STRAND_UE_TMP3 0x530
#define STRAND_UE_GLOBALS 0x538
#define STRAND_UE_GLOBALS_INCR 0x40
#define STRAND_ERR_SEQ_NO 0x6b8
#define STRAND_ERR_FLAG 0x6c0
#define STRAND_DIAG_BUF 0x6c8
#define STRAND_DIAG_BUF_INCR 0x8
#define STRAND_SUN4V_RPRT_BUF 0x6f8
#define STRAND_SUN4V_RPRT_BUF_INCR 0x8
#define STRAND_ERR_TABLE_ENTRY 0x728
#define STRAND_ERR_TABLE_ENTRY_INCR 0x8
#define STRAND_ERR_ISFSR 0x758
#define STRAND_ERR_ISFSR_INCR 0x8
#define STRAND_ERR_DSFSR 0x788
#define STRAND_ERR_DSFSR_INCR 0x8
#define STRAND_ERR_DSFAR 0x7b8
#define STRAND_ERR_DSFAR_INCR 0x8
#define STRAND_ERR_DESR 0x7e8
#define STRAND_ERR_DESR_INCR 0x8
#define STRAND_ERR_DFESR 0x818
#define STRAND_ERR_DFESR_INCR 0x8
#define STRAND_ERR_RETURN_ADDR 0x848
#define STRAND_ERR_RETURN_ADDR_INCR 0x8
#define STRAND_IO_PROT 0x878
#define STRAND_IO_ERROR 0x880
#define STRAND_NRPENDING 0x888
#define STRAND_REROUTED_CPU 0x890
#define STRAND_REROUTED_EHDL 0x898
#define STRAND_REROUTED_ADDR 0x8a0
#define STRAND_REROUTED_STICK 0x8a8
#define STRAND_REROUTED_ATTR 0x8b0
#define STRAND_ABORT_PC 0x8b8
#define STRAND_ERR_GLOBALS_SAVED 0x8c0
#define STRAND_FAIL_TL 0x8d0
#define STRAND_FAIL_GL 0x8d8
#define STRAND_FAIL_TRAPSTATE 0x8e0
#define STRAND_FAIL_TRAPSTATE_INCR 0x28
#define STRAND_FAIL_TRAPGLOBALS 0x9d0
#define STRAND_FAIL_TRAPGLOBALS_INCR 0x40
#define STRAND_MRA_INCR 0x8
#define STRAND_STACK 0xad0
#define STRAND_STACK_INCR 0x8
#define STRAND_SCR0 (STRAND_SCR + (0 * STRAND_SCR_INCR))
#define STRAND_SCR1 (STRAND_SCR + (1 * STRAND_SCR_INCR))
#define STRAND_SCR2 (STRAND_SCR + (2 * STRAND_SCR_INCR))
#define STRAND_SCR3 (STRAND_SCR + (3 * STRAND_SCR_INCR))
#define STRAND_FP_TMP1 STRAND_UE_TMP1
#define STRAND_FP_TMP2 STRAND_UE_TMP2
#define STRAND_FP_TMP3 STRAND_UE_TMP3
#define STRAND_ERR_ESR_INCR STRAND_ERR_ISFSR_INCR
#define CPU_SCR0 (CPU_SCR + (0 * CPU_SCR_INCR))
#define CPU_SCR1 (CPU_SCR + (1 * CPU_SCR_INCR))
#define CPU_SCR2 (CPU_SCR + (2 * CPU_SCR_INCR))
#define CPU_SCR3 (CPU_SCR + (3 * CPU_SCR_INCR))
#define ENDOFSTACK (STACK_VAL_INCR * (STACKDEPTH + 1))
#define TOP (CPU_STACK + STACK_TOP)
#define MAPPING_SIZE 0x20
#define MAPPING_ENTRY_ALIGNED 0x0
#define MAPPING_ICPUSET 0x10
#define MAPPING_ICPUSET_INCR 0x8
#define MAPPING_DCPUSET 0x18
#define MAPPING_DCPUSET_INCR 0x8
#define MAP_ENTRY_ALIGNED_DATA 0x0
#define MAPPING_VA (MAPPING_ENTRY_ALIGNED + MAP_ENTRY_ALIGNED_DATA + MAP_DATA_VA)
#define MAPPING_TTE (MAPPING_ENTRY_ALIGNED + MAP_ENTRY_ALIGNED_DATA + MAP_DATA_TTE)
#define STACK_VAL_INCR 0x8
#define CPU_EVBSC_L2_AFSR(n) CPU_VBSC_ERPT + EVBSC_L2_AFSR + (n * EVBSC_L2_AFSR_INCR)
#define CPU_EVBSC_L2_AFAR(n) CPU_VBSC_ERPT + EVBSC_L2_AFAR + (n * EVBSC_L2_AFAR_INCR)
#define CPU_EVBSC_DRAM_AFSR(n) CPU_VBSC_ERPT + EVBSC_DRAM_AFSR + (n * EVBSC_DRAM_AFSR_INCR)
#define CPU_EVBSC_DRAM_AFAR(n) CPU_VBSC_ERPT + EVBSC_DRAM_AFAR + (n * EVBSC_DRAM_AFAR_INCR)
#define CPU_EVBSC_DRAM_CNTR(n) CPU_VBSC_ERPT + EVBSC_DRAM_CNTR + (n * EVBSC_DRAM_CNTR_INCR)
#define CPU_EVBSC_DRAM_LOC(n) CPU_VBSC_ERPT + EVBSC_DRAM_LOC + (n * EVBSC_DRAM_LOC_INCR)
#define CPU_EVBSC_DCACHE_DATA(n) DCACHE_DATA + (n * DCACHE_DATA_INCR)
#define CPU_EVBSC_ICACHE_DIAG_DATA(n) DIAG_BUF_ICACHE + ICACHE_DIAG_DATA + (n * ICACHE_DIAG_DATA_INCR)
#define PCIERPT_SYSINO 0x0
#define PCIERPT_SUN4V_EHDL 0x8
#define PCIERPT_SUN4V_STICK 0x10
#define PCIERPT_SUN4V_DESC 0x18
#define PCIERPT_SUN4V_SPECFIC 0x1c
#define PCIERPT_WORD4 0x20
#define PCIERPT_HDR1 0x28
#define PCIERPT_HDR2 0x30
#define DMU_ERR_SIZE 0xa0
#define DMU_ERR_REPORT_TYPE_62 0x0
#define DMU_ERR_FPGA_TOD 0x8
#define DMU_ERR_EHDL 0x10
#define DMU_ERR_STICK 0x18
#define DMU_ERR_CPUVER 0x20
#define DMU_ERR_AGENTID 0x28
#define DMU_ERR_MONDO_NUM 0x2c
#define DMU_ERR_DMU_CORE_AND_BLOCK_ERR_STATUS 0x30
#define DMU_ERR_IMU_ERR_LOG_ENABLE 0x38
#define DMU_ERR_IMU_INTERRUPT_ENABLE 0x40
#define DMU_ERR_IMU_ENABLED_ERR_STATUS 0x48
#define DMU_ERR_IMU_ERR_STATUS_SET 0x50
#define DMU_ERR_IMU_SCS_ERR_LOG 0x58
#define DMU_ERR_IMU_EQS_ERR_LOG 0x60
#define DMU_ERR_IMU_RDS_ERR_LOG 0x68
#define DMU_ERR_MMU_ERR_LOG_ENABLE 0x70
#define DMU_ERR_MMU_INTR_ENABLE 0x78
#define DMU_ERR_MMU_INTR_STATUS 0x80
#define DMU_ERR_MMU_ERR_STATUS_SET 0x88
#define DMU_ERR_MMU_TRANSLATION_FAULT_ADDRESS 0x90
#define DMU_ERR_MMU_TRANSLATION_FAULT_STATUS 0x98
#define PEU_ERR_SIZE 0x120
#define PCIE_ERR_REPORT_TYPE_63 0x0
#define PEU_ERR_PEU_CORE_AND_BLOCK_INTR_ENABLE 0x30
#define PEU_ERR_PEU_CORE_AND_BLOCK_INTR_STATUS 0x38
#define PEU_ERR_ILU_ERR_LOG_ENABLE 0x40
#define PEU_ERR_ILU_INTR_ENABLE 0x48
#define PEU_ERR_ILU_INTR_STATUS 0x50
#define PEU_ERR_ILU_ERR_STATUS_SET 0x58
#define PEU_ERR_PEU_OTHER_EVENT_LOG_ENABLE 0x60
#define PEU_ERR_PEU_OTHER_EVENT_INTR_ENABLE 0x68
#define PEU_ERR_PEU_OTHER_EVENT_INTR_STATUS 0x70
#define PEU_ERR_PEU_OTHER_EVENT_STATUS_SET 0x78
#define PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER1_LOG 0x80
#define PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER2_LOG 0x88
#define PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER1_LOG 0x90
#define PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER2_LOG 0x98
#define PEU_ERR_PEU_UE_LOG_ENABLE 0xa0
#define PEU_ERR_PEU_UE_INTERRUPT_ENABLE 0xa8
#define PEU_ERR_PEU_UE_STATUS 0xb0
#define PEU_ERR_PEU_UE_STATUS_SET 0xb8
#define PEU_ERR_PEU_RECEIVE_UE_HEADER1_LOG 0xc0
#define PEU_ERR_PEU_RECEIVE_UE_HEADER2_LOG 0xc8
#define PEU_ERR_PEU_TRANSMIT_UE_HEADER1_LOG 0xd0
#define PEU_ERR_PEU_TRANSMIT_UE_HEADER2_LOG 0xd8
#define PEU_ERR_PEU_CE_LOG_ENABLE 0xe0
#define PEU_ERR_PEU_CE_INTERRUPT_ENABLE 0xe8
#define PEU_ERR_PEU_CE_INTERRUPT_STATUS 0xf0
#define PEU_ERR_PEU_CE_STATUS_SET 0xf8
#define PEU_ERR_PEU_CXPL_EVENT_ERROR_LOG_ENABLE 0x100
#define PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_ENABLE 0x108
#define PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_STATUS 0x110
#define PEU_ERR_PEU_CXPL_EVENT_ERROR_STATUS_SET 0x118
#define PCIERPT_SIZE 0x168
#define PCI_ERPT_PCIEPKT 0x0
#define PCI_UNSENT_PKT 0x160
#define PCIERPT_REPORT_TYPE_62 (PCI_ERPT_U + DMU_ERR_REPORT_TYPE_62)
#define PCIERPT_FPGA_TOD (PCI_ERPT_U + DMU_ERR_FPGA_TOD)
#define PCIERPT_EHDL (PCI_ERPT_U + DMU_ERR_EHDL)
#define PCIERPT_STICK (PCI_ERPT_U + DMU_ERR_STICK)
#define PCIERPT_CPUVER (PCI_ERPT_U + DMU_ERR_CPUVER )
#define PCIERPT_AGENTID (PCI_ERPT_U + DMU_ERR_AGENTID)
#define PCIERPT_MONDO_NUM (PCI_ERPT_U + DMU_ERR_MONDO_NUM)
#define PCIERPT_DMU_CORE_AND_BLOCK_ERR_STATUS (PCI_ERPT_U + DMU_ERR_DMU_CORE_AND_BLOCK_ERR_STATUS)
#define PCIERPT_IMU_ERR_LOG_ENABLE (PCI_ERPT_U + DMU_ERR_IMU_ERR_LOG_ENABLE)
#define PCIERPT_IMU_INTERRUPT_ENABLE (PCI_ERPT_U + DMU_ERR_IMU_INTERRUPT_ENABLE)
#define PCIERPT_IMU_ENABLED_ERR_STATUS (PCI_ERPT_U + DMU_ERR_IMU_ENABLED_ERR_STATUS)
#define PCIERPT_IMU_ERR_STATUS_SET (PCI_ERPT_U + DMU_ERR_IMU_ERR_STATUS_SET)
#define PCIERPT_IMU_SCS_ERR_LOG (PCI_ERPT_U + DMU_ERR_IMU_SCS_ERR_LOG)
#define PCIERPT_IMU_EQS_ERR_LOG (PCI_ERPT_U + DMU_ERR_IMU_EQS_ERR_LOG)
#define PCIERPT_IMU_RDS_ERR_LOG (PCI_ERPT_U + DMU_ERR_IMU_RDS_ERR_LOG)
#define PCIERPT_MMU_ERR_LOG_ENABLE (PCI_ERPT_U + DMU_ERR_MMU_ERR_LOG_ENABLE)
#define PCIERPT_MMU_INTR_ENABLE (PCI_ERPT_U + DMU_ERR_MMU_INTR_ENABLE)
#define PCIERPT_MMU_INTR_STATUS (PCI_ERPT_U + DMU_ERR_MMU_INTR_STATUS)
#define PCIERPT_MMU_ERR_STATUS_SET (PCI_ERPT_U + DMU_ERR_MMU_ERR_STATUS_SET)
#define PCIERPT_MMU_TRANSLATION_FAULT_ADDRESS (PCI_ERPT_U + DMU_ERR_MMU_TRANSLATION_FAULT_ADDRESS)
#define PCIERPT_MMU_TRANSLATION_FAULT_STATUS (PCI_ERPT_U + DMU_ERR_MMU_TRANSLATION_FAULT_STATUS)
#define PCIERPT_REPORT_TYPE_63 (PCI_ERPT_U + PCIE_ERR_REPORT_TYPE_63)
#define PCIERPT_PEU_CORE_AND_BLOCK_INTR_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CORE_AND_BLOCK_INTR_ENABLE)
#define PCIERPT_PEU_CORE_AND_BLOCK_INTR_STATUS (PCI_ERPT_U + PEU_ERR_PEU_CORE_AND_BLOCK_INTR_STATUS)
#define PCIERPT_ILU_ERR_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_ILU_ERR_LOG_ENABLE)
#define PCIERPT_ILU_INTR_ENABLE (PCI_ERPT_U + PEU_ERR_ILU_INTR_ENABLE)
#define PCIERPT_ILU_INTR_STATUS (PCI_ERPT_U + PEU_ERR_ILU_INTR_STATUS)
#define PCIERPT_ILU_ERR_STATUS_SET (PCI_ERPT_U + PEU_ERR_ILU_ERR_STATUS_SET)
#define PCIERPT_PEU_OTHER_EVENT_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_LOG_ENABLE)
#define PCIERPT_PEU_OTHER_EVENT_INTR_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_INTR_ENABLE)
#define PCIERPT_PEU_OTHER_EVENT_INTR_STATUS (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_INTR_STATUS)
#define PCIERPT_PEU_OTHER_EVENT_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_STATUS_SET)
#define PCIERPT_PEU_RECEIVE_OTHER_EVENT_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER1_LOG)
#define PCIERPT_PEU_RECEIVE_OTHER_EVENT_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER2_LOG)
#define PCIERPT_PEU_TRANSMIT_OTHER_EVENT_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER1_LOG)
#define PCIERPT_PEU_TRANSMIT_OTHER_EVENT_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER2_LOG)
#define PCIERPT_PEU_UE_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_UE_LOG_ENABLE)
#define PCIERPT_PEU_UE_INTERRUPT_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_UE_INTERRUPT_ENABLE)
#define PCIERPT_PEU_UE_STATUS (PCI_ERPT_U + PEU_ERR_PEU_UE_STATUS)
#define PCIERPT_PEU_UE_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_UE_STATUS_SET)
#define PCIERPT_PEU_RECEIVE_UE_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_UE_HEADER1_LOG)
#define PCIERPT_PEU_RECEIVE_UE_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_UE_HEADER2_LOG)
#define PCIERPT_PEU_TRANSMIT_UE_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_UE_HEADER1_LOG)
#define PCIERPT_PEU_TRANSMIT_UE_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_UE_HEADER2_LOG)
#define PCIERPT_PEU_CE_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CE_LOG_ENABLE)
#define PCIERPT_PEU_CE_INTERRUPT_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CE_INTERRUPT_ENABLE)
#define PCIERPT_PEU_CE_INTERRUPT_STATUS (PCI_ERPT_U + PEU_ERR_PEU_CE_INTERRUPT_STATUS)
#define PCIERPT_PEU_CE_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_CE_STATUS_SET)
#define PCIERPT_PEU_CXPL_EVENT_ERROR_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_LOG_ENABLE)
#define PCIERPT_PEU_CXPL_EVENT_ERROR_INT_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_ENABLE)
#define PCIERPT_PEU_CXPL_EVENT_ERROR_INT_STATUS (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_STATUS)
#define PCIERPT_PEU_CXPL_EVENT_ERROR_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_STATUS_SET)
#define LDC_CONSPKT_SIZE 0x40
#define LDC_CONS_TYPE 0x0
#define LDC_CONS_SIZE 0x1
#define LDC_CONS_CTRL_MSG 0x4
#define LDC_CONS_PAYLOAD 0x8
#define LDC_CONS_PAYLOAD_INCR 0x1
#define CONSOLE_SIZE 0x248
#define CONS_UARTBASE 0x18
#define CONS_VINTR_MAPREG 0x40
#define CONS_INBUF_INCR 0x8
#define LDC_ENDPOINT_SIZE 0x110
#define LDC_IS_PRIVATE 0x2
#define LDC_IS_SVC_ID 0x3
#define LDC_RX_UPDATED 0x4
#define LDC_TX_QBASE_RA 0x8
#define LDC_TX_QBASE_PA 0x10
#define LDC_TX_QSIZE 0x18
#define LDC_TX_QHEAD 0x20
#define LDC_TX_QTAIL 0x24
#define LDC_TX_CBARG 0x30
#define LDC_TX_MAPREG 0x38
#define LDC_RX_QBASE_RA 0x60
#define LDC_RX_QBASE_PA 0x68
#define LDC_RX_QSIZE 0x70
#define LDC_RX_QHEAD 0x78
#define LDC_RX_QTAIL 0x7c
#define LDC_RX_CBARG 0x88
#define LDC_RX_MAPREG 0x90
#define LDC_RX_VINTR_COOKIE 0xb8
#define LDC_TARGET_TYPE 0xc0
#define LDC_TARGET_GUEST 0xc8
#define LDC_TARGET_CHANNEL 0xd0
#define LDC_MAP_TABLE_RA 0xd8
#define LDC_MAP_TABLE_PA 0xe0
#define LDC_MAP_TABLE_NENTRIES 0xe8
#define LDC_MAP_TABLE_SZ 0xf0
#define VERSION_SIZE 0x10
#define VERSION_MAJOR (VERSION_NUM+MAJOR_OFF)
#define VERSION_MINOR (VERSION_NUM+MINOR_OFF)
#define LDC_MAPREG_SIZE 0x28
#define LDC_MAPREG_STATE 0x0
#define LDC_MAPREG_VALID 0x4
#define LDC_MAPREG_INO 0x8
#define LDC_MAPREG_CPUP 0x10
#define LDC_MAPREG_COOKIE 0x18
#define LDC_MAPREG_ENDPOINT 0x20
#define WATCHDOG_TICKS 0x0
#define LDC_I2E_SIZE 0x10
#define LDC_I2E_ENDPOINT 0x0
#define LDC_I2E_MAPREG 0x8
#define SP_LDC_ENDPOINT_SIZE 0xe8
#define LDC_CHANNEL_IDX 0x0
#define SP_LDC_IS_LIVE 0x1
#define SP_LDC_TARGET_TYPE 0x2
#define SP_LDC_TX_QD_PA 0x8
#define SP_LDC_RX_QD_PA 0x10
#define SP_LDC_TARGET_GUEST 0x18
#define SP_LDC_TARGET_CHANNEL 0x20
#define SP_LDC_TX_LOCK 0x28
#define SP_LDC_RX_LOCK 0x30
#define SP_LDC_TX_SCR_TXHEAD 0x38
#define SP_LDC_TX_SCR_TXTAIL 0x3c
#define SP_LDC_TX_SCR_TXSIZE 0x40
#define SP_LDC_TX_SCR_TX_QPA 0x48
#define SP_LDC_TX_SCR_RXHEAD 0x50
#define SP_LDC_TX_SCR_RXTAIL 0x54
#define SP_LDC_TX_SCR_RXSIZE 0x58
#define SP_LDC_TX_SCR_RX_QPA 0x60
#define SP_LDC_TX_SCR_TARGET 0x68
#define SP_LDC_RX_SCR_TXHEAD 0x70
#define SP_LDC_RX_SCR_TXTAIL 0x74
#define SP_LDC_RX_SCR_TXSIZE 0x78
#define SP_LDC_RX_SCR_TX_QPA 0x80
#define SP_LDC_RX_SCR_RXHEAD 0x88
#define SP_LDC_RX_SCR_RXTAIL 0x8c
#define SP_LDC_RX_SCR_RXSIZE 0x90
#define SP_LDC_RX_SCR_RX_QPA 0x98
#define SP_LDC_RX_SCR_TARGET 0xa0
#define SP_LDC_RX_SCR_PKT 0xa8
#define SRAM_LDC_QENTRY_SIZE 0x40
#define SRAM_LDC_PKT_DATA 0x0
#define SRAM_LDC_PKT_DATA_INCR 0x8
#define SRAM_LDC_QD_SIZE 0x140
#define SRAM_LDC_HEAD 0x100
#define SRAM_LDC_TAIL 0x101
#define SRAM_LDC_STATE 0x102
#define SRAM_LDC_STATE_UPDATED 0x103
#define SRAM_LDC_STATE_NOTIFY 0x104
#define LDC_MAPIN_SIZE 0x30
#define LDC_MI_MMU_MAP 0x8
#define LDC_MI_IO_VA 0x10
#define LDC_MI_VA_CTX 0x20
#define LDC_MI_LOCAL_ENDPOINT 0x22
#define LDC_MI_PG_SIZE 0x24
#define LDC_MI_PERMS 0x25
#define LDC_MI_MAP_TABLE_IDX 0x28
#define LDC_MI_NEXT_IDX 0 /* clobber 1st word when free */
#define MIE_VA_MMU_SHIFT 0
#define MIE_RA_MMU_SHIFT 8
#define MIE_IO_MMU_SHIFT 16
#define LDC_MI_VA_MMU_MAP (LDC_MI_MMU_MAP + 7)
#define LDC_MI_RA_MMU_MAP (LDC_MI_MMU_MAP + 6)
#define LDC_MI_IO_MMU_MAP (LDC_MI_MMU_MAP + 5)
#define GUEST_CONS_QUEUES_SIZE 0x4000
#define GUEST_CONS_RXQ 0x0
#define GUEST_CONS_RXQ_INCR 0x1
#define GUEST_CONS_TXQ 0x2000
#define GUEST_CONS_TXQ_INCR 0x1
#define RA2PA_SEGMENT_SIZE 0x20
#define RA2PA_SEGMENT_BASE 0x0
#define RA2PA_SEGMENT_LIMIT 0x8
#define RA2PA_SEGMENT_OFFSET 0x10
#define RA2PA_SEGMENT_FLAGS 0x18
#define GUEST_SIZE 0x45910
#define GUEST_CONFIGP 0x8
#define GUEST_STATE_LOCK 0x18
#define GUEST_SOFT_STATE 0x20
#define GUEST_SOFT_STATE_STR 0x21
#define GUEST_SOFT_STATE_STR_INCR 0x1
#define GUEST_SOFT_STATE_LOCK 0x48
#define GUEST_REAL_BASE 0x50
#define GUEST_REAL_LIMIT 0x58
#define GUEST_MEM_OFFSET 0x60
#define GUEST_RA2PA_SEGMENT 0x68
#define GUEST_RA2PA_SEGMENT_INCR 0x20
#define GUEST_LDC_MAPIN_BASERA 0x868
#define GUEST_LDC_MAPIN_SIZE 0x870
#define GUEST_PERM_MAPPINGS_LOCK 0x878
#define GUEST_PERM_MAPPINGS 0x880
#define GUEST_PERM_MAPPINGS_INCR 0x20
#define GUEST_CONSOLE 0x980
#define GUEST_TOD_OFFSET 0xbc8
#define GUEST_TTRACE_FRZ 0xbd0
#define GUEST_VCPUS 0xbd8
#define GUEST_VCPUS_INCR 0x8
#define GUEST_MAUS_INCR 0x8
#define GUEST_CWQS_INCR 0x8
#define GUEST_API_GROUPS 0xe58
#define GUEST_API_GROUPS_INCR 0x10
#define GUEST_HCALL_TABLE 0xf28
#define GUEST_DEV2INST 0xf30
#define GUEST_DEV2INST_INCR 0x1
#define GUEST_VINO2INST 0xf50
#define GUEST_VDEV_STATE 0x1750
#define GUEST_MD_PA 0x2760
#define GUEST_MD_SIZE 0x2768
#define GUEST_DUMPBUF_PA 0x2770
#define GUEST_DUMPBUF_RA 0x2778
#define GUEST_DUMPBUF_SIZE 0x2780
#define GUEST_ENTRY 0x2788
#define GUEST_ROM_BASE 0x2790
#define GUEST_ROM_SIZE 0x2798
#define GUEST_PERFREG_ACCESSIBLE 0x27a0
#define GUEST_DIAGPRIV 0x27a8
#define GUEST_RESET_REASON 0x27b0
#define GUEST_PERFREGHT_ACCESSIBLE 0x27b8
#define GUEST_RNG_CTL_ACCESSIBLE 0x27c0
#define GUEST_WATCHDOG 0x27c8
#define GUEST_DISK 0x27d0
#define GUEST_LDC_MAX_CHANNEL_IDX 0x27e0
#define GUEST_LDC_MAPIN_FREE_IDX 0x27e8
#define GUEST_LDC_ENDPOINT 0x27f0
#define GUEST_LDC_ENDPOINT_INCR 0x110
#define GUEST_LDC_MAPIN 0x137f0
#define GUEST_LDC_MAPIN_INCR 0x30
#define GUEST_LDC_I2E 0x437f0
#define GUEST_LDC_I2E_INCR 0x10
#define GUEST_ASYNC_BUSY 0x45878
#define GUEST_ASYNC_BUSY_INCR 0x1
#define GUEST_ASYNC_LOCK 0x45880
#define GUEST_ASYNC_LOCK_INCR 0x8
#define GUEST_ASYNC_BUF 0x458a0
#define GUEST_ASYNC_BUF_INCR 0x8
#define GUEST_START_STICK 0x458e0
#define GUEST_UTIL 0x458e8
#define GUEST_MGUEST 0x45908
#define GUEST_UTIL_SIZE 0x10
#define GUTIL_STICK_LAST 0x0
#define GUTIL_STOPPED_CYCLES 0x8
#define HVCTL_RES_STATUS_SIZE 0x38
#define HVCTL_RES_STATUS_RES 0x0
#define HVCTL_RES_STATUS_RESID 0x4
#define HVCTL_RES_STATUS_INFOID 0x8
#define HVCTL_RES_STATUS_CODE 0xc
#define HVCTL_RES_STATUS_DATA 0x10
#define HVCTL_RES_STATUS_DATA_INCR 0x1
#define RS_GUEST_SOFT_STATE_SIZE 0x21
#define RS_GUEST_SOFT_STATE 0x0
#define RS_GUEST_SOFT_STATE_STR 0x1
#define RS_GUEST_SOFT_STATE_STR_INCR 0x1
#define DEVOPSVEC_SIZE 0x180
#define DEVOPSVEC_DEVINO2VINO 0x0
#define DEVOPSVEC_MONDO_RECEIVE 0x8
#define DEVOPSVEC_GETVALID 0x10
#define DEVOPSVEC_SETVALID 0x18
#define DEVOPSVEC_GETSTATE 0x20
#define DEVOPSVEC_SETSTATE 0x28
#define DEVOPSVEC_GETTARGET 0x30
#define DEVOPSVEC_SETTARGET 0x38
#define DEVOPSVEC_MAP 0x40
#define DEVOPSVEC_MAP_V2 0x48
#define DEVOPSVEC_GETMAP 0x50
#define DEVOPSVEC_GETMAP_V2 0x58
#define DEVOPSVEC_UNMAP 0x60
#define DEVOPSVEC_GETBYPASS 0x68
#define DEVOPSVEC_CONFIGGET 0x70
#define DEVOPSVEC_CONFIGPUT 0x78
#define DEVOPSVEC_IOPEEK 0x80
#define DEVOPSVEC_IOPOKE 0x88
#define DEVOPSVEC_DMASYNC 0x90
#define DEVOPSVEC_MSIQ_CONF 0x98
#define DEVOPSVEC_MSIQ_INFO 0xa0
#define DEVOPSVEC_MSIQ_GETVALID 0xa8
#define DEVOPSVEC_MSIQ_SETVALID 0xb0
#define DEVOPSVEC_MSIQ_GETSTATE 0xb8
#define DEVOPSVEC_MSIQ_SETSTATE 0xc0
#define DEVOPSVEC_MSIQ_GETHEAD 0xc8
#define DEVOPSVEC_MSIQ_SETHEAD 0xd0
#define DEVOPSVEC_MSIQ_GETTAIL 0xd8
#define DEVOPSVEC_MSI_GETVALID 0xe0
#define DEVOPSVEC_MSI_SETVALID 0xe8
#define DEVOPSVEC_MSI_GETSTATE 0xf0
#define DEVOPSVEC_MSI_SETSTATE 0xf8
#define DEVOPSVEC_MSI_GETMSIQ 0x100
#define DEVOPSVEC_MSI_SETMSIQ 0x108
#define DEVOPSVEC_MSI_MSG_GETMSIQ 0x110
#define DEVOPSVEC_MSI_MSG_SETMSIQ 0x118
#define DEVOPSVEC_MSI_MSG_GETVALID 0x120
#define DEVOPSVEC_MSI_MSG_SETVALID 0x128
#define DEVOPSVEC_GETPERFREG 0x130
#define DEVOPSVEC_SETPERFREG 0x138
#define DEVOPSVEC_VGETCOOKIE 0x140
#define DEVOPSVEC_VSETCOOKIE 0x148
#define DEVOPSVEC_VGETVALID 0x150
#define DEVOPSVEC_VSETVALID 0x158
#define DEVOPSVEC_VGETTARGET 0x160
#define DEVOPSVEC_VSETTARGET 0x168
#define DEVOPSVEC_VGETSTATE 0x170
#define DEVOPSVEC_VSETSTATE 0x178
#define VINO2INST_SIZE 0x800
#define VINO2INST_VINO 0x0
#define VINO2INST_VINO_INCR 0x1
#define PIU_COOKIE_SIZE 0x3c0
#define PIU_COOKIE_HANDLE 0x0
#define PIU_COOKIE_NCU 0x8
#define PIU_COOKIE_PCIE 0x10
#define PIU_COOKIE_CFG 0x18
#define PIU_COOKIE_PERFREGS 0x30
#define PIU_COOKIE_EQCTLSET 0x38
#define PIU_COOKIE_EQCTLCLR 0x40
#define PIU_COOKIE_EQSTATE 0x48
#define PIU_COOKIE_EQTAIL 0x50
#define PIU_COOKIE_EQHEAD 0x58
#define PIU_COOKIE_MSIMAP 0x60
#define PIU_COOKIE_MSICLR 0x68
#define PIU_COOKIE_MSGMAP 0x70
#define PIU_COOKIE_MMUFLUSH 0x80
#define PIU_COOKIE_INTCLR 0x88
#define PIU_COOKIE_INTMAP 0x90
#define PIU_COOKIE_VIRTUAL_INTMAP 0x98
#define PIU_COOKIE_ERR_LOCK 0xa0
#define PIU_COOKIE_ERR_LOCK_COUNTER 0xa8
#define PIU_COOKIE_OE_STATUS 0xb0
#define PIU_COOKIE_INOMAX 0xb8
#define PIU_COOKIE_VINO 0xba
#define PIU_COOKIE_IOTSB0 0xc0
#define PIU_COOKIE_IOTSB1 0xc8
#define PIU_COOKIE_MSIEQBASE 0xd0
#define PIU_COOKIE_MSICOOKIE 0xd8
#define PIU_COOKIE_ERRCOOKIE 0xe0
#define PIU_COOKIE_DMU_ERPT 0xe8
#define PIU_COOKIE_PEU_ERPT 0x250
#define PIU_COOKIE_BLACKLIST 0x3b8
#define PIU_MSIEQ_SIZE 0x28
#define PIU_MSIEQ_EQMASK 0x0
#define PIU_MSIEQ_BASE 0x8
#define PIU_MSIEQ_GUEST 0x10
#define PIU_MSIEQ_WORD0 0x18
#define PIU_MSIEQ_WORD1 0x20
#define PIU_MSI_COOKIE_SIZE 0x5a8
#define PIU_MSI_COOKIE_PIU 0x0
#define PIU_MSI_COOKIE_EQ 0x8
#define PIU_MSI_COOKIE_EQ_INCR 0x28
#define PIU_ERR_COOKIE_SIZE 0x18
#define PIU_ERR_COOKIE_PIU 0x0
#define PIU_ERR_COOKIE_STATE 0x8
#define PIU_ERR_COOKIE_STATE_INCR 0x8
#define VDEV_STATE_SIZE 0x1010
#define VDEV_STATE_HANDLE 0x0
#define VDEV_STATE_MAPREG 0x8
#define VDEV_STATE_MAPREG_INCR 0x40
#define VDEV_STATE_INOMAX 0x1008
#define VDEV_STATE_VINOBASE 0x100a
#define SVC_LINK_SIZE 0x0
#define SVC_LINK_NEXT 0x10
#define SVC_CALLBACK_RX 0x0
#define SVC_CALLBACK_TX 0x8
#define SVC_CALLBACK_COOKIE 0x10
#define SVC_CTRL_SIZE 0x80
#define SVC_CTRL_CONFIG 0x10
#define SVC_CTRL_STATE 0x14
#define SVC_CTRL_COUNT 0x18
#define SVC_CTRL_DSTATE 0x1c
#define SVC_CTRL_LOCK 0x20
#define SVC_CTRL_INTR_COOKIE 0x28
#define SVC_CTRL_CALLBACK 0x30
#define SVC_CTRL_LINK 0x48
#define SVC_CTRL_RECV 0x50
#define SVC_CTRL_SEND 0x68
#define HV_SVC_DATA_SIZE 0x4e0
#define HV_SVC_DATA_RXBASE 0x0
#define HV_SVC_DATA_TXBASE 0x8
#define HV_SVC_DATA_RXCHANNEL 0x10
#define HV_SVC_DATA_TXCHANNEL 0x18
#define HV_SVC_DATA_SCR 0x20
#define HV_SVC_DATA_SCR_INCR 0x8
#define HV_SVC_DATA_NUM_SVCS 0x30
#define HV_SVC_DATA_SENDBUSY 0x34
#define HV_SVC_DATA_SENDH 0x38
#define HV_SVC_DATA_SENDT 0x40
#define HV_SVC_DATA_SENDDH 0x48
#define HV_SVC_DATA_SENDDT 0x50
#define HV_SVC_DATA_LOCK 0x58
#define HV_SVC_DATA_SVC 0x60
#define HV_SVC_DATA_SVC_INCR 0x80
#define MAPREG_DEVCOOKIE 0x10
#define MAPREG_GETSTATE 0x18
#define MAPREG_SETSTATE 0x20
#define TRAPGLOBALS_SIZE 0x40
#define TRAPGLOBALS_SHIFT 0x6
#define TRAPSTATE_SIZE 0x28
#define TRAPSTATE_HTSTATE 0x0
#define TRAPSTATE_TSTATE 0x8
#define TRAPSTATE_TT 0x10
#define TRAPSTATE_TPC 0x18
#define TRAPSTATE_TNPC 0x20
#define DBGERROR_PAYLOAD_SIZE 0x1f8
#define DBGERROR_DATA 0x0
#define DBGERROR_DATA_INCR 0x8
#define DBGERROR_SIZE 0x200
#define DBGERROR_ERROR_SVCH 0x0
#define DBGERROR_PAYLOAD 0x8
#define DEVINST_SIZE 0x10
#define DEVINST_SIZE_SHIFT 0x4
#define DEVINST_COOKIE 0x0
#define ERPT_SVC_PKT_SIZE 0x10
#define ERPT_PKT_ADDR 0x0
#define ERPT_PKT_SIZE 0x8
#define MAU_QUEUE_SIZE 0x50
#define MQ_HEAD_MARKER 0x30
#define CWQ_QUEUE_SIZE 0x10d0
#define CQ_DR_BASE_RA 0x10
#define CQ_HEAD_MARKER 0x50
#define CQ_DR_HV_OFFSET 0x88
#define CQ_HV_CWS_INCR 0x40
#define NCS_HVDESC_SIZE 0x40
#define NCS_HVDESC_SHIFT 0x6
#define NHD_ERRSTATUS 0x30
#define MA_REGS_SIZE 0x20
#define NCS_QCONF_ARG_SIZE 0x20
#define NCS_QTAIL_UPDATE_ARG_SIZE 0x18
#define CWQ_CW_RET_SIZE 0x8
#define CW_RET_DST_ADDR 0x0
#define CW_AUTH_KEY_ADDR 0x10
#define CW_AUTH_IV_ADDR 0x18
#define CW_FINAL_AUTH_STATE_ADDR 0x20
#define CW_ENC_KEY_ADDR 0x28
#define CW_ENC_IV_ADDR 0x30
#define CW_DST_ADDR (CW_RET + CW_RET_DST_ADDR)
#define CW_CSR (CW_RET + CW_RET_DST_ADDR)
#define CRYPTO_INTR_SIZE 0x18
#define RNG_CTLREGS_SIZE 0x20
#define RNG_CTLREGS_REG0 0x0
#define RNG_CTLREGS_REG1 0x8
#define RNG_CTLREGS_REG2 0x10
#define RNG_CTLREGS_REG3 0x18
#define RNG_CTLDATA_SIZE 0x38
#define RNG_CTLDATA_REGS 0x0
#define RNG_CTLDATA_STATE 0x20
#define RNG_CTLDATA_GUESTID 0x28
#define RNG_CTLDATA_READYTIME 0x30
#define SVCCN_PKT_SIZE 0x3
#define SVCCN_PKT_TYPE 0x0
#define SVCCN_PKT_LEN 0x1
#define SVCCN_PKT_DATA 0x2
#define SVCCN_PKT_DATA_INCR 0x1
#define VBSC_CTRL_PKT_SIZE 0x20
#define VBSC_PKT_ARG0 0x8
#define VBSC_PKT_ARG1 0x10
#define VBSC_PKT_ARG2 0x18
#define STRAND_CY_T0 (STRAND_CYCLIC + CY_T0)
#define STRAND_CY_CB (STRAND_CYCLIC + CY_CB)
#define STRAND_CY_TICK (STRAND_CYCLIC + CY_TICK)
#define STRAND_CY_HANDLER (STRAND_CYCLIC + CY_HANDLER)
#define STRAND_CY_ARG0 (STRAND_CYCLIC + CY_ARG0)
#define STRAND_CY_ARG1 (STRAND_CYCLIC + CY_ARG1)
#define STRAND_CY_CB_TICK (STRAND_CYCLIC + CY_CB + CB_TICK)
#define STRAND_CY_CB_HANDLER (STRAND_CYCLIC + CY_CB + CB_HANDLER)
#define STRAND_CY_CB_ARG0 (STRAND_CYCLIC + CY_CB + CB_ARG0)
#define STRAND_CY_CB_ARG1 (STRAND_CYCLIC + CY_CB + CB_ARG1)
#define CB_LAST ((N_CB - 1) * CB_SIZE)
#define STRAND_CY_CB_LAST_TICK (STRAND_CY_CB_TICK + CB_LAST)
#define ERROR_TABLE_ENTRY_SIZE 0x48
#define ERR_NAME_INCR 0x1
#define ERR_REPORT_FCN 0x10
#define ERR_GUEST_REPORT_FCN 0x18
#define ERR_CORRECT_FCN 0x20
#define ERR_STORM_FCN 0x28
#define ERR_PRINT_FCN 0x30
#define ERR_SUN4V_RPRT_TYPE 0x3c
#define ERR_SUN4V_EDESC 0x3d
#define ERR_REPORT_SIZE 0x40
#define ERR_WAY_SIZE 0x88
#define ERR_WAY_TAG_AND_ECC 0x0
#define ERR_WAY_DATA_AND_ECC 0x8
#define ERR_WAY_DATA_AND_ECC_INCR 0x8
#define ERR_L2_SIZE 0x8d0
#define ERR_L2_VDBITS 0x0
#define ERR_L2_UABITS 0x8
#define ERR_L2_WAYS_INCR 0x88
#define ERR_DRAM_CONTENTS 0x890
#define ERR_DRAM_CONTENTS_INCR 0x8
#define ERR_TLB_SIZE 0x10
#define ERR_ICACHE_WAY_SIZE 0x48
#define ERR_ICACHE_WAY_INSTR 0x0
#define ERR_ICACHE_WAY_INSTR_INCR 0x8
#define ERR_ICACHE_WAY_TAG 0x40
#define ERR_ICACHE_SIZE 0x240
#define ERR_ICACHE_WAY 0x0
#define ERR_ICACHE_WAY_INCR 0x48
#define ERR_DCACHE_WAY_SIZE 0x18
#define ERR_DCACHE_WAY_DATA 0x0
#define ERR_DCACHE_WAY_DATA_INCR 0x8
#define ERR_DCACHE_WAY_TAG 0x10
#define ERR_DCACHE_SIZE 0x60
#define ERR_DCACHE_WAY 0x0
#define ERR_DCACHE_WAY_INCR 0x18
#define ERR_SSI_SIZE 0x10
#define ERR_SSI_TIMEOUT 0x0
#define ERR_STB_SIZE 0x28
#define ERR_STB_DATA_ECC 0x8
#define ERR_STB_PARITY 0x10
#define ERR_STB_MARKS 0x18
#define ERR_STB_CURR_PTR 0x20
#define ERR_SCRATCHPAD_SIZE 0x10
#define ERR_SCRATCHPAD_DATA 0x0
#define ERR_SCRATCHPAD_ECC 0x8
#define ERR_TCA_SIZE 0x10
#define ERR_TSA_SIZE 0x78
#define ERR_TSA_TSTATE 0x18
#define ERR_TSA_HTSTATE 0x20
#define ERR_TSA_TNPC 0x30
#define ERR_TSA_CPU_MONDO_QHEAD 0x38
#define ERR_TSA_CPU_MONDO_QTAIL 0x40
#define ERR_TSA_DEV_MONDO_QHEAD 0x48
#define ERR_TSA_DEV_MONDO_QTAIL 0x50
#define ERR_TSA_ERR_RES_QHEAD 0x58
#define ERR_TSA_ERR_RES_QTAIL 0x60
#define ERR_TSA_ERR_NONRES_QHEAD 0x68
#define ERR_TSA_ERR_NONRES_QTAIL 0x70
#define ERR_MMU_ERR_REGS_SIZE 0x88
#define ERR_MMU_PARITY 0x0
#define ERR_MMU_PARITY_INCR 0x1
#define ERR_MMU_TSB_CFG_CTX0 0x8
#define ERR_MMU_TSB_CFG_CTX0_INCR 0x8
#define ERR_MMU_TSB_CFG_CTXNZ 0x28
#define ERR_MMU_TSB_CFG_CTXNZ_INCR 0x8
#define ERR_MMU_REAL_RANGE 0x48
#define ERR_MMU_REAL_RANGE_INCR 0x8
#define ERR_MMU_PHYS_OFFSET 0x68
#define ERR_MMU_PHYS_OFFSET_INCR 0x8
#define ERR_MAMU_SIZE 0x28
#define ERR_TRAP_REGS_SIZE 0x28
#define ERR_SOC_SIZE 0x48
#define ERR_SOC_EIER 0x10
#define ERR_SOC_VCID 0x18
#define ERR_SOC_FEER 0x20
#define ERR_SOC_PESR 0x28
#define ERR_SOC_SII_SYND 0x38
#define ERR_SOC_NCU_SYND 0x40
#define ERR_DIAG_DATA_SIZE 0x8d0
#define ERR_DIAG_DATA_DTLB 0x0
#define ERR_DIAG_DATA_DTLB_INCR 0x10
#define ERR_DIAG_DATA_ITLB 0x0
#define ERR_DIAG_DATA_ITLB_INCR 0x10
#define ERR_DIAG_DATA_ICACHE 0x0
#define ERR_DIAG_DATA_DCACHE 0x0
#define ERR_DIAG_DATA_SSI_INFO 0x0
#define ERR_DIAG_DATA_STB 0x0
#define ERR_DIAG_DATA_SCRATCHPAD 0x0
#define ERR_DIAG_DATA_TSA 0x0
#define ERR_DIAG_DATA_MMU_REGS 0x0
#define ERR_DIAG_DATA_MAMU 0x0
#define ERR_DIAG_DATA_SOC 0x0
#define ERR_DIAG_DATA_TCA 0x0
#define ERR_DIAG_DATA_REG 0x0
#define ERR_DIAG_DATA_L2_CACHE 0x0
#define ERR_DIAG_DATA_TRAP_REGS 0x0
#define ERR_DIAG_DATA_TRAP_REGS_INCR 0x28
#define ERR_DIAG_DATA_REG_INFO 0x0
#define ERR_ABORT_DATA_SIZE 0x800
#define ERR_ABORT_VERSION 0x0
#define ERR_ABORT_VERSION_INCR 0x1
#define ERR_ABORT_PC 0x40
#define ERR_ABORT_CWP 0x48
#define ERR_ABORT_TRAP_REGS 0x50
#define ERR_ABORT_TRAP_REGS_INCR 0x28
#define ERR_ABORT_GLOBAL_REGS 0x140
#define ERR_ABORT_GLOBAL_REGS_INCR 0x8
#define ERR_ABORT_REG_WINDOWS 0x200
#define ERR_ABORT_REG_WINDOWS_INCR 0x8
#define ERR_DIAG_BUF_SIZE 0xa98
#define ERR_DIAG_BUF_SPARC_ISFSR 0x0
#define ERR_DIAG_BUF_SPARC_DSFSR 0x8
#define ERR_DIAG_BUF_SPARC_DSFAR 0x10
#define ERR_DIAG_BUF_SPARC_DESR 0x18
#define ERR_DIAG_BUF_SPARC_DFESR 0x20
#define ERR_DIAG_BUF_L2_CACHE_ESR 0x28
#define ERR_DIAG_BUF_L2_CACHE_ESR_INCR 0x8
#define ERR_DIAG_BUF_L2_CACHE_EAR 0x68
#define ERR_DIAG_BUF_L2_CACHE_EAR_INCR 0x8
#define ERR_DIAG_BUF_L2_CACHE_ND 0xa8
#define ERR_DIAG_BUF_L2_CACHE_ND_INCR 0x8
#define ERR_DIAG_BUF_DRAM_ESR 0xe8
#define ERR_DIAG_BUF_DRAM_ESR_INCR 0x8
#define ERR_DIAG_BUF_DRAM_EAR 0x108
#define ERR_DIAG_BUF_DRAM_EAR_INCR 0x8
#define ERR_DIAG_BUF_DRAM_CTR 0x128
#define ERR_DIAG_BUF_DRAM_CTR_INCR 0x8
#define ERR_DIAG_BUF_DRAM_LOC 0x148
#define ERR_DIAG_BUF_DRAM_LOC_INCR 0x8
#define ERR_DIAG_BUF_DRAM_FBD 0x168
#define ERR_DIAG_BUF_DRAM_FBD_INCR 0x8
#define ERR_DIAG_BUF_DRAM_RETRY 0x188
#define ERR_DIAG_BUF_DRAM_RETRY_INCR 0x8
#define ERR_DIAG_L2_BANK 0x1a8
#define ERR_DIAG_L2_LINE_STATE 0x1b0
#define ERR_DIAG_L2_PA 0x1b8
#define ERR_DIAG_BUF_DIAG_DATA 0x1c0
#define ERR_DIAG_BUF_RPRT_IN_USE 0xa90
#define ERR_DIAG_BUF_RPRT_SIZE 0xa94
#define CPU_SUN4V_RPRT_SIZE 0x40
#define CPU_SUN4V_RPRT_G_EHDL 0x0
#define CPU_SUN4V_RPRT_G_STICK 0x8
#define CPU_SUN4V_RPRT_EDESC 0x10
#define CPU_SUN4V_RPRT_ATTR 0x14
#define CPU_SUN4V_RPRT_ADDR 0x18
#define CPU_SUN4V_RPRT_SZ 0x20
#define CPU_SUN4V_RPRT_G_CPUID 0x24
#define CPU_SUN4V_RPRT_G_SECS 0x26
#define CPU_SUN4V_RPRT_ASI 0x28
#define CPU_SUN4V_RPRT_REG 0x2a
#define CPU_SUN4V_RPRT_WORD6 0x2c
#define CPU_SUN4V_RPRT_WORD7 0x30
#define CPU_SUN4V_RPRT_WORD8 0x38
#define ESUN4V_G_EHDL CPU_SUN4V_RPRT_G_EHDL
#define ESUN4V_G_STICK CPU_SUN4V_RPRT_G_STICK
#define ESUN4V_EDESC CPU_SUN4V_RPRT_EDESC
#define ESUN4V_ATTR CPU_SUN4V_RPRT_ATTR
#define ESUN4V_ADDR CPU_SUN4V_RPRT_ADDR
#define ESUN4V_SZ CPU_SUN4V_RPRT_SZ
#define ESUN4V_G_CPUID CPU_SUN4V_RPRT_G_CPUID
#define ESUN4V_G_SECS CPU_SUN4V_RPRT_G_SECS
#define ERR_SUN4V_RPRT_SIZE 0x48
#define ERR_SUN4V_CPU_ERPT 0x0
#define ERR_SUN4V_RPRT_IN_USE 0x40
#define ERR_SUN4V_PCIE_ERPT ERR_SUN4V_CPU_ERPT
#define ERR_SUN4V_RPRT_G_EHDL (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_EHDL)
#define ERR_SUN4V_RPRT_G_STICK (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_STICK)
#define ERR_SUN4V_RPRT_EDESC (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_EDESC)
#define ERR_SUN4V_RPRT_ATTR (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_ATTR)
#define ERR_SUN4V_RPRT_ADDR (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_ADDR)
#define ERR_SUN4V_RPRT_SZ (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_SZ)
#define ERR_SUN4V_RPRT_G_CPUID (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_CPUID)
#define ERR_SUN4V_RPRT_G_SECS (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_SECS)
#define ERR_SUN4V_RPRT_ASI (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_ASI)
#define ERR_SUN4V_RPRT_REG (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_REG)
#define ERR_SUN4V_PCIE_SYSINO (ERR_SUN4V_PCIE_ERPT + PCIERPT_SYSINO)
#define ERR_SUN4V_PCIE_EHDL (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_EHDL)
#define ERR_SUN4V_PCIE_STICK (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_STICK)
#define ERR_SUN4V_PCIE_DESC (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_DESC)
#define ERR_SUN4V_PCIE_SPECIFIC (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_SPECFIC)
#define ERR_SUN4V_PCIE_WORD4 (ERR_SUN4V_PCIE_ERPT + PCIERPT_WORD4)
#define ERR_SUN4V_PCIE_HDR1 (ERR_SUN4V_PCIE_ERPT + PCIERPT_HDR1)
#define ERR_SUN4V_PCIE_HDR2 (ERR_SUN4V_PCIE_ERPT + PCIERPT_HDR2)
#define ERR_DIAG_RPRT_SIZE 0xaf0
#define ERR_DIAG_RPRT_ERROR_TYPE 0x0
#define ERR_DIAG_RPRT_REPORT_TYPE 0x8
#define ERR_DIAG_RPRT_TOD 0x10
#define ERR_DIAG_RPRT_EHDL 0x18
#define ERR_DIAG_RPRT_ERR_STICK 0x20
#define ERR_DIAG_RPRT_CPUVER 0x28
#define ERR_DIAG_RPRT_SERIAL 0x30
#define ERR_DIAG_RPRT_TSTATE 0x38
#define ERR_DIAG_RPRT_HTSTATE 0x40
#define ERR_DIAG_RPRT_TPC 0x48
#define ERR_DIAG_RPRT_CPUID 0x50
#define ERR_DIAG_RPRT_TT 0x52
#define ERR_DIAG_RPRT_TL 0x54
#define ERR_DIAG_RPRT_ERR_DIAG 0x58
#define ERR_DIAG_RPRT_IN_USE (ERR_DIAG_RPRT_ERR_DIAG + ERR_DIAG_BUF_RPRT_IN_USE)
#define ERR_DIAG_ABORT_DATA ERR_DIAG_RPRT_ERR_DIAG
#define ERR_DIAG_DATA_OFFSET (ERR_DIAG_RPRT_ERR_DIAG + ERR_DIAG_BUF_DIAG_DATA)
#define ERR_DIAG_RPRT_REPORT_SIZE (ERR_DIAG_RPRT_ERR_DIAG + ERR_DIAG_BUF_RPRT_SIZE)
#define NIU_COOKIE_SIZE 0x10
#define NIU_LDG2LDN_TABLE 0x0
#define NIU_VEC2LDG_TABLE 0x8
#define ECC_SYNDROME_TABLE_ENTRY_SIZE 0x1
#define ECC_MASK_TABLE_ENTRY_SIZE 0x4
#define FPGA_UART_COOKIE_SIZE 0x20
#define FPGA_UART_COOKIE_STATUS 0x0
#define FPGA_UART_COOKIE_ENABLE 0x8
#define FPGA_UART_COOKIE_DISABLE 0x10
#define FPGA_UART_COOKIE_VALID 0x18
#define FPGA_UART_COOKIE_STATE 0x19
#define FPGA_UART_COOKIE_TARGET 0x1a
#define ENUM_HVctl_res_guest 0x0
#define ENUM_HVctl_res_vcpu 0x1
#define ENUM_HVctl_res_memory 0x2
#define ENUM_HVctl_res_mau 0x3
#define ENUM_HVctl_res_cwq 0x4
#define ENUM_HVctl_res_ldc 0x5
#define ENUM_HVctl_res_console 0x6
#define ENUM_HVctl_res_hv_ldc 0x7
#define ENUM_HVctl_res_pcie_bus 0x8
#define ENUM_HVctl_res_guestmd 0x9
#define ENUM_HVctl_res_network_device 0xa
#define ENUM_HVctl_info_guest_state 0x0
#define ENUM_HVctl_info_guest_soft_state 0x1
#define ENUM_HVctl_info_guest_tod 0x2
#define ENUM_HVctl_info_guest_utilisation 0x3
#define ENUM_HVctl_info_guest_max 0x4
#define CONFIG_MAUS (CONFIG_MCONFIG + MCONFIG_MAUS)
#define CONFIG_CWQS (CONFIG_MCONFIG + MCONFIG_CWQS)
#define CONFIG_RNG (CONFIG_MCONFIG + MCONFIG_RNG)
#define MGUEST_NIU_STATEP 0x0
#define GUEST_NIU_STATEP (GUEST_MGUEST + MGUEST_NIU_STATEP)
#define NIUMAPREG_SIZE 0x40
#define NIUMAPREG_SHIFT 0x6
#define NIUMAPREG_STATE 0x0
#define NIUMAPREG_VALID 0x4
#define NIUMAPREG_VCPUP 0x8
#define NIUSTATE_SIZE 0x1000
#define NIUSTATE_MAPREG 0x0
#define NIUSTATE_MAPREG_INCR 0x40
projects / OpenSPARC-T2-SAM / blob