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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / legion / src / procs / sunsparc / libniagara / include / niagara.h
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: niagara.h
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23/*
24 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
25 * Use is subject to license terms.
26 */
27
28#ifndef _NIAGARA_H_
29#define _NIAGARA_H_
30
31#pragma ident "@(#)niagara.h 1.35 07/03/07 SMI"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37#ifdef NIAGARA1
38#include <modarith_types.h>
39#include <modarith.h>
40#include "niagara_err_trap.h"
41
42 /*
43 * Niagara specific definitions
44 */
45
46 /*
47 * This table describes the trap behaviour for Niagara ..
48 * based on the existing state (User, Priv, Hyper mode),
49 * and to which state the trap is to be delivered.
50 * Moreover, what is the priority of the trap type.
51 */
52
53typedef enum {
54 SS_trap_NONE = -1,
55
56 SS_trap_legion_save_state = 0x0, /* reserved on real HW */
57 SS_trap_power_on_reset = 0x1,
58 SS_trap_watchdog_reset = 0x2,
59 SS_trap_externally_initiated_reset = 0x3,
60 SS_trap_software_initiated_reset = 0x4,
61 SS_trap_RED_state_exception = 0x5,
62 /* 0x6-0x7 Reserved */
63 SS_trap_instruction_access_exception = 0x8,
64 SS_trap_instruction_access_MMU_miss = 0x9,
65 SS_trap_instruction_access_error = 0xa,
66 /* 0xb-0xf Reserved */
67 SS_trap_illegal_instruction = 0x10,
68 SS_trap_privileged_opcode = 0x11,
69 SS_trap_unimplemented_LDD = 0x12,
70 SS_trap_unimplemented_STD = 0x13,
71 /* 0x14-0x1f Reserved */
72 SS_trap_fp_disabled = 0x20,
73 SS_trap_fp_exception_ieee_754 = 0x21,
74 SS_trap_fp_exception_other = 0x22,
75 SS_trap_tag_overflow = 0x23,
76 SS_trap_clean_window = 0x24,
77 /* 0x25-0x27 clean_window reserved */
78 SS_trap_division_by_zero = 0x28,
79 SS_trap_internal_processor_error = 0x29,
80 /* 0x2a-0x2f Reserved */
81 SS_trap_data_access_exception = 0x30,
82 SS_trap_data_access_MMU_miss = 0x31,
83 SS_trap_data_access_error = 0x32,
84 SS_trap_data_access_protection = 0x33,
85 SS_trap_mem_address_not_aligned = 0x34,
86 SS_trap_LDDF_mem_address_not_aligned = 0x35,
87 SS_trap_STDF_mem_address_not_aligned = 0x36,
88 SS_trap_privileged_action = 0x37,
89 SS_trap_LDQF_mem_address_not_aligned = 0x38,
90 SS_trap_STQF_mem_address_not_aligned = 0x39,
91 /* 0x3a-0x3d Reserved */
92 SS_trap_instruction_real_translation_miss = 0x3e,
93 SS_trap_data_real_translation_miss = 0x3f,
94 SS_trap_async_data_error = 0x40,
95 SS_trap_interrupt_level_1 = 0x41,
96 SS_trap_interrupt_level_2 = 0x42,
97 SS_trap_interrupt_level_3 = 0x43,
98 SS_trap_interrupt_level_4 = 0x44,
99 SS_trap_interrupt_level_5 = 0x45,
100 SS_trap_interrupt_level_6 = 0x46,
101 SS_trap_interrupt_level_7 = 0x47,
102 SS_trap_interrupt_level_8 = 0x48,
103 SS_trap_interrupt_level_9 = 0x49,
104 SS_trap_interrupt_level_a = 0x4a,
105 SS_trap_interrupt_level_b = 0x4b,
106 SS_trap_interrupt_level_c = 0x4c,
107 SS_trap_interrupt_level_d = 0x4d,
108 SS_trap_interrupt_level_e = 0x4e,
109 SS_trap_interrupt_level_f = 0x4f,
110 /* 0x50-0x5d Reserved */
111 SS_trap_hstick_match = 0x5e,
112 SS_trap_trap_level_zero = 0x5f,
113 SS_trap_interrupt_vector_trap = 0x60,
114 SS_trap_RA_watchpoint = 0x61,
115 SS_trap_VA_watchpoint = 0x62,
116 SS_trap_ECC_error = 0x63,
117 SS_trap_fast_instruction_access_MMU_miss = 0x64,
118 /* 0x65-0x67 reserved for fast_instruction_access_MMU_miss */
119 SS_trap_fast_data_access_MMU_miss = 0x68,
120 /* 0x69-0x6b reserved for fast_data_access_MMU_miss */
121 SS_trap_fast_data_access_protection = 0x6c,
122 /* 0x6d-0x6f reserved for fast_data_access_protection */
123 /* 0x70-0x73 Reserved */
124 N1_trap_modular_arithmetic = 0x74,
125 /* 0x75 Reserved */
126 SS_trap_instruction_breakpoint = 0x76,
127 /* 0x77 Reserved */
128 N1_trap_data_error = 0x78,
129 /* 0x79-0x7b Reserved */
130 SS_trap_cpu_mondo_trap = 0x7c,
131 SS_trap_dev_mondo_trap = 0x7d,
132 SS_trap_resumable_error = 0x7e,
133 SS_trap_nonresumable_error = 0x7f,
134
135 SS_trap_spill_0_normal = 0x80,
136 SS_trap_spill_1_normal = 0x84,
137 SS_trap_spill_2_normal = 0x88,
138 SS_trap_spill_3_normal = 0x8c,
139 SS_trap_spill_4_normal = 0x90,
140 SS_trap_spill_5_normal = 0x94,
141 SS_trap_spill_6_normal = 0x98,
142 SS_trap_spill_7_normal = 0x9c,
143
144 SS_trap_spill_0_other = 0xa0,
145 SS_trap_spill_1_other = 0xa4,
146 SS_trap_spill_2_other = 0xa8,
147 SS_trap_spill_3_other = 0xac,
148 SS_trap_spill_4_other = 0xb0,
149 SS_trap_spill_5_other = 0xb4,
150 SS_trap_spill_6_other = 0xb8,
151 SS_trap_spill_7_other = 0xbc,
152
153 SS_trap_fill_0_normal = 0xc0,
154 SS_trap_fill_1_normal = 0xc4,
155 SS_trap_fill_2_normal = 0xc8,
156 SS_trap_fill_3_normal = 0xcc,
157 SS_trap_fill_4_normal = 0xd0,
158 SS_trap_fill_5_normal = 0xd4,
159 SS_trap_fill_6_normal = 0xd8,
160 SS_trap_fill_7_normal = 0xdc,
161
162 SS_trap_fill_0_other = 0xe0,
163 SS_trap_fill_1_other = 0xe4,
164 SS_trap_fill_2_other = 0xe8,
165 SS_trap_fill_3_other = 0xec,
166 SS_trap_fill_4_other = 0xf0,
167 SS_trap_fill_5_other = 0xf4,
168 SS_trap_fill_6_other = 0xf8,
169 SS_trap_fill_7_other = 0xfc,
170
171 /* trap 0x100-0x17f, */
172 SS_trap_trap_instruction = 0x100,
173 /* htrap 0x180-0x1ff, */
174 SS_trap_htrap_instruction = 0x180,
175 SS_trap_illegal_value = 0x200
176} ss_trap_type_t;
177
178typedef struct TRAP_PRIORITY {
179 ss_trap_type_t trap_type;
180 char * trap_namep;
181 uint_t priority;
182 tflag_t from_user;
183 tflag_t from_priv;
184 tflag_t from_hyperpriv;
185} ss_trap_list_t;
186
187extern ss_trap_list_t ss_trap_list[];
188
189 /*
190 * ASI's as implemented by Niagara
191 */
192
193typedef enum {
194 /* MANDATORY SPARC V9 ASIs */
195
196 SS_ASI_NUCLEUS = 0x4 , /* RW Implicit Address Space, nucleus context, TL>0 */
197 SS_ASI_NUCLEUS_LITTLE = 0xc , /* RW Implicit Address Space, nucleus context, TL>0 (LE) */
198 SS_ASI_AS_IF_USER_PRIMARY = 0x10, /* RW Primary Address Space, user privilege */
199 SS_ASI_AS_IF_USER_SECONDARY = 0x11, /* RW Secondary Address Space, user privilege */
200 SS_ASI_AS_IF_USER_PRIMARY_LITTLE = 0x18, /* RW Primary Address Space, user privilege (LE) */
201 SS_ASI_AS_IF_USER_SECONDARY_LITTLE = 0x19, /* RW Secondary Address Space, user privilege (LE) */
202 SS_ASI_PRIMARY = 0x80, /* RW Implicit Primary Address space */
203 SS_ASI_SECONDARY = 0x81, /* RW Implicit Secondary Address space */
204 SS_ASI_PRIMARY_NO_FAULT = 0x82, /* R Primary Address space, no fault */
205 SS_ASI_SECONDARY_NO_FAULT = 0x83, /* R Secondary Address space, no fault */
206 SS_ASI_PRIMARY_LITTLE = 0x88, /* RW Implicit Primary Address space (LE) */
207 SS_ASI_SECONDARY_LITTLE = 0x89, /* RW Implicit Secondary Address space (LE) */
208 SS_ASI_PRIMARY_NO_FAULT_LITTLE = 0x8A, /* R Primary Address space, no fault (LE) */
209 SS_ASI_SECONDARY_NO_FAULT_LITTLE = 0x8B, /* R Secondary Address space, no fault (LE) */
210
211 /* SunSPARC EXTENDED (non-V9) ASIs */
212
213 OLD_SS_ASI_PHYS_USE_EC = 0x14, /* RW physical address, non-allocating in L1 cache */
214 OLD_SS_ASI_PHYS_BYPASS_EC_WITH_EBIT = 0x15, /* RW Same as ASI_PHYS_USE_EC for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect */
215 SS_ASI_REAL_MEM = 0x14, /* RW physical address, non-allocating in L1 cache */
216 SS_ASI_REAL_IO = 0x15, /* RW Same as ASI_PHYS_USE_EC for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect */
217 SS_ASI_BLOCK_AS_IF_USER_PRIMARY = 0x16, /* RW 64B block load/store, primary address space, user privilege */
218 SS_ASI_BLOCK_AS_IF_USER_SECONDARY = 0x17, /* RW 64B block load/store, secondary address space, user privilege */
219 OLD_SS_ASI_PHYS_USE_EC_LITTLE = 0x1C, /* RW physical address, non-allocating in L1 cache */
220 OLD_SS_ASI_PHYS_BYPASS_EC_WITH_EBIT_LITTLE = 0x1D, /* RW Same as ASI_PHYS_USE_EC_LITTLE for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect (LE) */
221 SS_ASI_REAL_MEM_LITTLE = 0x1C, /* RW physical address, non-allocating in L1 cache */
222 SS_ASI_REAL_IO_LITTLE = 0x1D, /* RW Same as ASI_PHYS_USE_EC_LITTLE for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect (LE) */
223 SS_ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = 0x1E, /* RW 64B block load/store, primary address space, user privilege (LE) */
224 SS_ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = 0x1F, /* RW 64B block load/store, secondary address space, user privilege (LE) */
225 SS_ASI_SCRATCHPAD = 0x20, /* Scratchpad Registers */
226 SS_ASI_MMU = 0x21, /* MMU Registers */
227 SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_P = 0x22, /* Block initializing store/128b atomic LDDA, primary address, user privilege */
228 SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_S = 0x23, /* Block initializing store/128b atomic LDDA, secondary address, user privilege */
229 SS_ASI_QUAD_LDD = 0x24, /* 128b atomic LDDA */
230 SS_ASI_QUEUE = 0x25, /* Mondo Queue Pointers */
231 SS_ASI_QUAD_LDD_REAL = 0x26, /* 128b atomic LDDA, real address */
232 SS_ASI_NUCLEUS_BLK_INIT_ST_QUAD_LDD = 0x27, /* Block initializing store/128b atomic LDDA */
233 SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_P_LITTLE = 0x2A, /* Block initializing store/128b atomic LDDA, primary address, user priv (LE) */
234 SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_S_LITTLE = 0x2B, /* Block initializing store, secondary address, user privilege (LE) */
235 SS_ASI_QUAD_LDD_LITTLE = 0x2C, /* 128b atomic LDDA (LE) */
236 SS_ASI_QUAD_LDD_REAL_LITTLE = 0x2E, /* 128b atomic LDDA, real address (LE) */
237 SS_ASI_NUCLEUS_BLK_INIT_ST_QUAD_LDD_LITTLE = 0x2F, /* Block initializing store/128b atomic LDDA (LE) */
238 SS_ASI_DIRECT_MAP_ECACHE = 0x30, /* N1 PRM rev 1.4 - any type of access causes data_access_exception */
239 SS_ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x31, /* DMMU Context Zero TSB Base PS 0 */
240 SS_ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x32, /* DMMU Context Zero TSB Base PS 1 */
241 SS_ASI_DMMU_CTXT_ZERO_CONFIG = 0x33, /* DMMU Context Zero Config Register */
242
243 SS_ASI_QUAD_LDD_PHYS = 0x34, /* N1 PRM rev 1.4 - any type of access causes data_access_exception */
244 SS_ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x35, /* IMMU Context Zero TSB Base PS0 */
245 SS_ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x36, /* IMMU Context Zero TSB Base PS1 */
246 SS_ASI_IMMU_CTXT_ZERO_CONFIG = 0x37, /* IMMU Context Zero Config Register */
247 SS_ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x39, /* DMMU Context Nonzero TSB Base PS0 */
248 SS_ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3A, /* DMMU Context Nonzero TSB Base PS1 */
249 SS_ASI_DMMU_CTXT_NONZERO_CONFIG = 0x3B, /* DMMU Context Non-Zero Config Register */
250 SS_ASI_QUAD_LDD_PHYS_LITTLE = 0x3C, /* 128b atomic LDDA, physical address (LE) */
251 SS_ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x3D, /* IMMU Context Nonzero TSB Base PS0 */
252 SS_ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3E, /* IMMU Context Nonzero TSB Base PS1 */
253 SS_ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F, /* IMMU Context Non-Zero Config Register */
254 SS_ASI_STREAM_MA = 0x40, /* Asynchronous Streaming Control Register */
255 SS_ASI_LSU_DIAG_REG = 0x42, /* Diagnostic / Control register */
256 SS_ASI_ERROR_INJECT_REG = 0x43, /* Error Injection Register */
257 SS_ASI_STM_CTL_REG = 0x44, /* Self-timed Margin Control Register */
258 SS_ASI_LSU_CONTROL_REG = 0x45, /* Load/Store Unit Control Register */
259 SS_ASI_DCACHE_DATA = 0x46, /* Dcache data array diagnostics access */
260 SS_ASI_DCACHE_TAG = 0x47, /* Dcache tag and valid bit diagnostics access */
261 SS_ASI_INTR_DISPATCH_STATUS = 0x48, /* - any type of access causes data_access_exception */
262 SS_ASI_INTR_RECEIVE = 0x49, /* - any type of access causes data_access_exception */
263 SS_ASI_UPA_CONFIG_REGISTER = 0x4A, /* - any type of access causes data_access_exception */
264 SS_ASI_SPARC_ERROR_EN_REG = 0x4B, /* Sparc error enable reg(synchronous ecc/parity errors) */
265 SS_ASI_SPARC_ERROR_STATUS_REG = 0x4C, /* RW 0 Y Sparc error status reg */
266 SS_ASI_SPARC_ERROR_ADDRESS_REG = 0x4D, /* RW 0 Y Sparc error address reg */
267 SS_ASI_ECACHE_TAG_DATA = 0x4E, /* - any type of access causes data_access_exception */
268 SS_ASI_HYP_SCRATCHPAD = 0x4F, /* RW 0-38 Y Hypervisor Scratchpad */
269 SS_ASI_IMMU = 0x50, /* IMMU control register */
270 SS_ASI_IMMU_TSB_PS0_PTR_REG = 0x51, /* IMMU TSB PS0 pointer register */
271 SS_ASI_IMMU_TSB_PS1_PTR_REG = 0x52, /* IMMU TSB PS1 pointer register */
272 SS_ASI_ITLB_DATA_IN_REG = 0x54, /* IMMU data in register */
273 SS_ASI_ITLB_DATA_ACCESS_REG = 0x55, /* IMMU TLB Data Access Register */
274 SS_ASI_ITLB_TAG_READ_REG = 0x56, /* IMMU TLB Tag Read Register */
275 SS_ASI_IMMU_DEMAP = 0x57, /* IMMU TLB Demap */
276 SS_ASI_DMMU = 0x58, /* DMMU control register */
277 SS_ASI_DMMU_TSB_PS0_PTR_REG = 0x59, /* DMMU TSB PS0 pointer register */
278 SS_ASI_DMMU_TSB_PS1_PTR_REG = 0x5A, /* DMMU TSB PS1 pointer register */
279 SS_ASI_DMMU_TSB_DIRECT_PTR_REG = 0x5B, /* DMMU TSB Direct pointer register */
280 SS_ASI_DTLB_DATA_IN_REG = 0x5C, /* DMMU data in register */
281 SS_ASI_DTLB_DATA_ACCESS_REG = 0x5D, /* DMMU TLB Data Access Register */
282 SS_ASI_DTLB_TAG_READ_REG = 0x5E, /* DMMU TLB Tag Read Register */
283 SS_ASI_DMMU_DEMAP = 0x5F, /* DMMU TLB Demap */
284 SS_ASI_TLB_INVALIDATE_ALL = 0x60, /* MMU TLB Invalidate Register */
285 SS_ASI_ICACHE_INSTR = 0x66, /* Icache data array diagnostics access */
286 SS_ASI_ICACHE_TAG = 0x67, /* Icache tag and valid bit diagnostics access */
287 SS_ASI_SWVR_INTR_RECEIVE = 0x72, /* Interrupt Receive Register */
288 SS_ASI_SWVR_UDB_INTR_W = 0x73, /* Interrupt Vector Dispatch Register */
289 SS_ASI_SWVR_UDB_INTR_R = 0x74, /* Incoming Vector Register */
290 SS_ASI_ECACHE_W = 0x76, /* - any type of access causes data_access_exception */
291 SS_ASI_UDB_INTR_W = 0x77, /* - any type of access causes data_access_exception */
292 SS_ASI_ECACHE_R = 0x7E, /* any type of access causes data_access_exception */
293 SS_ASI_UDB_INTR_R = 0x7F, /* any type of access causes data_access_exception */
294
295 SS_ASI_PST8_P = 0xC0, /* 8 bit partial pri */
296 SS_ASI_PST8_S = 0xC1, /* 8 bit partial sec */
297 SS_ASI_PST16_P = 0xC2, /* 16 bit partial pri */
298 SS_ASI_PST16_S = 0xC3, /* 16 bit partial sec */
299 SS_ASI_PST32_P = 0xC4, /* 32 bit partial pri */
300 SS_ASI_PST32_S = 0xC5, /* 32 bit partial sec */
301 SS_ASI_PST8_PL = 0xC8, /* 8 bit partial pri LE */
302 SS_ASI_PST8_SL = 0xC9, /* 8 bit partial sec LE */
303 SS_ASI_PST16_PL = 0xCA, /* 16 bit partial pri LE */
304 SS_ASI_PST16_SL = 0xCB, /* 16 bit partial sec LE */
305 SS_ASI_PST32_PL = 0xCC, /* 32 bit partial pri LE */
306 SS_ASI_PST32_SL = 0xCD, /* 32 bit partial sec LE */
307
308 SS_ASI_FL8_P = 0xD0, /* float 8 bit partial pri */
309 SS_ASI_FL8_S = 0xD1, /* float 8 bit partial sec */
310 SS_ASI_FL16_P = 0xD2, /* float 16 bit partial pri */
311 SS_ASI_FL16_S = 0xD3, /* float 16 bit partial sec */
312 SS_ASI_FL8_PL = 0xD8, /* float 8 bit partial pri LE*/
313 SS_ASI_FL8_SL = 0xD9, /* float 8 bit partial sec LE*/
314 SS_ASI_FL16_PL = 0xDA, /* float 16 bit partial pri LE */
315 SS_ASI_FL16_SL = 0xDB, /* float 16 bit partial sec LE */
316
317 SS_ASI_BLK_COMMIT_P = 0xE0, /* any type of access causes data_access_exception */
318 SS_ASI_BLK_COMMIT_S = 0xE1, /* any type of access causes data_access_exception */
319 SS_ASI_BLK_INIT_ST_QUAD_LDD_P = 0xE2, /* Block initializing store/128b atomic LDDA, primary address */
320 SS_ASI_BLK_INIT_ST_QUAD_LDD_S = 0xE3, /* Block initializing store/128b atomic LDDA, secondary address */
321 SS_ASI_BLK_INIT_ST_QUAD_LDD_P_LITTLE = 0xEA, /* Block initializing store/128b atomic LDDA, primary address (LE) */
322 SS_ASI_BLK_INIT_ST_QUAD_LDD_S_LITTLE = 0xEB, /* Block initializing store/128b atomic LDDA, secondary address (LE) */
323 SS_ASI_BLK_P = 0xF0, /* 64B block load/store, primary address */
324 SS_ASI_BLK_S = 0xF1, /* 64B block load/store, secondary address */
325 SS_ASI_BLK_PL = 0xF8, /* 64B block load/store, primary address (LE) */
326 SS_ASI_BLK_SL = 0xF9 /* 64B block load/store, secondary address (LE) */
327
328} ss_asi_t;
329
330
331#define SS_ICACHE_SIZE 0x4000 /* 16K instn cache with 32B lines */
332#define SS_DCACHE_SIZE 0x2000 /* 8K data cache with 16B lines */
333
334 /* L1 I-Cache and D-Cache Diagnostic Access Sections 18.3 and 18.4 of PRM 1.2 */
335#define SS_ICACHE_DATA_LINEWORD_BITS 0x1ff8 /* line[12:6]word[5:3]rsv2[2:0] */
336#define SS_ICACHE_DATA_WAY_BITS 0x30000 /* way[17:16] */
337#define SS_ICACHE_TAG_LINE_BITS 0x1fc0 /* line[12:6]rsvd2[5:0] */
338#define SS_ICACHE_TAG_WAY_BITS 0x30000 /* way[17:16] */
339#define SS_DCACHE_DATA_BITS 0x1ff8 /* way[12:11]line[10:4]word[3]rsv2[2:0] */
340#define SS_DCACHE_DATA_TAG_BITS 0x7ffffff800 /* tag[39:11] */
341#define SS_DCACHE_TAG_WAYLINE_BITS 0x1ff0 /* way[12:11]line[10:4]rsvd1[3:0] */
342
343/*
344 * core = num / 4;
345 * strand = num % 4;
346 * idx = str_to_idx[num]
347 */
348#define STRANDSPERCORE 4 /* architectural, needed to match registers */
349#define CORESPERCHIP 8
350#define STRANDS_PER_CHIP (STRANDSPERCORE * CORESPERCHIP)
351#define VALID_CORE_MASK 0xffffffffull
352#define NO_STRAND ((uint_t)-1)
353#define STRANDID2IDX(npp, s) \
354 (((uint_t)(s) < STRANDS_PER_CHIP) ? (npp)->str_to_idx[s] : NO_STRAND)
355#define VALIDIDX(npp, tidx) \
356 ((uint_t)(tidx) != NO_STRAND)
357
358#define DEFAULT_ITLB_ENTRIES 64
359#define DEFAULT_DTLB_ENTRIES 64
360
361 /*
362 * L2 Cache controller definition
363 */
364
365#define L2_BANKS 4
366
367 /* L2 Cache Diagnostic Access section 18.6 of PRM 1.2 */
368typedef struct SS_L2_CACHE {
369 uint64_t * diag_datap;
370 uint64_t * diag_tagp;
371#define L2_TAG MASK64(39,18)
372#define L2_TAG_ECC MASK64(5,0)
373 uint64_t * diag_vuadp;
374#define L2_ODDEVEN_SHIFT 22
375#define L2_WAY MASK64(21,18)
376#define L2_LINE MASK64(17,8)
377#define L2_BANK MASK64(7,6)
378#define L2_WORD MASK64(5,3)
379#define L2_VDSEL MASK64(22,22)
380#define L2_DM_MASK MASK64(21,6)
381 /*
382 * index into data with way/line/bank/word/oddeven bits (0xc-0xf of way unused)
383 * access 64bits: 32bit data, 7bit ECC, plus rsvd bits
384 * 8MB size: 3MB data, 3MB associated ecc+rsvd, 2MB wasted due to unused way bits
385 */
386#define L2_DATA_SIZE ((L2_WAY|L2_LINE|L2_BANK|L2_WORD|(1<<L2_ODDEVEN_SHIFT))+8)
387 /*
388 * index into tags with way/line/bank bits (0xc-0xf of way unused)
389 * access 64bits: 22bit tag, 6bit ECC plus rsvd bits (512K size)
390 */
391#define L2_TAG_SIZE (((L2_WAY|L2_LINE|L2_BANK)>>3)+8)
392 /*
393 * index into vuad with way/line/bank bits (0xc-0xf of way unused)
394 * access 64bits: valid/dirty or alloc/used bits and associated parity (64K size)
395 */
396#define L2_VUAD_SIZE (((L2_LINE|L2_BANK|(L2_VDSEL>>4))>>3)+8)
397
398 uint64_t control[L2_BANKS];
399#define L2_DBGEN MASK64(20,20)
400#define L2_ERRORSTEER MASK64(19,15)
401#define L2_SCRUBINTERVAL MASK64(14,3)
402#define L2_SCRUBENABLE MASK64(2,2)
403#define L2_DMMODE MASK64(1,1)
404#define L2_DIS MASK64(0,0)
405
406 uint64_t error_enable[L2_BANKS];
407#define L2_DBG_TRIG_EN MASK64(2,2)
408#define L2_NCEEN MASK64(1,1)
409#define L2_CEEN MASK64(0,0)
410
411 uint64_t error_status[L2_BANKS];
412 uint64_t error_address[L2_BANKS];
413 uint64_t error_inject[L2_BANKS];
414 uint64_t bist_ctl[L2_BANKS];
415} ss_l2_cache_t;
416
417 /* L2 Cache Error Registers section 12.6 of PRM 1.2 */
418
419#define L2_MEU_bit BIT(63)
420#define L2_MEC_bit BIT(62)
421#define L2_RW_bit BIT(61)
422#define L2_MODA_bit BIT(59)
423#define L2_LDAC_bit BIT(53)
424#define L2_LDAU_bit BIT(52)
425#define L2_LDWC_bit BIT(51)
426#define L2_LDWU_bit BIT(50)
427#define L2_LDRC_bit BIT(49)
428#define L2_LDRU_bit BIT(48)
429#define L2_LDSC_bit BIT(47)
430#define L2_LDSU_bit BIT(46)
431#define L2_LTC_bit BIT(45)
432#define L2_LRU_bit BIT(44)
433#define L2_LVU_bit BIT(43)
434#define L2_DAC_bit BIT(42)
435#define L2_DAU_bit BIT(41)
436#define L2_DRC_bit BIT(40)
437#define L2_DRU_bit BIT(39)
438#define L2_DSC_bit BIT(38)
439#define L2_DSU_bit BIT(37)
440#define L2_VEC_bit BIT(36)
441#define L2_VEU_bit BIT(35)
442#define L2_SYND_MASK MASK64(31,0)
443
444#define L2_TID(val) (((uint64_t)val & 0x1f) << 54)
445#define L2_FAKE_SYND_SINGLE 0x43 /* single bit error on bit 0 */
446#define L2_FAKE_SYND_DOUBLE 0x33 /* uncorrectible double bit error */
447#define L2_FAKE_SYND_POISON 0x03 /* poisoned ecc */
448
449#define L2_PA_LINE(val) (val & MASK64(39,6))
450#define L2_PA_QUAD(val) (val & MASK64(39,4))
451#define L2_INDEX(val) (val & MASK64(21,6))
452#define L2_DIR_IDX(val) (val & MASK64(13,4))
453
454
455 /*
456 * SSI
457 */
458
459typedef struct NIAGAR_SSI {
460 uint64_t timeout;
461 uint64_t log;
462} ss_ssi_t;
463
464 /*
465 * JBI
466 */
467
468#define JBI_PORT_LOCN(n) (((uint64_t)n & 0x7f) << 51)
469#define JBI_PORT_PRES(n) (((uint64_t)n & 0x7f) << 44)
470#define JBI_MID(n) (((uint64_t)n & 0x3f) << 32)
471#define JBI_IQ_HIGH(n) ((n & 0x7) << 28)
472typedef struct SS_JBI {
473 uint64_t config1;
474 uint64_t config2;
475 uint64_t int_mrgn;
476 uint64_t debug;
477 uint64_t debug_arb;
478 uint64_t perf_ctl;
479 uint64_t perf_cnt;
480 uint64_t err_inject;
481 uint64_t err_config;
482 uint64_t error_log;
483 uint64_t error_ovf;
484 uint64_t log_enb;
485 uint64_t sig_enb;
486 uint64_t log_addr;
487 uint64_t log_ctrl;
488 uint64_t log_data0;
489 uint64_t log_data1;
490 uint64_t log_par;
491 uint64_t log_nack;
492 uint64_t log_arb;
493 uint64_t l2_timeout;
494 uint64_t arb_timeout;
495 uint64_t trans_timeout;
496 uint64_t intr_timeout;
497 uint64_t memsize;
498} ss_jbi_t;
499
500 /*
501 * IOB
502 */
503
504#define IOB_JBUS_TARGETS 32
505#define IOB_JBUS_BUSY 0x20
506#define IOB_JBUS_ACK 0
507#define IOB_JBUS_NACK -1
508typedef struct SS_JBUS {
509 uint64_t j_int_data0[IOB_JBUS_TARGETS];
510 uint64_t j_int_data1[IOB_JBUS_TARGETS];
511 uint64_t j_int_busy[IOB_JBUS_TARGETS];
512 pthread_mutex_t lock;
513} ss_jbus_t;
514
515typedef struct SS_IOB {
516 /* IOB Interrupt Registers section 7.3 of PRM 1.2 */
517#define IOB_DEV_ERR 1
518#define IOB_DEV_SSI 2
519#define IOB_DEV_MAX 4
520#define IOB_INT_MAN_CPUID(n) ((n&MASK64(12,8))>>8)
521#define IOB_INT_CTL_MASK MASK64(2,2)
522#define IOB_INT_CTL_CLEAR MASK64(1,1)
523#define IOB_INT_CTL_PEND MASK64(0,0)
524 uint64_t int_man[IOB_DEV_MAX];
525 uint8_t int_ctl[IOB_DEV_MAX]; /* max 3 bits ! */
526
527 pthread_mutex_t iob_lock; /* hold this lock for any iob register access */
528
529 pthread_mutex_t int_vec_lock; /* FIXME: to go away ! */
530
531 uint64_t int_vec_dis; /* poke your neighbour - interrupt vector dispatch ! */
532 uint64_t j_int_vec;
533#define IOB_INT_VEC_INTR(n) (((n>>16)&3) == 0)
534#define IOB_INT_VEC_RESET(n) (((n>>16)&3) == 1)
535#define IOB_INT_VEC_IDLE(n) (((n>>16)&3) == 2)
536#define IOB_INT_VEC_RESUME(n) (((n>>16)&3) == 3)
537#define IOB_INT_VEC_THREAD(n) ((n>>8)&0x1f)
538#define IOB_INT_VEC_VECTOR(n) (n&0x3f)
539 uint64_t rset_stat;
540 /* CPU throttle control section 16.1 of PRM 1.2 */
541 uint64_t tm_stat_ctl;
542 /* EFUSE Registers section 18.8 of PRM 1.2 */
543 uint64_t proc_ser_num;
544 uint64_t iob_fuse;
545 /* Internal Margin Register section 19.1.3 of PRM 1.2 */
546 uint64_t int_mrgn_reg;
547 /* IOB Visibility Port Support section 19.2 of PRM 1.2 */
548 uint64_t l2_vis_control;
549 uint64_t l2_vis_mask_a;
550 uint64_t l2_vis_mask_b;
551 uint64_t l2_vis_compare_a;
552 uint64_t l2_vis_compare_b;
553 uint64_t l2_trig_delay;
554 uint64_t iob_vis_select;
555 uint64_t db_enet_control;
556 uint64_t db_enet_idleval;
557 uint64_t db_jbus_control;
558 uint64_t db_jbus_mask0;
559 uint64_t db_jbus_mask1;
560 uint64_t db_jbus_mask2;
561 uint64_t db_jbus_mask3;
562 uint64_t db_jbus_compare0;
563 uint64_t db_jbus_compare1;
564 uint64_t db_jbus_compare2;
565 uint64_t db_jbus_compare3;
566 uint64_t db_jbus_count;
567} ss_iob_t;
568
569 /*
570 * Clock Unit definition
571 */
572
573 /* Clock Unit section 11.1 of PRM 1.2 */
574typedef struct SS_CLOCK {
575 uint64_t divider;
576 uint64_t control;
577 uint64_t dll_control;
578 uint64_t dll_bypass;
579 uint64_t jbus_sync;
580 uint64_t dram_sync;
581 uint64_t version;
582} ss_clock_t;
583
584 /*
585 * Memory controller defn
586 */
587typedef struct SS_DRAM_BANK {
588 uint8_t cas_addr_width; /* DRAM controller section 15.5 of RPM 1.1 */
589 uint8_t ras_addr_width;
590 uint8_t cas_lat;
591 uint16_t scrub_freq;
592 uint16_t refresh_freq;
593 uint16_t refresh_counter;
594 uint8_t scrub_enable;
595 uint8_t trrd;
596 uint8_t trc;
597 uint8_t dram_trcd;
598 uint8_t twtr;
599 uint8_t trtw;
600 uint8_t trtp;
601 uint8_t tras;
602 uint8_t trp;
603 uint8_t twr;
604 uint8_t trfc;
605 uint8_t tmrd;
606 uint8_t tiwtr;
607 uint8_t precharge_wait;
608 uint8_t dimm_stack;
609 uint16_t ext_wr_mode2;
610 uint16_t ext_wr_mode1;
611 uint16_t ext_wr_mode3;
612 uint8_t wair_control;
613 uint8_t rank1_present;
614 uint8_t channel_disabled;
615 uint8_t sel_lo_addr_bits;
616 uint8_t dimm_init;
617 uint8_t sw_dv_count;
618 uint8_t hw_dmux_clk_inv;
619 uint8_t pad_en_clk_inv;
620 uint8_t mode_write_status;
621 uint8_t init_status;
622 uint8_t dimm_present;
623 uint8_t failover_status;
624 uint64_t failover_mask;
625
626 uint8_t perf_ctl; /* Performance counter section 10.3 of PRM 1.1 */
627 uint64_t perf_count;
628
629 uint64_t error_status; /* Error handling section 12.9 of PRM 1.1 */
630 uint64_t error_address;
631 uint64_t error_inject;
632 uint32_t error_counter;
633 uint64_t error_location;
634
635 uint32_t open_bank_max; /* Power management section 16.2 of PRM 1.1 */
636 uint16_t prog_time_cntr;
637
638 uint8_t dbg_trg_en; /* Hardware debug section 19.1 of PRM 1.1 */
639} ss_dram_bank_t;
640
641/* DRAM Error Registers in section 12.9 of PRM 1.2 */
642#define DRAM_MEU_bit BIT(63)
643#define DRAM_MEC_bit BIT(62)
644#define DRAM_DAC_bit BIT(61)
645#define DRAM_DAU_bit BIT(60)
646#define DRAM_DSC_bit BIT(59)
647#define DRAM_DSU_bit BIT(58)
648#define DRAM_DBU_bit BIT(57)
649#define DRAM_SYND_MASK MASK64(15,0)
650
651#define DRAM_FAKE_SYND_SINGLE 0x00010101 /* nibble 31, bit 1 in error */
652#define DRAM_FAKE_SYND_DOUBLE 0x00000101 /* uncorrectible multi-nibble error */
653#define DRAM_FAKE_SYND_POISON 0x00008221 /* poisoned ecc */
654
655/****************************************************************
656 *
657 * Niagara address mapped registers
658 *
659 * Ref point: NAMR
660 *
661 * As well as ASI based registers, a number of Niagara state
662 * registers appear in the normal physical address space memory
663 * map.
664 * The following functions are provided as "virtual devices" within
665 * the physical address space, but in fact are components of the
666 * Niagara chip itself.
667 *
668 * FIXME: There is an annoying architectural problem here in that
669 * if there is ever an MP version of Niagara, then we have a problem
670 * determining which Niagara each of these devices belongs to.
671 * For now though we know there is only one per domain.
672 *
673 ****************************************************************/
674typedef enum {
675 NI_SSI_TIMEOUT = 0x10088,
676 NI_SSI_LOG = 0x00018
677} ss_ssi_reg_t;
678
679typedef enum {
680 NI_JBI_CONFIG1 = 0x00000,
681 NI_JBI_CONFIG2 = 0x00008,
682 NI_JBI_INT_MRGN = 0x00010,
683 NI_JBI_DEBUG = 0x04000,
684 NI_JBI_DEBUG_ARB = 0x04100,
685 NI_JBI_ERR_INJECT = 0x04800,
686 NI_JBI_PERF_CTL = 0x20000,
687 NI_JBI_PERF_CNT = 0x20008,
688 NI_JBI_ERR_CONFIG = 0x10000,
689 NI_JBI_ERROR_LOG = 0x10020,
690 NI_JBI_ERROR_OVF = 0x10028,
691 NI_JBI_LOG_ENB = 0x10030,
692 NI_JBI_SIG_ENB = 0x10038,
693 NI_JBI_LOG_ADDR = 0x10040,
694 NI_JBI_LOG_CTRL = 0x10048,
695 NI_JBI_LOG_DATA0 = 0x10050,
696 NI_JBI_LOG_DATA1 = 0x10058,
697 NI_JBI_LOG_PAR = 0x10060,
698 NI_JBI_LOG_NACK = 0x10070,
699 NI_JBI_LOG_ARB = 0x10078,
700 NI_JBI_L2_TIMEOUT = 0x10080,
701 NI_JBI_ARB_TIMEOUT = 0x10088,
702 NI_JBI_TRANS_TIMEOUT = 0x10090,
703 NI_JBI_INTR_TIMEOUT = 0x10098,
704 NI_JBI_MEMSIZE = 0x100a0
705} ss_jbi_reg_t;
706
707typedef enum {
708 NI_J_INT_DATA0 = 0x0400,
709 NI_J_INT_DATA1 = 0x0500,
710 NI_J_INT_ADATA0 = 0x0600,
711 NI_J_INT_ADATA1 = 0x0700,
712 NI_J_INT_BUSY = 0x0900,
713 NI_J_INT_ABUSY = 0x0b00
714} ss_jbus_reg_t;
715
716typedef enum {
717 NI_INT_MAN0 = 0x0000,
718 NI_INT_MAN1 = 0x0008,
719 NI_INT_MAN2 = 0x0010,
720 NI_INT_MAN3 = 0x0018,
721 NI_INT_CTL0 = 0x0400,
722 NI_INT_CTL1 = 0x0408,
723 NI_INT_CTL2 = 0x0410,
724 NI_INT_CTL3 = 0x0418,
725 NI_INT_VEC_DIS = 0x0800,
726 NI_RSET_STAT = 0x0810,
727 NI_TM_STAT_CTL = 0x0828,
728 NI_PROC_SER_NUM = 0x0820,
729 NI_CORE_AVAIL = 0x0830,
730 NI_IOB_FUSE = 0x0840,
731 NI_INT_MRGN_REG = 0x0850,
732 NI_J_INT_VEC = 0x0a00,
733 NI_L2_VIS_CONTROL = 0x1800,
734 NI_L2_VIS_MASK_A = 0x1820,
735 NI_L2_VIS_MASK_B = 0x1828,
736 NI_L2_VIS_COMPARE_A = 0x1830,
737 NI_L2_VIS_COMPARE_B = 0x1838,
738 NI_L2_TRIG_DELAY = 0x1840,
739 NI_IOB_VIS_SELECT = 0x1000,
740 NI_DB_ENET_CONTROL = 0x2000,
741 NI_DB_ENET_IDLEVAL = 0x2008,
742 NI_DB_JBUS_CONTROL = 0x2100,
743 NI_DB_JBUS_MASK0 = 0x2140,
744 NI_DB_JBUS_MASK1 = 0x2160,
745 NI_DB_JBUS_MASK2 = 0x2180,
746 NI_DB_JBUS_MASK3 = 0x21a0,
747 NI_DB_JBUS_COMPARE0 = 0x2148,
748 NI_DB_JBUS_COMPARE1 = 0x2168,
749 NI_DB_JBUS_COMPARE2 = 0x2188,
750 NI_DB_JBUS_COMPARE3 = 0x21a8,
751 NI_DB_JBUS_COUNT = 0x2150
752} ss_iob_reg_t;
753
754typedef enum {
755 SS_CLOCK_DIVIDER = 0x00,
756 SS_CLOCK_CONTROL = 0x08,
757 SS_DBG_INIT = 0x10,
758 SS_CLOCK_DLL_CONTROL = 0x18,
759 SS_CLOCK_JBUS_SYNC = 0x28,
760 SS_CLOCK_DLL_BYPASS = 0x38,
761 SS_CLOCK_DRAM_SYNC = 0x30,
762 SS_CLOCK_VERSION = 0x40
763} ss_clock_reg_t;
764
765typedef enum {
766 SS_L2_DIAG_DATA = 0x0,
767 SS_L2_DIAG_TAG = 0x4,
768 SS_L2_DIAG_VUAD = 0x6,
769 SS_L2_TAG_BIST = 0x8,
770 SS_L2_CONTROL = 0x9,
771 SS_L2_ERROR_ENABLE = 0xa,
772 SS_L2_ERROR_STATUS = 0xb,
773 SS_L2_ERROR_ADDRESS = 0xc,
774 SS_L2_ERROR_INJECT = 0xd
775} ss_l2_ctl_reg_t;
776
777typedef enum {
778 SS_DRAM_CAS_ADDR_WIDTH = 0x000, /* DRAM controller section 15.5 of RPM 1.1 */
779 SS_DRAM_RAS_ADDR_WIDTH = 0x008,
780 SS_DRAM_CAS_LAT = 0x010,
781 SS_DRAM_SCRUB_FREQ = 0x018,
782 SS_DRAM_REFRESH_FREQ = 0x020,
783 SS_DRAM_REFRESH_COUNTER = 0x038,
784 SS_DRAM_SCRUB_ENABLE = 0x040,
785 SS_DRAM_TRRD = 0x080,
786 SS_DRAM_TRC = 0x088,
787 SS_DRAM_DRAM_TRCD = 0x090,
788 SS_DRAM_TWTR = 0x098,
789 SS_DRAM_TRTW = 0x0a0,
790 SS_DRAM_TRTP = 0x0a8,
791 SS_DRAM_TRAS = 0x0b0,
792 SS_DRAM_TRP = 0x0b8,
793 SS_DRAM_TWR = 0x0c0,
794 SS_DRAM_TRFC = 0x0c8,
795 SS_DRAM_TMRD = 0x0d0,
796 SS_DRAM_TIWTR = 0x0e0,
797 SS_DRAM_PRECHARGE_WAIT = 0x0e8,
798 SS_DRAM_DIMM_STACK = 0x108,
799 SS_DRAM_EXT_WR_MODE2 = 0x110,
800 SS_DRAM_EXT_WR_MODE1 = 0x118,
801 SS_DRAM_EXT_WR_MODE3 = 0x120,
802 SS_DRAM_WAIR_CONTROL = 0x128,
803 SS_DRAM_RANK1_PRESENT = 0x130,
804 SS_DRAM_CHANNEL_DISABLED = 0x138,
805 SS_DRAM_SEL_LO_ADDR_BITS = 0x140,
806 SS_DRAM_DIMM_INIT = 0x1a0,
807 SS_DRAM_SW_DV_COUNT = 0x1b0,
808 SS_DRAM_HW_DMUX_CLK_INV = 0x1b8,
809 SS_DRAM_PAD_EN_CLK_INV = 0x1c0,
810 SS_DRAM_MODE_WRITE_STATUS = 0x208,
811 SS_DRAM_INIT_STATUS = 0x210,
812 SS_DRAM_DIMM_PRESENT = 0x218,
813 SS_DRAM_FAILOVER_STATUS = 0x220,
814 SS_DRAM_FAILOVER_MASK = 0x228,
815
816 SS_DRAM_PERF_CTL = 0x400, /* Performance counter section 10.3 of PRM 1.1 */
817 SS_DRAM_PERF_COUNT = 0x408,
818
819 SS_DRAM_ERROR_STATUS = 0x280, /* Error handling section 12.9 of PRM 1.1 */
820 SS_DRAM_ERROR_ADDRESS = 0x288,
821 SS_DRAM_ERROR_INJECT = 0x290,
822 SS_DRAM_ERROR_COUNTER = 0x298,
823 SS_DRAM_ERROR_LOCATION = 0x2a0,
824
825 SS_DRAM_OPEN_BANK_MAX = 0x028, /* Power management section 16.2 of PRM 1.1 */
826 SS_DRAM_PROG_TIME_CNTR = 0x048,
827
828 SS_DRAM_DBG_TRG_EN = 0x230, /* Hardware debug section 19.1 of PRM 1.1 */
829
830 SS_DRAM_ILLEGAL_REG = -1
831} ss_memory_ctl_reg_t;
832
833
834typedef struct {
835 tvaddr_t reg_tsb_base; /* the value stuffed into the register */
836 tvaddr_t base_addr; /* the pre-masked base addr to use on fault */
837 bool_t is_split;
838 uint_t tsb_size;
839 uint_t page_size; /* from the config register */
840} ss_tsb_info_t;
841
842 /*
843 * per strand mmu registers
844 */
845struct SS_MMU {
846 bool_t enabled; /* force real or virtual translations in priv/user mode */
847 bool_t is_immu;
848 tvaddr_t fault_addr;
849 uint64_t sfsr;
850 uint64_t sfar; /* DMMU only */
851 uint64_t va_watchpoint;
852 uint64_t tag_access_reg;
853 bool_t tsb_direct_ps1;
854};
855
856#define INVALID_SCRATCHPAD(addr) \
857 (((addr)>=0x20 && (addr)<=0x2f) || ((addr)>=0x3f))
858#define INVALID_HYP_SCRATCHPAD(addr) ((addr)>=0x3f)
859#define SSR_HSCRATCHPAD_INDEX (SSR_ScratchPad0)
860
861/*
862 * Types of demap operation are provided for Niagara 1
863 */
864enum SS_DEMAP {
865 NA_demap_page = 0x0,
866 NA_demap_context = 0x1,
867 NA_demap_all = 0x2,
868 NA_demap_reserved = 0x3,
869 NA_demap_init = 0xffff /* Special case for seperate ASI */
870};
871
872/*
873 * Sparc Error Registers implemented for Niagara 1
874 */
875struct SS_ERROR {
876 uint64_t enabled;
877#define NA_NCEEN MASK64(1,1)
878#define NA_CEEN MASK64(0,0)
879 uint64_t status;
880 uint64_t addr;
881 uint64_t inject;
882};
883
884/* Sparc Error Registers Section 12.4 of PRM 1.6 */
885#define NA_MAU_bit BIT(9)
886#define NA_DMSU_bit BIT(11)
887#define NA_NCU_bit BIT(12)
888#define NA_LDAU_bit BIT(13)
889#define NA_FRU_bit BIT(14)
890#define NA_FRC_bit BIT(15)
891#define NA_IRU_bit BIT(16)
892#define NA_IRC_bit BIT(17)
893#define NA_DTC_bit BIT(18)
894#define NA_DDC_bit BIT(19)
895#define NA_ITC_bit BIT(20)
896#define NA_IDC_bit BIT(21)
897#define NA_DMTU_bit BIT(22)
898#define NA_DMDU_bit BIT(23)
899#define NA_IMTU_bit BIT(24)
900#define NA_IMDU_bit BIT(25)
901#define NA_PRIV_bit BIT(29)
902#define NA_MEC_bit BIT(30)
903#define NA_MEU_bit BIT(31)
904
905
906#if ERROR_INJECTION
907
908#define IRC 0x00000001
909#define IRU 0x00000002
910#define FRC 0x00000004
911#define FRU 0x00000008
912#define IMTU 0x00000010
913#define IMDU 0x00000020
914#define DMTU 0x00000040
915#define DMDU 0x00000080
916#define DMSU 0x00000100
917#define ITC 0x00000200
918#define IDC 0x00000400
919#define DTC 0x00000800
920#define DDC 0x00001000
921#define MAU 0x00002000
922#define LDAC 0x00004000
923#define LDWC 0x00008000
924#define LDRC 0x00010000
925#define LDSC 0x00020000
926#define LDAU 0x00040000
927#define LDWU 0x00080000
928#define LDRU 0x00100000
929#define LDSU 0x00200000
930#define LTC 0x00400000
931#define LVU 0x00800000
932#define LRU 0x01000000
933#define DAC 0x02000000
934#define DSC 0x04000000
935#define DAU 0x08000000
936#define DSU 0x10000000
937#define DBU9 0x20000000
938#define DRAM 0x40000000
939#define DRC 0x80000000
940#define ANY_TYPE 0xffffffff
941
942#endif /* ERROR_INJECTION */
943
944
945
946/*
947 * macros used to determine the virtual core and strand Ids for Niagara 1
948 */
949#define SS_COREID_SHIFT 2
950#define THREAD_STS_SHIFT 8 /* vcore IDs stored in thread_status bits 12:8 */
951#define THREAD_STS_SPEC_EN_BIT 2
952#define THREAD_STS_SPEC_EN (1ull << THREAD_STS_SPEC_EN_BIT)
953#define THREAD_STS_ACTIVE 1
954#define THREAD_STS_TSTATE_SHIFT 16
955#define THREAD_STS_TSTATE_BITS 5
956#define THREAD_STS_TSTATE_IDLE 0
957#define THREAD_STS_TSTATE_WAIT 1
958#define THREAD_STS_TSTATE_HALT 0x2
959#define THREAD_STS_TSTATE_RUN 0x5
960#define THREAD_STS_TSTATE_SPEC_RUN 0x7
961#define THREAD_STS_TSTATE_SPEC_RDY 0x13
962#define THREAD_STS_TSTATE_RDY 0x19
963#define THREAD_STS_WAIT_I_SHIFT 40
964#define THREAD_STS_WAIT_O_SHIFT 44
965#define THREAD_STS_WAIT_S_SHIFT 48
966
967/* These two states are used only for sending idle/resume cmds to threads */
968#define THREAD_STS_TSTATE_CMD_IDLE 0x1f
969#define THREAD_STS_TSTATE_CMD_RUN 0x1c
970
971/*
972 * Macro for setting thread_status
973 */
974#define SET_THREAD_STS_SFSM( _npp, _nsp, _sts ) \
975 (_npp)->sfsm_state[(_nsp)->vcore_id] = (_sts)
976
977/*
978 * Strand structure for Niagara 1
979 */
980typedef struct SS_STRAND {
981 ss_trap_type_t pending_precise_tt;
982 ss_trap_type_t pending_async_tt;
983 bool_t flag_queue_irq[4]; /* see na_qnum_t */
984 na_queue_t nqueue[4]; /* see na_qnum_t */
985
986 bool_t mmu_bypass; /* no translation if hpstate in RED or HPriv modes */
987
988 /* IRQ lock is used whenever a irq vector bit needs
989 * to be set or cleared. Pre examining irq_vector
990 * should not require holding the lock, but
991 * attention must be set *after* vector modification.
992 */
993 pthread_mutex_t irq_lock;
994 uint64_t irq_vector; /* bit63 = highest priority */
995#define INTR_VEC_MASK MASK64(5,0)
996
997 uint16_t pri_context;
998 uint16_t sec_context;
999 uint16_t partid; /* partition ID */
1000
1001 SS_CORE_NUM_FIELDS
1002
1003 bool_t spec_en; /* %tsr.spec_en */
1004
1005 uint64_t strand_reg[SSR_Num_Regs];
1006
1007 ss_tsb_info_t immu_ctxt_zero_tsb_ps0;
1008 ss_tsb_info_t immu_ctxt_zero_tsb_ps1;
1009 ss_tsb_info_t immu_ctxt_nonzero_tsb_ps0;
1010 ss_tsb_info_t immu_ctxt_nonzero_tsb_ps1;
1011 ss_tsb_info_t dmmu_ctxt_zero_tsb_ps0;
1012 ss_tsb_info_t dmmu_ctxt_zero_tsb_ps1;
1013 ss_tsb_info_t dmmu_ctxt_nonzero_tsb_ps0;
1014 ss_tsb_info_t dmmu_ctxt_nonzero_tsb_ps1;
1015
1016 ss_tlb_t * dtlbp; /* the D-TLB this strand uses */
1017 ss_tlb_t * itlbp; /* the I-TLB this strand uses */
1018
1019 /* the MMU fault status registers ... */
1020 ss_mmu_t dmmu;
1021 ss_mmu_t immu;
1022
1023 ss_l1_cache_t * icachep; /* the instn cache this strand uses */
1024 ss_l1_cache_t * dcachep; /* the data cache this strand uses */
1025
1026 /* Error handling registers */
1027 ss_error_t error;
1028
1029 /* Other control registers */
1030 uint64_t lsu_control_raw;
1031
1032 /*
1033 * per CPU performance counters
1034 */
1035 uint32_t pic0;
1036 uint32_t pic1;
1037 uint64_t pcr;
1038 uint64_t pic0_sample_base;
1039 uint64_t pic1_sample_base;
1040} ss_strand_t;
1041
1042
1043/*
1044 * Niagara processor itself - composed of strands, TLBs and
1045 * other state.
1046 */
1047struct SS_PROC {
1048 config_proc_t * config_procp; /* points back to generic type */
1049
1050 /* data private for a Niagara cpu */
1051 uint64_t clkfreq;
1052 uint64_t core_mask;
1053 uint_t nwins;
1054 uint_t nglobals;
1055 uint_t maxtl;
1056 uint64_t ver;
1057 bool_t has_fpu;
1058
1059 tvaddr_t rstv_addr; /* Red State Trap Vector base - copied into v9 info */
1060
1061 uint_t str_to_idx[STRANDS_PER_CHIP]; /* strand/ss_strandp idx */
1062 uint_t nstrands; /* array size for strand/ss_strandp */
1063 sparcv9_cpu_t** strand;
1064
1065 /* linear array of strand specific info for this Niagara proc */
1066 ss_strand_t * ss_strandp;
1067
1068 uint_t nitlb;
1069 uint_t ndtlb;
1070 ss_tlb_t * itlbp; /* linear array of I tlbs - one per core */
1071 ss_tlb_t * dtlbp; /* linear array of D tlbs - one per core */
1072
1073 ss_tlb_spec_t itlbspec; /* parsed spec for each TLB ... */
1074 ss_tlb_spec_t dtlbspec; /* contains duplicated fields FIXME */
1075
1076 ss_l1_cache_t * icachep; /* linear array of icaches - 1/core */
1077 ss_l1_cache_t * dcachep; /* linear array of dcaches - 1/core */
1078 mod_arith_t * mod_arith_p; /* linear array of mod_arith_units */
1079
1080 bool_t is_inited; /* set once allocated simcpu_t for each strand */
1081
1082 /* SSI registers */
1083 ss_ssi_t * ssip;
1084 config_dev_t * ssi_devp; /* pseudo device for SSI regs */
1085
1086 /* JBI registers */
1087 ss_jbi_t * jbip;
1088 config_dev_t * jbi_devp; /* pseudo device for JBI Config regs */
1089
1090 /* IOB registers */
1091 ss_jbus_t * jbusp;
1092 config_dev_t * jbus_devp; /* pseudo device for IOB regs */
1093
1094 uint64_t core_avail; /* for IOB - set in ss_init() */
1095 ss_iob_t * iobp;
1096 config_dev_t * iob_devp; /* pseudo device for IOB regs */
1097
1098 /* Clock unit registers */
1099 ss_clock_t * clockp;
1100 config_dev_t * clock_devp; /* pseudo device for clock unit regs */
1101
1102 /* L2 Cache controllers */
1103 uint_t num_l2banks;
1104 ss_l2_cache_t * l2p;
1105 config_dev_t * l2_ctl_devp; /* pseudo device for l2 controller regs */
1106
1107 /* Memory controllers */
1108 uint_t num_mbanks;
1109 ss_dram_bank_t * mbankp;
1110 config_dev_t * dram_ctl_devp; /* pseudo device for dram ctrl regs */
1111
1112 error_conf_t * pend_errlistp; /* processor list of pending errors */
1113 pthread_mutex_t err_lock;
1114 bool_t error_check;
1115 error_proc_t * errorp;
1116
1117 pthread_mutex_t thread_sts_lock; /* call it cmp_lock ? */
1118 uint8_t sfsm_state[STRANDS_PER_CHIP];
1119
1120 proc_debug_t proc_debug;
1121
1122 bool_t rust_jbi_stores;
1123};
1124
1125/*
1126 * macros used in MMU area
1127 */
1128#define MMU_SFSR_FV (0x1 << 0)
1129#define MMU_SFSR_OW (0x1 << 1)
1130#define MMU_SFSR_W (0x1 << 2)
1131#define MMU_SFSR_CT_SHIFT 4
1132#define MMU_SFSR_CT (0x3 << MMU_SFSR_CT_SHIFT)
1133#define MMU_SFSR_E (0x1 << 6)
1134#define MMU_SFSR_FT_MASK (0x7f)
1135#define MMU_SFSR_FT_SHIFT (7)
1136#define MMU_SFSR_FT (MMU_SFSR_FT_MASK << MMU_SFSR_FT_SHIFT)
1137#define MMU_SFSR_ASI_MASK (0xff)
1138#define MMU_SFSR_ASI_SHIFT (16)
1139#define MMU_SFSR_ASI (MMU_SFSR_ASI_MASK << MMU_SFSR_ASI_SHIFT)
1140
1141#define MMU_SFSR_FT_PRIV (0x01) /* Privilege violation */
1142#define MMU_SFSR_FT_SO (0x02) /* side-effect load from E-page */
1143#define MMU_SFSR_FT_ATOMICIO (0x04) /* atomic access to IO address */
1144#define MMU_SFSR_FT_ASI (0x08) /* illegal ASI/VA/RW/SZ */
1145#define MMU_SFSR_FT_NFO (0x10) /* non-load from NFO page */
1146#define MMU_SFSR_FT_VARANGE (0x20) /* d-mmu, i-mmu branch, call, seq */
1147#define MMU_SFSR_FT_VARANGE2 (0x40) /* i-mmu jmpl or return */
1148
1149#define MMU_SFSR_MASK (MMU_SFSR_ASI | MMU_SFSR_FT | MMU_SFSR_E | \
1150 MMU_SFSR_CT | MMU_SFSR_W | MMU_SFSR_OW | \
1151 MMU_SFSR_FV)
1152
1153#define SS_TLB_IS_REAL(n) (bool_t)(((uint64_t)n >> 9) & 0x1)
1154
1155#define SET_DTLB_FAULT(_nsp, _va) do{ (_nsp)->dmmu.fault_addr = (_va); } while (0)
1156#define SET_ITLB_FAULT(_nsp, _va) do{ (_nsp)->immu.fault_addr = (_va); } while (0)
1157
1158#define SS_TLB_LRU (-1)
1159
1160#define SUN4U_TTED_V_BIT 63
1161
1162/*
1163 * niagara function prototypes
1164 */
1165uint64_t niagara_shuffle_sun4v_format(uint64_t);
1166
1167/*
1168 * external function prototypes used in this file
1169 */
1170extern bool_t ss_tlb_insert(simcpu_t*, ss_mmu_t*, ss_tlb_t*, uint_t, bool_t, uint64_t, uint_t);
1171extern void ss_setup_pseudo_devs(domain_t *domainp, ss_proc_t *procp);
1172
1173/* Processor specific parsing for "proc" elements in config file */
1174extern bool_t ss_parse_proc_entry(ss_proc_t*, domain_t *);
1175
1176/*
1177 * default CPU version values
1178 * from NG PRM rev 1.7, section 3.4.5
1179 */
1180#define SS_VER_MANUF 0x003eULL
1181#define SS_VER_IMPL 0x0023ULL
1182#define SS_VER_MASK 0x0020ULL
1183#define SS_VER_MAXGL 3
1184#define SS_VER_MAXTL 6
1185#define SS_VER_MAXWIN 7
1186
1187/*
1188 * %pcr
1189 */
1190#define SS_PCR_PRIV BIT(0)
1191#define SS_PCR_ST BIT(1)
1192#define SS_PCR_UT BIT(2)
1193#define SS_PCR_SL_SHIFT 4
1194#define SS_PCR_SL MASK64(6,SS_PCR_SL_SHIFT)
1195#define SS_PCR_OV0 BIT(8)
1196#define SS_PCR_OV1 BIT(9)
1197
1198#define SS_PCR_SL_SB_full 0
1199#define SS_PCR_SL_FP_intr_cnt 1
1200#define SS_PCR_SL_IC_miss 2
1201#define SS_PCR_SL_DC_miss 3
1202#define SS_PCR_SL_ITLB_miss 4
1203#define SS_PCR_SL_DTLB_miss 5
1204#define SS_PCR_SL_L2_imiss 6
1205#define SS_PCR_SL_L2_dmiss_ld 7
1206
1207#define SS_PCR_UT_ST (SS_PCR_UT | SS_PCR_ST)
1208#define SS_PCR_MASK (SS_PCR_OV1 | SS_PCR_OV0 | SS_PCR_SL | SS_PCR_UT | \
1209 SS_PCR_ST | SS_PCR_PRIV)
1210#define SS_PCR_CLEAR_ON_READ (0)
1211
1212#define SS_PCR_TEST_OVF_PENDING(_pcr) \
1213 (((_pcr) & (SS_PCR_OV0 | SS_PCR_OV1)) != 0)
1214
1215#endif /* NIAGARA1 */
1216
1217#ifdef __cplusplus
1218}
1219#endif
1220
1221#endif /* _NIAGARA_H_ */
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