* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: niagara.h
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* ========== Copyright Header End ============================================
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
#pragma ident "@(#)niagara.h 1.35 07/03/07 SMI"
#include <modarith_types.h>
#include "niagara_err_trap.h"
* Niagara specific definitions
* This table describes the trap behaviour for Niagara ..
* based on the existing state (User, Priv, Hyper mode),
* and to which state the trap is to be delivered.
* Moreover, what is the priority of the trap type.
SS_trap_legion_save_state
= 0x0, /* reserved on real HW */
SS_trap_power_on_reset
= 0x1,
SS_trap_watchdog_reset
= 0x2,
SS_trap_externally_initiated_reset
= 0x3,
SS_trap_software_initiated_reset
= 0x4,
SS_trap_RED_state_exception
= 0x5,
SS_trap_instruction_access_exception
= 0x8,
SS_trap_instruction_access_MMU_miss
= 0x9,
SS_trap_instruction_access_error
= 0xa,
SS_trap_illegal_instruction
= 0x10,
SS_trap_privileged_opcode
= 0x11,
SS_trap_unimplemented_LDD
= 0x12,
SS_trap_unimplemented_STD
= 0x13,
SS_trap_fp_disabled
= 0x20,
SS_trap_fp_exception_ieee_754
= 0x21,
SS_trap_fp_exception_other
= 0x22,
SS_trap_tag_overflow
= 0x23,
SS_trap_clean_window
= 0x24,
/* 0x25-0x27 clean_window reserved */
SS_trap_division_by_zero
= 0x28,
SS_trap_internal_processor_error
= 0x29,
SS_trap_data_access_exception
= 0x30,
SS_trap_data_access_MMU_miss
= 0x31,
SS_trap_data_access_error
= 0x32,
SS_trap_data_access_protection
= 0x33,
SS_trap_mem_address_not_aligned
= 0x34,
SS_trap_LDDF_mem_address_not_aligned
= 0x35,
SS_trap_STDF_mem_address_not_aligned
= 0x36,
SS_trap_privileged_action
= 0x37,
SS_trap_LDQF_mem_address_not_aligned
= 0x38,
SS_trap_STQF_mem_address_not_aligned
= 0x39,
SS_trap_instruction_real_translation_miss
= 0x3e,
SS_trap_data_real_translation_miss
= 0x3f,
SS_trap_async_data_error
= 0x40,
SS_trap_interrupt_level_1
= 0x41,
SS_trap_interrupt_level_2
= 0x42,
SS_trap_interrupt_level_3
= 0x43,
SS_trap_interrupt_level_4
= 0x44,
SS_trap_interrupt_level_5
= 0x45,
SS_trap_interrupt_level_6
= 0x46,
SS_trap_interrupt_level_7
= 0x47,
SS_trap_interrupt_level_8
= 0x48,
SS_trap_interrupt_level_9
= 0x49,
SS_trap_interrupt_level_a
= 0x4a,
SS_trap_interrupt_level_b
= 0x4b,
SS_trap_interrupt_level_c
= 0x4c,
SS_trap_interrupt_level_d
= 0x4d,
SS_trap_interrupt_level_e
= 0x4e,
SS_trap_interrupt_level_f
= 0x4f,
SS_trap_hstick_match
= 0x5e,
SS_trap_trap_level_zero
= 0x5f,
SS_trap_interrupt_vector_trap
= 0x60,
SS_trap_RA_watchpoint
= 0x61,
SS_trap_VA_watchpoint
= 0x62,
SS_trap_ECC_error
= 0x63,
SS_trap_fast_instruction_access_MMU_miss
= 0x64,
/* 0x65-0x67 reserved for fast_instruction_access_MMU_miss */
SS_trap_fast_data_access_MMU_miss
= 0x68,
/* 0x69-0x6b reserved for fast_data_access_MMU_miss */
SS_trap_fast_data_access_protection
= 0x6c,
/* 0x6d-0x6f reserved for fast_data_access_protection */
N1_trap_modular_arithmetic
= 0x74,
SS_trap_instruction_breakpoint
= 0x76,
N1_trap_data_error
= 0x78,
SS_trap_cpu_mondo_trap
= 0x7c,
SS_trap_dev_mondo_trap
= 0x7d,
SS_trap_resumable_error
= 0x7e,
SS_trap_nonresumable_error
= 0x7f,
SS_trap_spill_0_normal
= 0x80,
SS_trap_spill_1_normal
= 0x84,
SS_trap_spill_2_normal
= 0x88,
SS_trap_spill_3_normal
= 0x8c,
SS_trap_spill_4_normal
= 0x90,
SS_trap_spill_5_normal
= 0x94,
SS_trap_spill_6_normal
= 0x98,
SS_trap_spill_7_normal
= 0x9c,
SS_trap_spill_0_other
= 0xa0,
SS_trap_spill_1_other
= 0xa4,
SS_trap_spill_2_other
= 0xa8,
SS_trap_spill_3_other
= 0xac,
SS_trap_spill_4_other
= 0xb0,
SS_trap_spill_5_other
= 0xb4,
SS_trap_spill_6_other
= 0xb8,
SS_trap_spill_7_other
= 0xbc,
SS_trap_fill_0_normal
= 0xc0,
SS_trap_fill_1_normal
= 0xc4,
SS_trap_fill_2_normal
= 0xc8,
SS_trap_fill_3_normal
= 0xcc,
SS_trap_fill_4_normal
= 0xd0,
SS_trap_fill_5_normal
= 0xd4,
SS_trap_fill_6_normal
= 0xd8,
SS_trap_fill_7_normal
= 0xdc,
SS_trap_fill_0_other
= 0xe0,
SS_trap_fill_1_other
= 0xe4,
SS_trap_fill_2_other
= 0xe8,
SS_trap_fill_3_other
= 0xec,
SS_trap_fill_4_other
= 0xf0,
SS_trap_fill_5_other
= 0xf4,
SS_trap_fill_6_other
= 0xf8,
SS_trap_fill_7_other
= 0xfc,
SS_trap_trap_instruction
= 0x100,
SS_trap_htrap_instruction
= 0x180,
SS_trap_illegal_value
= 0x200
typedef struct TRAP_PRIORITY
{
ss_trap_type_t trap_type
;
extern ss_trap_list_t ss_trap_list
[];
* ASI's as implemented by Niagara
/* MANDATORY SPARC V9 ASIs */
SS_ASI_NUCLEUS
= 0x4 , /* RW Implicit Address Space, nucleus context, TL>0 */
SS_ASI_NUCLEUS_LITTLE
= 0xc , /* RW Implicit Address Space, nucleus context, TL>0 (LE) */
SS_ASI_AS_IF_USER_PRIMARY
= 0x10, /* RW Primary Address Space, user privilege */
SS_ASI_AS_IF_USER_SECONDARY
= 0x11, /* RW Secondary Address Space, user privilege */
SS_ASI_AS_IF_USER_PRIMARY_LITTLE
= 0x18, /* RW Primary Address Space, user privilege (LE) */
SS_ASI_AS_IF_USER_SECONDARY_LITTLE
= 0x19, /* RW Secondary Address Space, user privilege (LE) */
SS_ASI_PRIMARY
= 0x80, /* RW Implicit Primary Address space */
SS_ASI_SECONDARY
= 0x81, /* RW Implicit Secondary Address space */
SS_ASI_PRIMARY_NO_FAULT
= 0x82, /* R Primary Address space, no fault */
SS_ASI_SECONDARY_NO_FAULT
= 0x83, /* R Secondary Address space, no fault */
SS_ASI_PRIMARY_LITTLE
= 0x88, /* RW Implicit Primary Address space (LE) */
SS_ASI_SECONDARY_LITTLE
= 0x89, /* RW Implicit Secondary Address space (LE) */
SS_ASI_PRIMARY_NO_FAULT_LITTLE
= 0x8A, /* R Primary Address space, no fault (LE) */
SS_ASI_SECONDARY_NO_FAULT_LITTLE
= 0x8B, /* R Secondary Address space, no fault (LE) */
/* SunSPARC EXTENDED (non-V9) ASIs */
OLD_SS_ASI_PHYS_USE_EC
= 0x14, /* RW physical address, non-allocating in L1 cache */
OLD_SS_ASI_PHYS_BYPASS_EC_WITH_EBIT
= 0x15, /* RW Same as ASI_PHYS_USE_EC for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect */
SS_ASI_REAL_MEM
= 0x14, /* RW physical address, non-allocating in L1 cache */
SS_ASI_REAL_IO
= 0x15, /* RW Same as ASI_PHYS_USE_EC for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect */
SS_ASI_BLOCK_AS_IF_USER_PRIMARY
= 0x16, /* RW 64B block load/store, primary address space, user privilege */
SS_ASI_BLOCK_AS_IF_USER_SECONDARY
= 0x17, /* RW 64B block load/store, secondary address space, user privilege */
OLD_SS_ASI_PHYS_USE_EC_LITTLE
= 0x1C, /* RW physical address, non-allocating in L1 cache */
OLD_SS_ASI_PHYS_BYPASS_EC_WITH_EBIT_LITTLE
= 0x1D, /* RW Same as ASI_PHYS_USE_EC_LITTLE for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect (LE) */
SS_ASI_REAL_MEM_LITTLE
= 0x1C, /* RW physical address, non-allocating in L1 cache */
SS_ASI_REAL_IO_LITTLE
= 0x1D, /* RW Same as ASI_PHYS_USE_EC_LITTLE for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect (LE) */
SS_ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
= 0x1E, /* RW 64B block load/store, primary address space, user privilege (LE) */
SS_ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
= 0x1F, /* RW 64B block load/store, secondary address space, user privilege (LE) */
SS_ASI_SCRATCHPAD
= 0x20, /* Scratchpad Registers */
SS_ASI_MMU
= 0x21, /* MMU Registers */
SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_P
= 0x22, /* Block initializing store/128b atomic LDDA, primary address, user privilege */
SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_S
= 0x23, /* Block initializing store/128b atomic LDDA, secondary address, user privilege */
SS_ASI_QUAD_LDD
= 0x24, /* 128b atomic LDDA */
SS_ASI_QUEUE
= 0x25, /* Mondo Queue Pointers */
SS_ASI_QUAD_LDD_REAL
= 0x26, /* 128b atomic LDDA, real address */
SS_ASI_NUCLEUS_BLK_INIT_ST_QUAD_LDD
= 0x27, /* Block initializing store/128b atomic LDDA */
SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_P_LITTLE
= 0x2A, /* Block initializing store/128b atomic LDDA, primary address, user priv (LE) */
SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_S_LITTLE
= 0x2B, /* Block initializing store, secondary address, user privilege (LE) */
SS_ASI_QUAD_LDD_LITTLE
= 0x2C, /* 128b atomic LDDA (LE) */
SS_ASI_QUAD_LDD_REAL_LITTLE
= 0x2E, /* 128b atomic LDDA, real address (LE) */
SS_ASI_NUCLEUS_BLK_INIT_ST_QUAD_LDD_LITTLE
= 0x2F, /* Block initializing store/128b atomic LDDA (LE) */
SS_ASI_DIRECT_MAP_ECACHE
= 0x30, /* N1 PRM rev 1.4 - any type of access causes data_access_exception */
SS_ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0
= 0x31, /* DMMU Context Zero TSB Base PS 0 */
SS_ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1
= 0x32, /* DMMU Context Zero TSB Base PS 1 */
SS_ASI_DMMU_CTXT_ZERO_CONFIG
= 0x33, /* DMMU Context Zero Config Register */
SS_ASI_QUAD_LDD_PHYS
= 0x34, /* N1 PRM rev 1.4 - any type of access causes data_access_exception */
SS_ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0
= 0x35, /* IMMU Context Zero TSB Base PS0 */
SS_ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1
= 0x36, /* IMMU Context Zero TSB Base PS1 */
SS_ASI_IMMU_CTXT_ZERO_CONFIG
= 0x37, /* IMMU Context Zero Config Register */
SS_ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0
= 0x39, /* DMMU Context Nonzero TSB Base PS0 */
SS_ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1
= 0x3A, /* DMMU Context Nonzero TSB Base PS1 */
SS_ASI_DMMU_CTXT_NONZERO_CONFIG
= 0x3B, /* DMMU Context Non-Zero Config Register */
SS_ASI_QUAD_LDD_PHYS_LITTLE
= 0x3C, /* 128b atomic LDDA, physical address (LE) */
SS_ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0
= 0x3D, /* IMMU Context Nonzero TSB Base PS0 */
SS_ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1
= 0x3E, /* IMMU Context Nonzero TSB Base PS1 */
SS_ASI_IMMU_CTXT_NONZERO_CONFIG
= 0x3F, /* IMMU Context Non-Zero Config Register */
SS_ASI_STREAM_MA
= 0x40, /* Asynchronous Streaming Control Register */
SS_ASI_LSU_DIAG_REG
= 0x42, /* Diagnostic / Control register */
SS_ASI_ERROR_INJECT_REG
= 0x43, /* Error Injection Register */
SS_ASI_STM_CTL_REG
= 0x44, /* Self-timed Margin Control Register */
SS_ASI_LSU_CONTROL_REG
= 0x45, /* Load/Store Unit Control Register */
SS_ASI_DCACHE_DATA
= 0x46, /* Dcache data array diagnostics access */
SS_ASI_DCACHE_TAG
= 0x47, /* Dcache tag and valid bit diagnostics access */
SS_ASI_INTR_DISPATCH_STATUS
= 0x48, /* - any type of access causes data_access_exception */
SS_ASI_INTR_RECEIVE
= 0x49, /* - any type of access causes data_access_exception */
SS_ASI_UPA_CONFIG_REGISTER
= 0x4A, /* - any type of access causes data_access_exception */
SS_ASI_SPARC_ERROR_EN_REG
= 0x4B, /* Sparc error enable reg(synchronous ecc/parity errors) */
SS_ASI_SPARC_ERROR_STATUS_REG
= 0x4C, /* RW 0 Y Sparc error status reg */
SS_ASI_SPARC_ERROR_ADDRESS_REG
= 0x4D, /* RW 0 Y Sparc error address reg */
SS_ASI_ECACHE_TAG_DATA
= 0x4E, /* - any type of access causes data_access_exception */
SS_ASI_HYP_SCRATCHPAD
= 0x4F, /* RW 0-38 Y Hypervisor Scratchpad */
SS_ASI_IMMU
= 0x50, /* IMMU control register */
SS_ASI_IMMU_TSB_PS0_PTR_REG
= 0x51, /* IMMU TSB PS0 pointer register */
SS_ASI_IMMU_TSB_PS1_PTR_REG
= 0x52, /* IMMU TSB PS1 pointer register */
SS_ASI_ITLB_DATA_IN_REG
= 0x54, /* IMMU data in register */
SS_ASI_ITLB_DATA_ACCESS_REG
= 0x55, /* IMMU TLB Data Access Register */
SS_ASI_ITLB_TAG_READ_REG
= 0x56, /* IMMU TLB Tag Read Register */
SS_ASI_IMMU_DEMAP
= 0x57, /* IMMU TLB Demap */
SS_ASI_DMMU
= 0x58, /* DMMU control register */
SS_ASI_DMMU_TSB_PS0_PTR_REG
= 0x59, /* DMMU TSB PS0 pointer register */
SS_ASI_DMMU_TSB_PS1_PTR_REG
= 0x5A, /* DMMU TSB PS1 pointer register */
SS_ASI_DMMU_TSB_DIRECT_PTR_REG
= 0x5B, /* DMMU TSB Direct pointer register */
SS_ASI_DTLB_DATA_IN_REG
= 0x5C, /* DMMU data in register */
SS_ASI_DTLB_DATA_ACCESS_REG
= 0x5D, /* DMMU TLB Data Access Register */
SS_ASI_DTLB_TAG_READ_REG
= 0x5E, /* DMMU TLB Tag Read Register */
SS_ASI_DMMU_DEMAP
= 0x5F, /* DMMU TLB Demap */
SS_ASI_TLB_INVALIDATE_ALL
= 0x60, /* MMU TLB Invalidate Register */
SS_ASI_ICACHE_INSTR
= 0x66, /* Icache data array diagnostics access */
SS_ASI_ICACHE_TAG
= 0x67, /* Icache tag and valid bit diagnostics access */
SS_ASI_SWVR_INTR_RECEIVE
= 0x72, /* Interrupt Receive Register */
SS_ASI_SWVR_UDB_INTR_W
= 0x73, /* Interrupt Vector Dispatch Register */
SS_ASI_SWVR_UDB_INTR_R
= 0x74, /* Incoming Vector Register */
SS_ASI_ECACHE_W
= 0x76, /* - any type of access causes data_access_exception */
SS_ASI_UDB_INTR_W
= 0x77, /* - any type of access causes data_access_exception */
SS_ASI_ECACHE_R
= 0x7E, /* any type of access causes data_access_exception */
SS_ASI_UDB_INTR_R
= 0x7F, /* any type of access causes data_access_exception */
SS_ASI_PST8_P
= 0xC0, /* 8 bit partial pri */
SS_ASI_PST8_S
= 0xC1, /* 8 bit partial sec */
SS_ASI_PST16_P
= 0xC2, /* 16 bit partial pri */
SS_ASI_PST16_S
= 0xC3, /* 16 bit partial sec */
SS_ASI_PST32_P
= 0xC4, /* 32 bit partial pri */
SS_ASI_PST32_S
= 0xC5, /* 32 bit partial sec */
SS_ASI_PST8_PL
= 0xC8, /* 8 bit partial pri LE */
SS_ASI_PST8_SL
= 0xC9, /* 8 bit partial sec LE */
SS_ASI_PST16_PL
= 0xCA, /* 16 bit partial pri LE */
SS_ASI_PST16_SL
= 0xCB, /* 16 bit partial sec LE */
SS_ASI_PST32_PL
= 0xCC, /* 32 bit partial pri LE */
SS_ASI_PST32_SL
= 0xCD, /* 32 bit partial sec LE */
SS_ASI_FL8_P
= 0xD0, /* float 8 bit partial pri */
SS_ASI_FL8_S
= 0xD1, /* float 8 bit partial sec */
SS_ASI_FL16_P
= 0xD2, /* float 16 bit partial pri */
SS_ASI_FL16_S
= 0xD3, /* float 16 bit partial sec */
SS_ASI_FL8_PL
= 0xD8, /* float 8 bit partial pri LE*/
SS_ASI_FL8_SL
= 0xD9, /* float 8 bit partial sec LE*/
SS_ASI_FL16_PL
= 0xDA, /* float 16 bit partial pri LE */
SS_ASI_FL16_SL
= 0xDB, /* float 16 bit partial sec LE */
SS_ASI_BLK_COMMIT_P
= 0xE0, /* any type of access causes data_access_exception */
SS_ASI_BLK_COMMIT_S
= 0xE1, /* any type of access causes data_access_exception */
SS_ASI_BLK_INIT_ST_QUAD_LDD_P
= 0xE2, /* Block initializing store/128b atomic LDDA, primary address */
SS_ASI_BLK_INIT_ST_QUAD_LDD_S
= 0xE3, /* Block initializing store/128b atomic LDDA, secondary address */
SS_ASI_BLK_INIT_ST_QUAD_LDD_P_LITTLE
= 0xEA, /* Block initializing store/128b atomic LDDA, primary address (LE) */
SS_ASI_BLK_INIT_ST_QUAD_LDD_S_LITTLE
= 0xEB, /* Block initializing store/128b atomic LDDA, secondary address (LE) */
SS_ASI_BLK_P
= 0xF0, /* 64B block load/store, primary address */
SS_ASI_BLK_S
= 0xF1, /* 64B block load/store, secondary address */
SS_ASI_BLK_PL
= 0xF8, /* 64B block load/store, primary address (LE) */
SS_ASI_BLK_SL
= 0xF9 /* 64B block load/store, secondary address (LE) */
#define SS_ICACHE_SIZE 0x4000 /* 16K instn cache with 32B lines */
#define SS_DCACHE_SIZE 0x2000 /* 8K data cache with 16B lines */
/* L1 I-Cache and D-Cache Diagnostic Access Sections 18.3 and 18.4 of PRM 1.2 */
#define SS_ICACHE_DATA_LINEWORD_BITS 0x1ff8 /* line[12:6]word[5:3]rsv2[2:0] */
#define SS_ICACHE_DATA_WAY_BITS 0x30000 /* way[17:16] */
#define SS_ICACHE_TAG_LINE_BITS 0x1fc0 /* line[12:6]rsvd2[5:0] */
#define SS_ICACHE_TAG_WAY_BITS 0x30000 /* way[17:16] */
#define SS_DCACHE_DATA_BITS 0x1ff8 /* way[12:11]line[10:4]word[3]rsv2[2:0] */
#define SS_DCACHE_DATA_TAG_BITS 0x7ffffff800 /* tag[39:11] */
#define SS_DCACHE_TAG_WAYLINE_BITS 0x1ff0 /* way[12:11]line[10:4]rsvd1[3:0] */
#define STRANDSPERCORE 4 /* architectural, needed to match registers */
#define STRANDS_PER_CHIP (STRANDSPERCORE * CORESPERCHIP)
#define VALID_CORE_MASK 0xffffffffull
#define NO_STRAND ((uint_t)-1)
#define STRANDID2IDX(npp, s) \
(((uint_t)(s) < STRANDS_PER_CHIP) ? (npp)->str_to_idx[s] : NO_STRAND)
#define VALIDIDX(npp, tidx) \
((uint_t)(tidx) != NO_STRAND)
#define DEFAULT_ITLB_ENTRIES 64
#define DEFAULT_DTLB_ENTRIES 64
* L2 Cache controller definition
/* L2 Cache Diagnostic Access section 18.6 of PRM 1.2 */
typedef struct SS_L2_CACHE
{
#define L2_TAG MASK64(39,18)
#define L2_TAG_ECC MASK64(5,0)
#define L2_ODDEVEN_SHIFT 22
#define L2_WAY MASK64(21,18)
#define L2_LINE MASK64(17,8)
#define L2_BANK MASK64(7,6)
#define L2_WORD MASK64(5,3)
#define L2_VDSEL MASK64(22,22)
#define L2_DM_MASK MASK64(21,6)
* index into data with way/line/bank/word/oddeven bits (0xc-0xf of way unused)
* access 64bits: 32bit data, 7bit ECC, plus rsvd bits
* 8MB size: 3MB data, 3MB associated ecc+rsvd, 2MB wasted due to unused way bits
#define L2_DATA_SIZE ((L2_WAY|L2_LINE|L2_BANK|L2_WORD|(1<<L2_ODDEVEN_SHIFT))+8)
* index into tags with way/line/bank bits (0xc-0xf of way unused)
* access 64bits: 22bit tag, 6bit ECC plus rsvd bits (512K size)
#define L2_TAG_SIZE (((L2_WAY|L2_LINE|L2_BANK)>>3)+8)
* index into vuad with way/line/bank bits (0xc-0xf of way unused)
* access 64bits: valid/dirty or alloc/used bits and associated parity (64K size)
#define L2_VUAD_SIZE (((L2_LINE|L2_BANK|(L2_VDSEL>>4))>>3)+8)
uint64_t control
[L2_BANKS
];
#define L2_DBGEN MASK64(20,20)
#define L2_ERRORSTEER MASK64(19,15)
#define L2_SCRUBINTERVAL MASK64(14,3)
#define L2_SCRUBENABLE MASK64(2,2)
#define L2_DMMODE MASK64(1,1)
#define L2_DIS MASK64(0,0)
uint64_t error_enable
[L2_BANKS
];
#define L2_DBG_TRIG_EN MASK64(2,2)
#define L2_NCEEN MASK64(1,1)
#define L2_CEEN MASK64(0,0)
uint64_t error_status
[L2_BANKS
];
uint64_t error_address
[L2_BANKS
];
uint64_t error_inject
[L2_BANKS
];
uint64_t bist_ctl
[L2_BANKS
];
/* L2 Cache Error Registers section 12.6 of PRM 1.2 */
#define L2_MEU_bit BIT(63)
#define L2_MEC_bit BIT(62)
#define L2_RW_bit BIT(61)
#define L2_MODA_bit BIT(59)
#define L2_LDAC_bit BIT(53)
#define L2_LDAU_bit BIT(52)
#define L2_LDWC_bit BIT(51)
#define L2_LDWU_bit BIT(50)
#define L2_LDRC_bit BIT(49)
#define L2_LDRU_bit BIT(48)
#define L2_LDSC_bit BIT(47)
#define L2_LDSU_bit BIT(46)
#define L2_LTC_bit BIT(45)
#define L2_LRU_bit BIT(44)
#define L2_LVU_bit BIT(43)
#define L2_DAC_bit BIT(42)
#define L2_DAU_bit BIT(41)
#define L2_DRC_bit BIT(40)
#define L2_DRU_bit BIT(39)
#define L2_DSC_bit BIT(38)
#define L2_DSU_bit BIT(37)
#define L2_VEC_bit BIT(36)
#define L2_VEU_bit BIT(35)
#define L2_SYND_MASK MASK64(31,0)
#define L2_TID(val) (((uint64_t)val & 0x1f) << 54)
#define L2_FAKE_SYND_SINGLE 0x43 /* single bit error on bit 0 */
#define L2_FAKE_SYND_DOUBLE 0x33 /* uncorrectible double bit error */
#define L2_FAKE_SYND_POISON 0x03 /* poisoned ecc */
#define L2_PA_LINE(val) (val & MASK64(39,6))
#define L2_PA_QUAD(val) (val & MASK64(39,4))
#define L2_INDEX(val) (val & MASK64(21,6))
#define L2_DIR_IDX(val) (val & MASK64(13,4))
typedef struct NIAGAR_SSI
{
#define JBI_PORT_LOCN(n) (((uint64_t)n & 0x7f) << 51)
#define JBI_PORT_PRES(n) (((uint64_t)n & 0x7f) << 44)
#define JBI_MID(n) (((uint64_t)n & 0x3f) << 32)
#define JBI_IQ_HIGH(n) ((n & 0x7) << 28)
#define IOB_JBUS_TARGETS 32
#define IOB_JBUS_BUSY 0x20
uint64_t j_int_data0
[IOB_JBUS_TARGETS
];
uint64_t j_int_data1
[IOB_JBUS_TARGETS
];
uint64_t j_int_busy
[IOB_JBUS_TARGETS
];
/* IOB Interrupt Registers section 7.3 of PRM 1.2 */
#define IOB_INT_MAN_CPUID(n) ((n&MASK64(12,8))>>8)
#define IOB_INT_CTL_MASK MASK64(2,2)
#define IOB_INT_CTL_CLEAR MASK64(1,1)
#define IOB_INT_CTL_PEND MASK64(0,0)
uint64_t int_man
[IOB_DEV_MAX
];
uint8_t int_ctl
[IOB_DEV_MAX
]; /* max 3 bits ! */
pthread_mutex_t iob_lock
; /* hold this lock for any iob register access */
pthread_mutex_t int_vec_lock
; /* FIXME: to go away ! */
uint64_t int_vec_dis
; /* poke your neighbour - interrupt vector dispatch ! */
#define IOB_INT_VEC_INTR(n) (((n>>16)&3) == 0)
#define IOB_INT_VEC_RESET(n) (((n>>16)&3) == 1)
#define IOB_INT_VEC_IDLE(n) (((n>>16)&3) == 2)
#define IOB_INT_VEC_RESUME(n) (((n>>16)&3) == 3)
#define IOB_INT_VEC_THREAD(n) ((n>>8)&0x1f)
#define IOB_INT_VEC_VECTOR(n) (n&0x3f)
/* CPU throttle control section 16.1 of PRM 1.2 */
/* EFUSE Registers section 18.8 of PRM 1.2 */
/* Internal Margin Register section 19.1.3 of PRM 1.2 */
/* IOB Visibility Port Support section 19.2 of PRM 1.2 */
uint64_t l2_vis_compare_a
;
uint64_t l2_vis_compare_b
;
uint64_t db_enet_control
;
uint64_t db_enet_idleval
;
uint64_t db_jbus_control
;
uint64_t db_jbus_compare0
;
uint64_t db_jbus_compare1
;
uint64_t db_jbus_compare2
;
uint64_t db_jbus_compare3
;
/* Clock Unit section 11.1 of PRM 1.2 */
typedef struct SS_CLOCK
{
typedef struct SS_DRAM_BANK
{
uint8_t cas_addr_width
; /* DRAM controller section 15.5 of RPM 1.1 */
uint16_t refresh_counter
;
uint8_t channel_disabled
;
uint8_t sel_lo_addr_bits
;
uint8_t mode_write_status
;
uint8_t perf_ctl
; /* Performance counter section 10.3 of PRM 1.1 */
uint64_t error_status
; /* Error handling section 12.9 of PRM 1.1 */
uint32_t open_bank_max
; /* Power management section 16.2 of PRM 1.1 */
uint8_t dbg_trg_en
; /* Hardware debug section 19.1 of PRM 1.1 */
/* DRAM Error Registers in section 12.9 of PRM 1.2 */
#define DRAM_MEU_bit BIT(63)
#define DRAM_MEC_bit BIT(62)
#define DRAM_DAC_bit BIT(61)
#define DRAM_DAU_bit BIT(60)
#define DRAM_DSC_bit BIT(59)
#define DRAM_DSU_bit BIT(58)
#define DRAM_DBU_bit BIT(57)
#define DRAM_SYND_MASK MASK64(15,0)
#define DRAM_FAKE_SYND_SINGLE 0x00010101 /* nibble 31, bit 1 in error */
#define DRAM_FAKE_SYND_DOUBLE 0x00000101 /* uncorrectible multi-nibble error */
#define DRAM_FAKE_SYND_POISON 0x00008221 /* poisoned ecc */
/****************************************************************
* Niagara address mapped registers
* As well as ASI based registers, a number of Niagara state
* registers appear in the normal physical address space memory
* The following functions are provided as "virtual devices" within
* the physical address space, but in fact are components of the
* FIXME: There is an annoying architectural problem here in that
* if there is ever an MP version of Niagara, then we have a problem
* determining which Niagara each of these devices belongs to.
* For now though we know there is only one per domain.
****************************************************************/
NI_SSI_TIMEOUT
= 0x10088,
NI_JBI_CONFIG1
= 0x00000,
NI_JBI_CONFIG2
= 0x00008,
NI_JBI_INT_MRGN
= 0x00010,
NI_JBI_DEBUG_ARB
= 0x04100,
NI_JBI_ERR_INJECT
= 0x04800,
NI_JBI_PERF_CTL
= 0x20000,
NI_JBI_PERF_CNT
= 0x20008,
NI_JBI_ERR_CONFIG
= 0x10000,
NI_JBI_ERROR_LOG
= 0x10020,
NI_JBI_ERROR_OVF
= 0x10028,
NI_JBI_LOG_ENB
= 0x10030,
NI_JBI_SIG_ENB
= 0x10038,
NI_JBI_LOG_ADDR
= 0x10040,
NI_JBI_LOG_CTRL
= 0x10048,
NI_JBI_LOG_DATA0
= 0x10050,
NI_JBI_LOG_DATA1
= 0x10058,
NI_JBI_LOG_PAR
= 0x10060,
NI_JBI_LOG_NACK
= 0x10070,
NI_JBI_LOG_ARB
= 0x10078,
NI_JBI_L2_TIMEOUT
= 0x10080,
NI_JBI_ARB_TIMEOUT
= 0x10088,
NI_JBI_TRANS_TIMEOUT
= 0x10090,
NI_JBI_INTR_TIMEOUT
= 0x10098,
NI_J_INT_ADATA0
= 0x0600,
NI_J_INT_ADATA1
= 0x0700,
NI_PROC_SER_NUM
= 0x0820,
NI_INT_MRGN_REG
= 0x0850,
NI_L2_VIS_CONTROL
= 0x1800,
NI_L2_VIS_MASK_A
= 0x1820,
NI_L2_VIS_MASK_B
= 0x1828,
NI_L2_VIS_COMPARE_A
= 0x1830,
NI_L2_VIS_COMPARE_B
= 0x1838,
NI_L2_TRIG_DELAY
= 0x1840,
NI_IOB_VIS_SELECT
= 0x1000,
NI_DB_ENET_CONTROL
= 0x2000,
NI_DB_ENET_IDLEVAL
= 0x2008,
NI_DB_JBUS_CONTROL
= 0x2100,
NI_DB_JBUS_MASK0
= 0x2140,
NI_DB_JBUS_MASK1
= 0x2160,
NI_DB_JBUS_MASK2
= 0x2180,
NI_DB_JBUS_MASK3
= 0x21a0,
NI_DB_JBUS_COMPARE0
= 0x2148,
NI_DB_JBUS_COMPARE1
= 0x2168,
NI_DB_JBUS_COMPARE2
= 0x2188,
NI_DB_JBUS_COMPARE3
= 0x21a8,
NI_DB_JBUS_COUNT
= 0x2150
SS_CLOCK_DLL_CONTROL
= 0x18,
SS_CLOCK_JBUS_SYNC
= 0x28,
SS_CLOCK_DLL_BYPASS
= 0x38,
SS_CLOCK_DRAM_SYNC
= 0x30,
SS_L2_ERROR_ENABLE
= 0xa,
SS_L2_ERROR_STATUS
= 0xb,
SS_L2_ERROR_ADDRESS
= 0xc,
SS_DRAM_CAS_ADDR_WIDTH
= 0x000, /* DRAM controller section 15.5 of RPM 1.1 */
SS_DRAM_RAS_ADDR_WIDTH
= 0x008,
SS_DRAM_SCRUB_FREQ
= 0x018,
SS_DRAM_REFRESH_FREQ
= 0x020,
SS_DRAM_REFRESH_COUNTER
= 0x038,
SS_DRAM_SCRUB_ENABLE
= 0x040,
SS_DRAM_DRAM_TRCD
= 0x090,
SS_DRAM_PRECHARGE_WAIT
= 0x0e8,
SS_DRAM_DIMM_STACK
= 0x108,
SS_DRAM_EXT_WR_MODE2
= 0x110,
SS_DRAM_EXT_WR_MODE1
= 0x118,
SS_DRAM_EXT_WR_MODE3
= 0x120,
SS_DRAM_WAIR_CONTROL
= 0x128,
SS_DRAM_RANK1_PRESENT
= 0x130,
SS_DRAM_CHANNEL_DISABLED
= 0x138,
SS_DRAM_SEL_LO_ADDR_BITS
= 0x140,
SS_DRAM_DIMM_INIT
= 0x1a0,
SS_DRAM_SW_DV_COUNT
= 0x1b0,
SS_DRAM_HW_DMUX_CLK_INV
= 0x1b8,
SS_DRAM_PAD_EN_CLK_INV
= 0x1c0,
SS_DRAM_MODE_WRITE_STATUS
= 0x208,
SS_DRAM_INIT_STATUS
= 0x210,
SS_DRAM_DIMM_PRESENT
= 0x218,
SS_DRAM_FAILOVER_STATUS
= 0x220,
SS_DRAM_FAILOVER_MASK
= 0x228,
SS_DRAM_PERF_CTL
= 0x400, /* Performance counter section 10.3 of PRM 1.1 */
SS_DRAM_PERF_COUNT
= 0x408,
SS_DRAM_ERROR_STATUS
= 0x280, /* Error handling section 12.9 of PRM 1.1 */
SS_DRAM_ERROR_ADDRESS
= 0x288,
SS_DRAM_ERROR_INJECT
= 0x290,
SS_DRAM_ERROR_COUNTER
= 0x298,
SS_DRAM_ERROR_LOCATION
= 0x2a0,
SS_DRAM_OPEN_BANK_MAX
= 0x028, /* Power management section 16.2 of PRM 1.1 */
SS_DRAM_PROG_TIME_CNTR
= 0x048,
SS_DRAM_DBG_TRG_EN
= 0x230, /* Hardware debug section 19.1 of PRM 1.1 */
tvaddr_t reg_tsb_base
; /* the value stuffed into the register */
tvaddr_t base_addr
; /* the pre-masked base addr to use on fault */
uint_t page_size
; /* from the config register */
* per strand mmu registers
bool_t enabled
; /* force real or virtual translations in priv/user mode */
uint64_t sfar
; /* DMMU only */
#define INVALID_SCRATCHPAD(addr) \
(((addr)>=0x20 && (addr)<=0x2f) || ((addr)>=0x3f))
#define INVALID_HYP_SCRATCHPAD(addr) ((addr)>=0x3f)
#define SSR_HSCRATCHPAD_INDEX (SSR_ScratchPad0)
* Types of demap operation are provided for Niagara 1
NA_demap_init
= 0xffff /* Special case for seperate ASI */
* Sparc Error Registers implemented for Niagara 1
#define NA_NCEEN MASK64(1,1)
#define NA_CEEN MASK64(0,0)
/* Sparc Error Registers Section 12.4 of PRM 1.6 */
#define NA_MAU_bit BIT(9)
#define NA_DMSU_bit BIT(11)
#define NA_NCU_bit BIT(12)
#define NA_LDAU_bit BIT(13)
#define NA_FRU_bit BIT(14)
#define NA_FRC_bit BIT(15)
#define NA_IRU_bit BIT(16)
#define NA_IRC_bit BIT(17)
#define NA_DTC_bit BIT(18)
#define NA_DDC_bit BIT(19)
#define NA_ITC_bit BIT(20)
#define NA_IDC_bit BIT(21)
#define NA_DMTU_bit BIT(22)
#define NA_DMDU_bit BIT(23)
#define NA_IMTU_bit BIT(24)
#define NA_IMDU_bit BIT(25)
#define NA_PRIV_bit BIT(29)
#define NA_MEC_bit BIT(30)
#define NA_MEU_bit BIT(31)
#define ANY_TYPE 0xffffffff
#endif /* ERROR_INJECTION */
* macros used to determine the virtual core and strand Ids for Niagara 1
#define SS_COREID_SHIFT 2
#define THREAD_STS_SHIFT 8 /* vcore IDs stored in thread_status bits 12:8 */
#define THREAD_STS_SPEC_EN_BIT 2
#define THREAD_STS_SPEC_EN (1ull << THREAD_STS_SPEC_EN_BIT)
#define THREAD_STS_ACTIVE 1
#define THREAD_STS_TSTATE_SHIFT 16
#define THREAD_STS_TSTATE_BITS 5
#define THREAD_STS_TSTATE_IDLE 0
#define THREAD_STS_TSTATE_WAIT 1
#define THREAD_STS_TSTATE_HALT 0x2
#define THREAD_STS_TSTATE_RUN 0x5
#define THREAD_STS_TSTATE_SPEC_RUN 0x7
#define THREAD_STS_TSTATE_SPEC_RDY 0x13
#define THREAD_STS_TSTATE_RDY 0x19
#define THREAD_STS_WAIT_I_SHIFT 40
#define THREAD_STS_WAIT_O_SHIFT 44
#define THREAD_STS_WAIT_S_SHIFT 48
/* These two states are used only for sending idle/resume cmds to threads */
#define THREAD_STS_TSTATE_CMD_IDLE 0x1f
#define THREAD_STS_TSTATE_CMD_RUN 0x1c
* Macro for setting thread_status
#define SET_THREAD_STS_SFSM( _npp, _nsp, _sts ) \
(_npp)->sfsm_state[(_nsp)->vcore_id] = (_sts)
* Strand structure for Niagara 1
typedef struct SS_STRAND
{
ss_trap_type_t pending_precise_tt
;
ss_trap_type_t pending_async_tt
;
bool_t flag_queue_irq
[4]; /* see na_qnum_t */
na_queue_t nqueue
[4]; /* see na_qnum_t */
bool_t mmu_bypass
; /* no translation if hpstate in RED or HPriv modes */
/* IRQ lock is used whenever a irq vector bit needs
* to be set or cleared. Pre examining irq_vector
* should not require holding the lock, but
* attention must be set *after* vector modification.
pthread_mutex_t irq_lock
;
uint64_t irq_vector
; /* bit63 = highest priority */
#define INTR_VEC_MASK MASK64(5,0)
uint16_t partid
; /* partition ID */
bool_t spec_en
; /* %tsr.spec_en */
uint64_t strand_reg
[SSR_Num_Regs
];
ss_tsb_info_t immu_ctxt_zero_tsb_ps0
;
ss_tsb_info_t immu_ctxt_zero_tsb_ps1
;
ss_tsb_info_t immu_ctxt_nonzero_tsb_ps0
;
ss_tsb_info_t immu_ctxt_nonzero_tsb_ps1
;
ss_tsb_info_t dmmu_ctxt_zero_tsb_ps0
;
ss_tsb_info_t dmmu_ctxt_zero_tsb_ps1
;
ss_tsb_info_t dmmu_ctxt_nonzero_tsb_ps0
;
ss_tsb_info_t dmmu_ctxt_nonzero_tsb_ps1
;
ss_tlb_t
* dtlbp
; /* the D-TLB this strand uses */
ss_tlb_t
* itlbp
; /* the I-TLB this strand uses */
/* the MMU fault status registers ... */
ss_l1_cache_t
* icachep
; /* the instn cache this strand uses */
ss_l1_cache_t
* dcachep
; /* the data cache this strand uses */
/* Error handling registers */
/* Other control registers */
uint64_t lsu_control_raw
;
* per CPU performance counters
uint64_t pic0_sample_base
;
uint64_t pic1_sample_base
;
* Niagara processor itself - composed of strands, TLBs and
config_proc_t
* config_procp
; /* points back to generic type */
/* data private for a Niagara cpu */
tvaddr_t rstv_addr
; /* Red State Trap Vector base - copied into v9 info */
uint_t str_to_idx
[STRANDS_PER_CHIP
]; /* strand/ss_strandp idx */
uint_t nstrands
; /* array size for strand/ss_strandp */
/* linear array of strand specific info for this Niagara proc */
ss_strand_t
* ss_strandp
;
ss_tlb_t
* itlbp
; /* linear array of I tlbs - one per core */
ss_tlb_t
* dtlbp
; /* linear array of D tlbs - one per core */
ss_tlb_spec_t itlbspec
; /* parsed spec for each TLB ... */
ss_tlb_spec_t dtlbspec
; /* contains duplicated fields FIXME */
ss_l1_cache_t
* icachep
; /* linear array of icaches - 1/core */
ss_l1_cache_t
* dcachep
; /* linear array of dcaches - 1/core */
mod_arith_t
* mod_arith_p
; /* linear array of mod_arith_units */
bool_t is_inited
; /* set once allocated simcpu_t for each strand */
config_dev_t
* ssi_devp
; /* pseudo device for SSI regs */
config_dev_t
* jbi_devp
; /* pseudo device for JBI Config regs */
config_dev_t
* jbus_devp
; /* pseudo device for IOB regs */
uint64_t core_avail
; /* for IOB - set in ss_init() */
config_dev_t
* iob_devp
; /* pseudo device for IOB regs */
/* Clock unit registers */
config_dev_t
* clock_devp
; /* pseudo device for clock unit regs */
/* L2 Cache controllers */
config_dev_t
* l2_ctl_devp
; /* pseudo device for l2 controller regs */
config_dev_t
* dram_ctl_devp
; /* pseudo device for dram ctrl regs */
error_conf_t
* pend_errlistp
; /* processor list of pending errors */
pthread_mutex_t err_lock
;
pthread_mutex_t thread_sts_lock
; /* call it cmp_lock ? */
uint8_t sfsm_state
[STRANDS_PER_CHIP
];
* macros used in MMU area
#define MMU_SFSR_FV (0x1 << 0)
#define MMU_SFSR_OW (0x1 << 1)
#define MMU_SFSR_W (0x1 << 2)
#define MMU_SFSR_CT_SHIFT 4
#define MMU_SFSR_CT (0x3 << MMU_SFSR_CT_SHIFT)
#define MMU_SFSR_E (0x1 << 6)
#define MMU_SFSR_FT_MASK (0x7f)
#define MMU_SFSR_FT_SHIFT (7)
#define MMU_SFSR_FT (MMU_SFSR_FT_MASK << MMU_SFSR_FT_SHIFT)
#define MMU_SFSR_ASI_MASK (0xff)
#define MMU_SFSR_ASI_SHIFT (16)
#define MMU_SFSR_ASI (MMU_SFSR_ASI_MASK << MMU_SFSR_ASI_SHIFT)
#define MMU_SFSR_FT_PRIV (0x01) /* Privilege violation */
#define MMU_SFSR_FT_SO (0x02) /* side-effect load from E-page */
#define MMU_SFSR_FT_ATOMICIO (0x04) /* atomic access to IO address */
#define MMU_SFSR_FT_ASI (0x08) /* illegal ASI/VA/RW/SZ */
#define MMU_SFSR_FT_NFO (0x10) /* non-load from NFO page */
#define MMU_SFSR_FT_VARANGE (0x20) /* d-mmu, i-mmu branch, call, seq */
#define MMU_SFSR_FT_VARANGE2 (0x40) /* i-mmu jmpl or return */
#define MMU_SFSR_MASK (MMU_SFSR_ASI | MMU_SFSR_FT | MMU_SFSR_E | \
MMU_SFSR_CT | MMU_SFSR_W | MMU_SFSR_OW | \
#define SS_TLB_IS_REAL(n) (bool_t)(((uint64_t)n >> 9) & 0x1)
#define SET_DTLB_FAULT(_nsp, _va) do{ (_nsp)->dmmu.fault_addr = (_va); } while (0)
#define SET_ITLB_FAULT(_nsp, _va) do{ (_nsp)->immu.fault_addr = (_va); } while (0)
#define SUN4U_TTED_V_BIT 63
* niagara function prototypes
uint64_t niagara_shuffle_sun4v_format(uint64_t);
* external function prototypes used in this file
extern bool_t
ss_tlb_insert(simcpu_t
*, ss_mmu_t
*, ss_tlb_t
*, uint_t
, bool_t
, uint64_t, uint_t
);
extern void ss_setup_pseudo_devs(domain_t
*domainp
, ss_proc_t
*procp
);
/* Processor specific parsing for "proc" elements in config file */
extern bool_t
ss_parse_proc_entry(ss_proc_t
*, domain_t
*);
* default CPU version values
* from NG PRM rev 1.7, section 3.4.5
#define SS_VER_MANUF 0x003eULL
#define SS_VER_IMPL 0x0023ULL
#define SS_VER_MASK 0x0020ULL
#define SS_PCR_PRIV BIT(0)
#define SS_PCR_SL_SHIFT 4
#define SS_PCR_SL MASK64(6,SS_PCR_SL_SHIFT)
#define SS_PCR_OV0 BIT(8)
#define SS_PCR_OV1 BIT(9)
#define SS_PCR_SL_SB_full 0
#define SS_PCR_SL_FP_intr_cnt 1
#define SS_PCR_SL_IC_miss 2
#define SS_PCR_SL_DC_miss 3
#define SS_PCR_SL_ITLB_miss 4
#define SS_PCR_SL_DTLB_miss 5
#define SS_PCR_SL_L2_imiss 6
#define SS_PCR_SL_L2_dmiss_ld 7
#define SS_PCR_UT_ST (SS_PCR_UT | SS_PCR_ST)
#define SS_PCR_MASK (SS_PCR_OV1 | SS_PCR_OV0 | SS_PCR_SL | SS_PCR_UT | \
#define SS_PCR_CLEAR_ON_READ (0)
#define SS_PCR_TEST_OVF_PENDING(_pcr) \
(((_pcr) & (SS_PCR_OV0 | SS_PCR_OV1)) != 0)