Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / devtools / amd64 / include / ITYPES.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: ITYPES.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
/* %COPYRIGHT% */

#ifndef _ITYPES_H
#define _ITYPES_H

#pragma ident	"@(#)ITYPES.h	1.1"

#include "spix_sparc.h"
//#include "IHASH.h"
#include "INSTR.h"

#ifdef  __cplusplus
extern "C" {
#endif

  // ==== Instruction classification functions ====

  // True for valid instructions.  Returns false if ih >= NIHASH.
int ih_isvalid(int ih);

int ih_isnone(int ih);

  // ==== Memory access ====

  // True for instructions that load a value from memory.  This
  // includes all integer load instruc- tions, all FP load
  // instructions, and all atomic load/store instructions.
int ih_isload(int ih);

  // True for instructions that load a value from memory into an
  // integer register.  This includes all atomic load/store
  // instructions.
int ih_isiload(int ih);

  // True for instructions that unconditionally store a value to
  // memory.  This includes all integer store instructions, all FP
  // store instructions, and the LDSTUB, LDSTUBA, SWAP, and SWAPA
  // atomic load/store instructions.
int ih_isustore(int ih);

  // True for instructions that conditionally store a value to
  // memory.  This includes the CASA and CASXA instructions.
int ih_iscstore(int ih);

  // True for instructions that conditionally or unconditionally
  // store a value from an integer register into memory.  This
  // includes all atomic load/store instructions.
int ih_isistore(int ih);

  // True for instructions that conditionally or unconditionally
  // store any value into memory.  This includes all atomic load/store
  // instructions.
int ih_isstore(int ih);

  // ==== Integer arithmetic ====

  // True for instructions that perform an integer arithmetic or
  // logical operation.  This does not include load, store, branch,
  // or floating point instructions.
int ih_isalu(int ih);

  // ==== Control Transfer ====  

  // True if JMPL appears to function as register-indirect CALL.
int ih_isjmplcall(unsigned instr, int ih);

  // True if JMPL appears to return from subroutine.
int ih_isjmplreturn(unsigned instr, int ih);

  // True for CALL's and JMPL's calling subroutines.
int ih_iscall(unsigned instr, int ih);

  // True for RETURN's and JMPL's returning from subroutines.
int ih_isreturn(unsigned instr, int ih);

  // True for CALL, JMPL, and RETURN instructions.
int ih_isproc(int ih);

  // True for TCC instructions.
int ih_isticc(int ih);

  // True for delayed control transfer instructions.
int ih_isdcti(int ih);

  // True for CTI instructions.  This includes all DCTI, TCC, DONE,
  // and RETRY instructions.
int ih_iscti(int ih);

  // True for branch instructions with the annul bit set.
int ih_isannul(int ih);

  // True for conditional branch instructions, whether on the
  // "always" condition, the "never" condition, or any other
  // condition.  Note, this type is the union of the isubranch() and
  // is_cbranch() members below.
int ih_isbranch(int ih);

  // True for unconditional branch instructions.  This includes only
  // conditional branch instructions on the "always" condition.
  // Note, it does not include CALL, JMPL, or RETURN instructions.
int ih_isuncond(int ih);

  // True for conditional branch instructions.  This includes
  // conditional branch instructions on any condition other than
  // "always".
int ih_iscbranch(int ih);

  // True for conditional branches on the "always" condition that
  // also have the "annul" attribute set.
int ih_isbaa(int ih);

  // True for non-predicted branch instructions that are contingent
  // on the integer condition codes.
int ih_isbicc(int ih);

  // True for predicted branch instructions that are contingent on
  // the integer condition codes.
int ih_isbpcc(int ih);

  // True for branch instructions that are contingent on the value
  // of a register.
int ih_isbpr(int ih);

  // True for non-predicted branch instructions that are contingent
  // on the floating point condition codes.
int ih_isfbfcc(int ih);

  // True for predicted branch instructions that are contingent on
  // the floating point condition codes.
int ih_isfbpfcc(int ih);

  // ==== Conditional move ====

  // True for conditional integer register move instructions that
  // are contingent on either the integer or floating point
  // condition codes.
int ih_ismovcc(int ih);

  // True for conditional integer register move instructions that
  // are contingent on the value of a register.
int ih_ismovr(int ih);

  // True for conditional floating point register move instructions
  // that are contingent on either the integer or floating point
  // condition codes.
int ih_isfmovcc(int ih);

  // True for conditional floating point register move instructions
  // that are contingent on the value of a register.
int ih_isfmovr(int ih);

  // ==== Floating point operations ====

  // True for floating point instructions.  This includes all FPOP1
  // and FPOP2 instructions, all loads or stores to floating point
  // registers (including the %fsr register), the FBfcc and FBPfcc
  // instructions, the MOVcc instructions that use the %fcc
  // conditions, and all UltraSPARC extended "vis" instructions
  // (including those that do not use floating point registers).
int ih_isfp(int ih);

  // True for FPOP1 instructions as defined by the SPARC
  // Architecture Manual.
int ih_isfpop1(int ih);

  // ==== Condition code modifiers ====

  // True for instructions that use either the %xcc or %icc
  // condition codes.  This includes the RDCCR instruction.
int ih_isuseccr(int ih);

  // True for instructions that set either the %xcc or %icc
  // condition codes.  This includes the WRCCR instruction.
int ih_issetccr(int ih);

  // True for instructions that set any of the floating point
  // condition codes.  This includes the LDFSR and LDXFSR
  // instructions.
int ih_issetfcc(int ih);

  // ==== Architecture specific ====

  // True for instructions that are defined for the SPARC V8
  // architecture.
int ih_isv8(int ih);

  // True for instructions that are defined for the SPARC V9
  // architecture.  (It does not include any of the UltraSPARC
  // extended instructions.)
int ih_isv9(int ih);

  // True for the UltraSPARC extended "vis" instructions.
int ih_isvis(int ih);

  // ==== Privileged instructions ====

  // True for the privileged instructions.  It does not select
  // instructions that are privileged only for certain operands
  // (such as RDASR) or that are only privileged depending on the
  // processor's configuration (such as RDTICK).
int ih_ispriv(int ih);

  // ==== ???? ====

int ih_isfpcvt(int ih);

int ih_isany(int ih);

#ifdef  __cplusplus
}
#endif

#endif /* _ITYPES_H */