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* OpenSPARC T2 Processor File: ITYPES.h
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
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#pragma ident "@(#)ITYPES.h 1.1"
// ==== Instruction classification functions ====
// True for valid instructions. Returns false if ih >= NIHASH.
// ==== Memory access ====
// True for instructions that load a value from memory. This
// includes all integer load instruc- tions, all FP load
// instructions, and all atomic load/store instructions.
// True for instructions that load a value from memory into an
// integer register. This includes all atomic load/store
// True for instructions that unconditionally store a value to
// memory. This includes all integer store instructions, all FP
// store instructions, and the LDSTUB, LDSTUBA, SWAP, and SWAPA
// atomic load/store instructions.
// True for instructions that conditionally store a value to
// memory. This includes the CASA and CASXA instructions.
// True for instructions that conditionally or unconditionally
// store a value from an integer register into memory. This
// includes all atomic load/store instructions.
// True for instructions that conditionally or unconditionally
// store any value into memory. This includes all atomic load/store
// ==== Integer arithmetic ====
// True for instructions that perform an integer arithmetic or
// logical operation. This does not include load, store, branch,
// or floating point instructions.
// ==== Control Transfer ====
// True if JMPL appears to function as register-indirect CALL.
int ih_isjmplcall(unsigned instr
, int ih
);
// True if JMPL appears to return from subroutine.
int ih_isjmplreturn(unsigned instr
, int ih
);
// True for CALL's and JMPL's calling subroutines.
int ih_iscall(unsigned instr
, int ih
);
// True for RETURN's and JMPL's returning from subroutines.
int ih_isreturn(unsigned instr
, int ih
);
// True for CALL, JMPL, and RETURN instructions.
// True for TCC instructions.
// True for delayed control transfer instructions.
// True for CTI instructions. This includes all DCTI, TCC, DONE,
// and RETRY instructions.
// True for branch instructions with the annul bit set.
// True for conditional branch instructions, whether on the
// "always" condition, the "never" condition, or any other
// condition. Note, this type is the union of the isubranch() and
// is_cbranch() members below.
// True for unconditional branch instructions. This includes only
// conditional branch instructions on the "always" condition.
// Note, it does not include CALL, JMPL, or RETURN instructions.
// True for conditional branch instructions. This includes
// conditional branch instructions on any condition other than
int ih_iscbranch(int ih
);
// True for conditional branches on the "always" condition that
// also have the "annul" attribute set.
// True for non-predicted branch instructions that are contingent
// on the integer condition codes.
// True for predicted branch instructions that are contingent on
// the integer condition codes.
// True for branch instructions that are contingent on the value
// True for non-predicted branch instructions that are contingent
// on the floating point condition codes.
// True for predicted branch instructions that are contingent on
// the floating point condition codes.
// ==== Conditional move ====
// True for conditional integer register move instructions that
// are contingent on either the integer or floating point
// True for conditional integer register move instructions that
// are contingent on the value of a register.
// True for conditional floating point register move instructions
// that are contingent on either the integer or floating point
// True for conditional floating point register move instructions
// that are contingent on the value of a register.
// ==== Floating point operations ====
// True for floating point instructions. This includes all FPOP1
// and FPOP2 instructions, all loads or stores to floating point
// registers (including the %fsr register), the FBfcc and FBPfcc
// instructions, the MOVcc instructions that use the %fcc
// conditions, and all UltraSPARC extended "vis" instructions
// (including those that do not use floating point registers).
// True for FPOP1 instructions as defined by the SPARC
// ==== Condition code modifiers ====
// True for instructions that use either the %xcc or %icc
// condition codes. This includes the RDCCR instruction.
// True for instructions that set either the %xcc or %icc
// condition codes. This includes the WRCCR instruction.
// True for instructions that set any of the floating point
// condition codes. This includes the LDFSR and LDXFSR
// ==== Architecture specific ====
// True for instructions that are defined for the SPARC V8
// True for instructions that are defined for the SPARC V9
// architecture. (It does not include any of the UltraSPARC
// extended instructions.)
// True for the UltraSPARC extended "vis" instructions.
// ==== Privileged instructions ====
// True for the privileged instructions. It does not select
// instructions that are privileged only for certain operands
// (such as RDASR) or that are only privileged depending on the
// processor's configuration (such as RDTICK).