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920dae64 AT |
1 | <!-- interpreter=xml2reg args='-t'--> |
2 | <register_list> | |
3 | <register name="SOC_ERROR_INTERRUPT_ENABLE_REG (SOC_ERROR_INTERRUPT_ENABLE_REG)"> | |
4 | <class_name>N2_SocErrorIntrEnReg</class_name> | |
5 | <submodule>N2</submodule> | |
6 | <comment> | |
7 | SOC Error Interrupt Enable Register. This register controls which | |
8 | errors will generate an Error Indication (SOC) error packet to the | |
9 | CPX. If the EIE bit is set, an Error Indication (SOC) error packet | |
10 | will always be sent to the CPX irrespective of whether the error | |
11 | caused the transaction to be terminated or not. The Correctable SOC | |
12 | errors will set an error code of 0b'01' in the error field of the | |
13 | packaet with uncorrectable SOC errors set an error code of 0b'10' in | |
14 | the error field. TABLE 12-52 shows the format of the SOC Error Interrupt Enable Register. TABLE 12-52 | |
15 | SOC Error Interrupt Enable Register - SOC_ERROR_INTERRUPT_ENABLE_REG (0x80-0000-3010) | |
16 | </comment> | |
17 | <inherits>n2/lib/ras/xml/N2_SocErrorReg.xml</inherits> | |
18 | <base_address>0x8000003010ULL</base_address> | |
19 | <count>1</count> | |
20 | <stride>8</stride> | |
21 | <priv>yes</priv> | |
22 | <field name="DUMMY1"> | |
23 | <start_offset>63</start_offset> | |
24 | <end_offset>63</end_offset> | |
25 | <initial_value>0</initial_value> | |
26 | <protection>RO</protection> | |
27 | <field_type>ZERO</field_type> | |
28 | <comment> | |
29 | Unused. | |
30 | </comment> | |
31 | <format type="hex"/> | |
32 | </field> | |
33 | </register> | |
34 | </register_list> |