[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / api / memsync / src / LoadStoreEntry.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: LoadStoreEntry.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
#ifndef _LOADSTOREENTRY_H
#define _LOADSTOREENTRY_H
/************************************************************************
**  
**  Copyright (C) 2002, Sun Microsystems, Inc.
**
**  Sun considers its source code as an unpublished, proprietary
**  trade secret and it is available only under strict license provisions.
**  This copyright notice is placed here only to protect Sun in the event 
**  the source is deemed a published work. Disassembly, decompilation,
**  or other means of reducing the object code to human readable form
**  is prohibited by the license agreement under which this code is
**  provided to the user or company in possession of this copy."
**
*************************************************************************/
#include <iostream>

#include "MemorySyncDefs.h"
#include "MemoryAccessEntry.h"
#include "MemoryAccessBuffer.h"
#include "LoadStoreCmd.h"
#include <list>
 
class LoadStoreEntry {
    
  public:
    /**
     * Default constructor
     */
    LoadStoreEntry();

    LoadStoreEntry(LoadStoreCmd& cmd); 

    /**
     * Copy constructor
     * 
     * @param orig The LoadStoreEntry object to copy.
     */
    LoadStoreEntry( const LoadStoreEntry &orig );
    
    /**
     * Destructor
     */
    virtual ~LoadStoreEntry();
    
    /**
     * Equality operator
     * 
     * @param rhs The right hand side of the equality operator
     * @return Return true if this objec and rhs are equal, 
     * otherwise return false
     */
    bool operator==( const LoadStoreEntry &rhs ) const;
    
    /**
     * Assignment operator
     * 
     * @param rhs The right hand side of the assignment operator.
     * @return The lvalue of the assignment.
     */
    const LoadStoreEntry & operator=( const LoadStoreEntry &rhs );
    
    /**
     * Return a string representation of this LoadStoreEntry object. 
     */
    std::string toString() const;

    void setLink2(std::list<MemoryAccessEntry>::iterator link2) { link2_ = link2; vlink2_ = true; }
    void setLink2Valid (bool valid) { vlink2_ = valid; }
    
    void setLink(std::list<MemoryAccessEntry>::iterator link) { link_ = link; vlink_ = true; }
    void setLinkValid (bool valid) { vlink_ = valid; }
    void setState(enum LS_ENTRY_STATE state) { state_ = state; }
    void setExecuted (bool exe) { executed_ = exe; }
    void setSizeV (uint8_t sizev) { vbyte_ = sizev; }
    void setData (uint64_t data);
    void setDataOnly (uint64_t data) { data_ = data; }
    void setSwitchData (bool switchData) { switchData_ = switchData; }
    void setCoreId (uint32_t cid) { cid_ = cid; }
    void setThrdId (uint32_t tid) { tid_ = tid; }
    void setItype  (enum INSTR_TYPE itype) { itype_ = itype; }
    void setDsrc(enum DATA_SRC dsrc)  { dsrc_ = dsrc; }
    void setIseq (uint64_t iseq) { iseq_ = iseq; }

    std::list<MemoryAccessEntry>::iterator getLink2() const { return link2_; }
    bool                isLink2Valid() const { return vlink2_; }

    std::list<MemoryAccessEntry>::iterator getLink() const { return link_; }
    enum DATA_SRC   getDsrc() const { return dsrc_; }
    enum INSTR_TYPE     getItype() const { return itype_; }
    enum LS_ENTRY_STATE getState() const { return state_; }
    uint64_t            getIseq() const { return iseq_; }
    uint64_t            getId() const { return id_; }
    uint32_t            getSize() const { return size_; }
    uint64_t            getAddr() const { return addr_; }
    uint64_t            getData() const { return data_; }
    uint32_t            getCoreId() const { return cid_; }
    uint32_t            getThrdId() const { return tid_; }
    uint8_t             getVbyte() const { return vbyte_; }
    uint8_t             getSizeV() const { return vbyte_; } 
    bool                isValid() const { return valid_; }
    bool                isLinkValid() const { return vlink_; }
    bool                isExecuted() const { return executed_; }
    bool                isDataValid() const { return (state_ != LS_NEW); }
    bool                isIssued() const { return (state_ != LS_NEW && state_ != LS_TDATA &&
						   state_ != LS_RDATA); }
    bool                isSwitchData() const { return switchData_; }
    bool                isRMOstore() const { return ((itype_ == ITYPE_BLOCK_STORE) ||
						     (itype_ == ITYPE_STORE_INIT));  }
    bool                isIO() const { return ((addr_ & IO_ADDR_BIT_MASK) == 0 ? false : true); } 
  protected:
    
  private:
    std::list<MemoryAccessEntry>::iterator link_;
    enum INSTR_TYPE     itype_;
    /* For all stores in N1, and normal stores in N2, the state diagram is as follows:
       
                          SC          SA        SU
       LS_NEW -> LS_TDATA -> LS_ISSUE -> LS_ACK -> LS_UPDATE 
             |       ^                            |
             |       |                            +-> LS_INV
	     +-> LS_RDATA                      

       For RMO Store in N2, the state diagram is as follows:

       
                          SC         
       LS_NEW -> LS_TDATA -> LS_ISSUE -> LS_INV 
             |       ^                               
             |       |                               
	     +-> LS_RDATA                      


       For Load Buffer, the state diagram is simply as
       
       LS_NEW 

       For Fetch Buffer, the state diagram is as follows:
       LS_NEW -> LS_RDATA -> LS_ACK

    */         
    enum LS_ENTRY_STATE state_;
    enum DATA_SRC       dsrc_;     // load data source
    uint64_t            iseq_;     // load store instruction sequence
    uint64_t            id_;
    uint64_t            addr_;
    uint64_t            data_;
    uint32_t            size_;
    uint32_t            tid_;     // tid_ & cid_ are for identification, good for debug
    uint32_t            cid_;
    uint8_t             vbyte_;
    bool                valid_;
    bool                vlink_;
    bool                executed_;
    /* Atomic instruction consists of two parts: load and store. However, for CAS
       instruction, if the comparison is a false, then the value of the addressed
       memory is not changed. In this case, Riesling won't send a store transaction 
       to the memory, thus no store side callback. The switchData_ indicates 
       if the memory data will be changed for an atomic instruction. It is a false 
       only if the atomic instruction is a CAS and its comparsion results in a false. 
    */
    bool                switchData_;
    /* The following two parameters are introduced primarily for the memory sync model
       to work in Niagara 1 swerver-memory.cc environment. In that environment, 
       although the data source is known at MEM_ISSUE stage, the store buffer 
       data is not availabe at this moment. Hence, if a load with STB as data
       source, there is no way to get data. To simplify the code needed to 
       modify in swerver-memory.cc, a link to the MemoryAccessEntry is provided 
       so that when the store buffer entry data is ready, the data can be forwarded
       to the corresponding LoadData Entry in MAB.
    */
    std::list<MemoryAccessEntry>::iterator link2_;
    bool                vlink2_;
    
    /* The following parameter is introduced for working in Niagara 1 swerver-memory.cc 
       environment. In that environment, store data is set at PCX_L2 stage. This field
       is needed to indicates which entry has a valid data already. Checking address 
       is not reliable since there may be entry with same addresses. Updating the latest
       one is also not ok since there may be two issues before PCX_L2 signal is sent.
       N2 environment should not have this problem since data is supposed to come with
       the issue command.
    */
    //    bool                vdata_;

  };
  
#endif /* _LOADSTOREENTRY_H */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: LoadStoreEntry.h
	5	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	6	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
	7	*
	8	* The above named program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public
	10	* License version 2 as published by the Free Software Foundation.
	11	*
	12	* The above named program is distributed in the hope that it will be
	13	* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public
	18	* License along with this work; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
	20	*
	21	* ========== Copyright Header End ============================================
	22	*/
	23	#ifndef _LOADSTOREENTRY_H
	24	#define _LOADSTOREENTRY_H
	25	/************************************************************************
	26	**
	27	** Copyright (C) 2002, Sun Microsystems, Inc.
	28	**
	29	** Sun considers its source code as an unpublished, proprietary
	30	** trade secret and it is available only under strict license provisions.
	31	** This copyright notice is placed here only to protect Sun in the event
	32	** the source is deemed a published work. Disassembly, decompilation,
	33	** or other means of reducing the object code to human readable form
	34	** is prohibited by the license agreement under which this code is
	35	** provided to the user or company in possession of this copy."
	36	**
	37	*************************************************************************/
	38	#include <iostream>
	39
	40	#include "MemorySyncDefs.h"
	41	#include "MemoryAccessEntry.h"
	42	#include "MemoryAccessBuffer.h"
	43	#include "LoadStoreCmd.h"
	44	#include <list>
	45
	46	class LoadStoreEntry {
	47
	48	public:
	49	/**
	50	* Default constructor
	51	*/
	52	LoadStoreEntry();
	53
	54	LoadStoreEntry(LoadStoreCmd& cmd);
	55
	56	/**
	57	* Copy constructor
	58	*
	59	* @param orig The LoadStoreEntry object to copy.
	60	*/
	61	LoadStoreEntry( const LoadStoreEntry &orig );
	62
	63	/**
	64	* Destructor
65	*/
66	virtual ~LoadStoreEntry();
67
68	/**
69	* Equality operator
70	*
71	* @param rhs The right hand side of the equality operator
72	* @return Return true if this objec and rhs are equal,
73	* otherwise return false
74	*/
75	bool operator==( const LoadStoreEntry &rhs ) const;
76
77	/**
78	* Assignment operator
79	*
80	* @param rhs The right hand side of the assignment operator.
81	* @return The lvalue of the assignment.
82	*/
83	const LoadStoreEntry & operator=( const LoadStoreEntry &rhs );
84
85	/**
86	* Return a string representation of this LoadStoreEntry object.
87	*/
88	std::string toString() const;
89
90	void setLink2(std::list<MemoryAccessEntry>::iterator link2) { link2_ = link2; vlink2_ = true; }
91	void setLink2Valid (bool valid) { vlink2_ = valid; }
92
93	void setLink(std::list<MemoryAccessEntry>::iterator link) { link_ = link; vlink_ = true; }
94	void setLinkValid (bool valid) { vlink_ = valid; }
95	void setState(enum LS_ENTRY_STATE state) { state_ = state; }
96	void setExecuted (bool exe) { executed_ = exe; }
97	void setSizeV (uint8_t sizev) { vbyte_ = sizev; }
98	void setData (uint64_t data);
99	void setDataOnly (uint64_t data) { data_ = data; }
100	void setSwitchData (bool switchData) { switchData_ = switchData; }
101	void setCoreId (uint32_t cid) { cid_ = cid; }
102	void setThrdId (uint32_t tid) { tid_ = tid; }
103	void setItype (enum INSTR_TYPE itype) { itype_ = itype; }
104	void setDsrc(enum DATA_SRC dsrc) { dsrc_ = dsrc; }
105	void setIseq (uint64_t iseq) { iseq_ = iseq; }
106
107	std::list<MemoryAccessEntry>::iterator getLink2() const { return link2_; }
108	bool isLink2Valid() const { return vlink2_; }
109
110	std::list<MemoryAccessEntry>::iterator getLink() const { return link_; }
111	enum DATA_SRC getDsrc() const { return dsrc_; }
112	enum INSTR_TYPE getItype() const { return itype_; }
113	enum LS_ENTRY_STATE getState() const { return state_; }
114	uint64_t getIseq() const { return iseq_; }
115	uint64_t getId() const { return id_; }
116	uint32_t getSize() const { return size_; }
117	uint64_t getAddr() const { return addr_; }
118	uint64_t getData() const { return data_; }
119	uint32_t getCoreId() const { return cid_; }
120	uint32_t getThrdId() const { return tid_; }
121	uint8_t getVbyte() const { return vbyte_; }
122	uint8_t getSizeV() const { return vbyte_; }
123	bool isValid() const { return valid_; }
124	bool isLinkValid() const { return vlink_; }
125	bool isExecuted() const { return executed_; }
126	bool isDataValid() const { return (state_ != LS_NEW); }
127	bool isIssued() const { return (state_ != LS_NEW && state_ != LS_TDATA &&
128	state_ != LS_RDATA); }
129	bool isSwitchData() const { return switchData_; }
130	bool isRMOstore() const { return ((itype_ == ITYPE_BLOCK_STORE) \|\|
131	(itype_ == ITYPE_STORE_INIT)); }
132	bool isIO() const { return ((addr_ & IO_ADDR_BIT_MASK) == 0 ? false : true); }
133	protected:
134
135	private:
136	std::list<MemoryAccessEntry>::iterator link_;
137	enum INSTR_TYPE itype_;
138	/* For all stores in N1, and normal stores in N2, the state diagram is as follows:
139
140	SC SA SU
141	LS_NEW -> LS_TDATA -> LS_ISSUE -> LS_ACK -> LS_UPDATE
142	\| ^ \|
143	\| \| +-> LS_INV
144	+-> LS_RDATA
145
146	For RMO Store in N2, the state diagram is as follows:
147
148
149	SC
150	LS_NEW -> LS_TDATA -> LS_ISSUE -> LS_INV
151	\| ^
152	\| \|
153	+-> LS_RDATA
154
155
156	For Load Buffer, the state diagram is simply as
157
158	LS_NEW
159
160	For Fetch Buffer, the state diagram is as follows:
161	LS_NEW -> LS_RDATA -> LS_ACK
162
163	*/
164	enum LS_ENTRY_STATE state_;
165	enum DATA_SRC dsrc_; // load data source
166	uint64_t iseq_; // load store instruction sequence
167	uint64_t id_;
168	uint64_t addr_;
169	uint64_t data_;
170	uint32_t size_;
171	uint32_t tid_; // tid_ & cid_ are for identification, good for debug
172	uint32_t cid_;
173	uint8_t vbyte_;
174	bool valid_;
175	bool vlink_;
176	bool executed_;
177	/* Atomic instruction consists of two parts: load and store. However, for CAS
178	instruction, if the comparison is a false, then the value of the addressed
179	memory is not changed. In this case, Riesling won't send a store transaction
180	to the memory, thus no store side callback. The switchData_ indicates
181	if the memory data will be changed for an atomic instruction. It is a false
182	only if the atomic instruction is a CAS and its comparsion results in a false.
183	*/
184	bool switchData_;
185	/* The following two parameters are introduced primarily for the memory sync model
186	to work in Niagara 1 swerver-memory.cc environment. In that environment,
187	although the data source is known at MEM_ISSUE stage, the store buffer
188	data is not availabe at this moment. Hence, if a load with STB as data
189	source, there is no way to get data. To simplify the code needed to
190	modify in swerver-memory.cc, a link to the MemoryAccessEntry is provided
191	so that when the store buffer entry data is ready, the data can be forwarded
192	to the corresponding LoadData Entry in MAB.
193	*/
194	std::list<MemoryAccessEntry>::iterator link2_;
195	bool vlink2_;
196
197	/* The following parameter is introduced for working in Niagara 1 swerver-memory.cc
198	environment. In that environment, store data is set at PCX_L2 stage. This field
199	is needed to indicates which entry has a valid data already. Checking address
200	is not reliable since there may be entry with same addresses. Updating the latest
201	one is also not ok since there may be two issues before PCX_L2 signal is sent.
202	N2 environment should not have this problem since data is supposed to come with
203	the issue command.
204	*/
205	// bool vdata_;
206
207	};
208
209	#endif /* _LOADSTOREENTRY_H */