sam-t2/sam/cpus/vonk/ss/api/memsync/src/LoadStoreEntry.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: LoadStoreEntry.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
#ifndef _LOADSTOREENTRY_H
#define _LOADSTOREENTRY_H
/************************************************************************
**
**  Copyright (C) 2002, Sun Microsystems, Inc.
**
**  Sun considers its source code as an unpublished, proprietary
**  trade secret and it is available only under strict license provisions.
**  This copyright notice is placed here only to protect Sun in the event
**  the source is deemed a published work. Disassembly, decompilation,
**  or other means of reducing the object code to human readable form
**  is prohibited by the license agreement under which this code is
**  provided to the user or company in possession of this copy."
**
*************************************************************************/
#include <iostream>

#include "MemorySyncDefs.h"
#include "MemoryAccessEntry.h"
#include "MemoryAccessBuffer.h"
#include "LoadStoreCmd.h"
#include <list>

class LoadStoreEntry {

  public:
    /**
     * Default constructor
     */
    LoadStoreEntry();

    LoadStoreEntry(LoadStoreCmd& cmd);

    /**
     * Copy constructor
     *
     * @param orig The LoadStoreEntry object to copy.
     */
    LoadStoreEntry( const LoadStoreEntry &orig );

    /**
     * Destructor
     */
    virtual ~LoadStoreEntry();

    /**
     * Equality operator
     *
     * @param rhs The right hand side of the equality operator
     * @return Return true if this objec and rhs are equal,
     * otherwise return false
     */
    bool operator==( const LoadStoreEntry &rhs ) const;

    /**
     * Assignment operator
     *
     * @param rhs The right hand side of the assignment operator.
     * @return The lvalue of the assignment.
     */
    const LoadStoreEntry & operator=( const LoadStoreEntry &rhs );

    /**
     * Return a string representation of this LoadStoreEntry object.
     */
    std::string toString() const;

    void setLink2(std::list<MemoryAccessEntry>::iterator link2) { link2_ = link2; vlink2_ = true; }
    void setLink2Valid (bool valid) { vlink2_ = valid; }

    void setLink(std::list<MemoryAccessEntry>::iterator link) { link_ = link; vlink_ = true; }
    void setLinkValid (bool valid) { vlink_ = valid; }
    void setState(enum LS_ENTRY_STATE state) { state_ = state; }
    void setExecuted (bool exe) { executed_ = exe; }
    void setSizeV (uint8_t sizev) { vbyte_ = sizev; }
    void setData (uint64_t data);
    void setDataOnly (uint64_t data) { data_ = data; }
    void setSwitchData (bool switchData) { switchData_ = switchData; }
    void setCoreId (uint32_t cid) { cid_ = cid; }
    void setThrdId (uint32_t tid) { tid_ = tid; }
    void setItype  (enum INSTR_TYPE itype) { itype_ = itype; }
    void setDsrc(enum DATA_SRC dsrc)  { dsrc_ = dsrc; }
    void setIseq (uint64_t iseq) { iseq_ = iseq; }

    std::list<MemoryAccessEntry>::iterator getLink2() const { return link2_; }
    bool                isLink2Valid() const { return vlink2_; }

    std::list<MemoryAccessEntry>::iterator getLink() const { return link_; }
    enum DATA_SRC   getDsrc() const { return dsrc_; }
    enum INSTR_TYPE     getItype() const { return itype_; }
    enum LS_ENTRY_STATE getState() const { return state_; }
    uint64_t            getIseq() const { return iseq_; }
    uint64_t            getId() const { return id_; }
    uint32_t            getSize() const { return size_; }
    uint64_t            getAddr() const { return addr_; }
    uint64_t            getData() const { return data_; }
    uint32_t            getCoreId() const { return cid_; }
    uint32_t            getThrdId() const { return tid_; }
    uint8_t             getVbyte() const { return vbyte_; }
    uint8_t             getSizeV() const { return vbyte_; }
    bool                isValid() const { return valid_; }
    bool                isLinkValid() const { return vlink_; }
    bool                isExecuted() const { return executed_; }
    bool                isDataValid() const { return (state_ != LS_NEW); }
    bool                isIssued() const { return (state_ != LS_NEW && state_ != LS_TDATA &&
                                                   state_ != LS_RDATA); }
    bool                isSwitchData() const { return switchData_; }
    bool                isRMOstore() const { return ((itype_ == ITYPE_BLOCK_STORE) ||
                                                     (itype_ == ITYPE_STORE_INIT));  }
    bool                isIO() const { return ((addr_ & IO_ADDR_BIT_MASK) == 0 ? false : true); }
  protected:

  private:
    std::list<MemoryAccessEntry>::iterator link_;
    enum INSTR_TYPE     itype_;
    /* For all stores in N1, and normal stores in N2, the state diagram is as follows:

                          SC          SA        SU
       LS_NEW -> LS_TDATA -> LS_ISSUE -> LS_ACK -> LS_UPDATE
             |       ^                            |
             |       |                            +-> LS_INV
             +-> LS_RDATA

       For RMO Store in N2, the state diagram is as follows:


                          SC
       LS_NEW -> LS_TDATA -> LS_ISSUE -> LS_INV
             |       ^
             |       |
             +-> LS_RDATA


       For Load Buffer, the state diagram is simply as

       LS_NEW

       For Fetch Buffer, the state diagram is as follows:
       LS_NEW -> LS_RDATA -> LS_ACK

    */
    enum LS_ENTRY_STATE state_;
    enum DATA_SRC       dsrc_;     // load data source
    uint64_t            iseq_;     // load store instruction sequence
    uint64_t            id_;
    uint64_t            addr_;
    uint64_t            data_;
    uint32_t            size_;
    uint32_t            tid_;     // tid_ & cid_ are for identification, good for debug
    uint32_t            cid_;
    uint8_t             vbyte_;
    bool                valid_;
    bool                vlink_;
    bool                executed_;
    /* Atomic instruction consists of two parts: load and store. However, for CAS
       instruction, if the comparison is a false, then the value of the addressed
       memory is not changed. In this case, Riesling won't send a store transaction
       to the memory, thus no store side callback. The switchData_ indicates
       if the memory data will be changed for an atomic instruction. It is a false
       only if the atomic instruction is a CAS and its comparsion results in a false.
    */
    bool                switchData_;
    /* The following two parameters are introduced primarily for the memory sync model
       to work in Niagara 1 swerver-memory.cc environment. In that environment,
       although the data source is known at MEM_ISSUE stage, the store buffer
       data is not availabe at this moment. Hence, if a load with STB as data
       source, there is no way to get data. To simplify the code needed to
       modify in swerver-memory.cc, a link to the MemoryAccessEntry is provided
       so that when the store buffer entry data is ready, the data can be forwarded
       to the corresponding LoadData Entry in MAB.
    */
    std::list<MemoryAccessEntry>::iterator link2_;
    bool                vlink2_;

    /* The following parameter is introduced for working in Niagara 1 swerver-memory.cc
       environment. In that environment, store data is set at PCX_L2 stage. This field
       is needed to indicates which entry has a valid data already. Checking address
       is not reliable since there may be entry with same addresses. Updating the latest
       one is also not ok since there may be two issues before PCX_L2 signal is sent.
       N2 environment should not have this problem since data is supposed to come with
       the issue command.
    */
    //    bool                vdata_;

  };

#endif /* _LOADSTOREENTRY_H */