Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / cpu / bin / SS_StateCtr.py

# ========== Copyright Header Begin ==========================================
# 
# OpenSPARC T2 Processor File: SS_StateCtr.py
# Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
# 
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
# 
# The above named program is distributed in the hope that it will be 
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# General Public License for more details.
# 
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
# 
# ========== Copyright Header End ============================================

import sys

from SS_State import *
from SS_Setup import *

setup = setups[sys.argv[1]]

import SS_StateAsr
import SS_StatePrf
import SS_StateHrf
import SS_StateSrf

ctr_regs=[]
ctr_regs.extend(SS_StateAsr.ctr_regs)
ctr_regs.extend(SS_StatePrf.ctr_regs)
ctr_regs.extend(SS_StateHrf.ctr_regs)
ctr_regs.extend(SS_StateSrf.ctr_regs)

asi_regs=[
 SS_AsiCtrReg('SS','lsu_ctr',PRIVATE,
 [             
   ('ic'       , 0, 0,RW,0),
   ('dc'       , 1, 1,RW,0),
   ('im'       , 2, 2,RW,0),
   ('dm'       , 3, 3,RW,0),
   ('pw'       ,19,19,RW,0),
   ('pr'       ,20,20,RW,0),
   ('vw'       ,21,21,RW,0),
   ('vr'       ,22,22,RW,0),
   ('vm'       ,25,32,RW,0),
   ('pm'       ,33,40,RW,0),
   ('mode'     ,33,34,RW,0)
 ])
, SS_CtrReg('SS','tsb_tte_tag',0,0,0,64,
 [     
   ('va'       , 0,41,RW,0),   # va bits 63:22 actually
   ('context'  ,48,63,RW,0)
 ]) 
, SS_CtrReg('SS','tsb_tte_data',0,0,0,64,
 [     
   ('size'     , 0, 3,RW,0),   # note 4 bits 
   ('soft'     , 4, 5,RW,0),
   ('w'        , 6, 6,RW,0),
   ('x'        , 7, 7,RW,0),
   ('p'        , 8, 8,RW,0),
   ('cv'       , 9, 9,RW,0),
   ('cp'       ,10,10,RW,0),
   ('e'        ,11,11,RW,0),
   ('ie'       ,12,12,RW,0),
   ('pa'       ,13,55,RW,0),   # note 56 bits of PA ... 
   ('soft2'    ,56,61,RW,0),
   ('nfo'      ,62,62,RW,0),
   ('v'        ,63,63,RW,0)
 ])
]

ctr_regs.extend(asi_regs)

h_file=open('%s' % sys.argv[2],'w')

h_base_name = sys.argv[2].split('/')[-1].split('.')[0]

h_file.write('#ifndef __'+h_base_name+'_h__\n')
h_file.write('#define __'+h_base_name+'_h__\n')
h_file.write('\n')
h_file.write('#include "SS_AsiCtrReg.h"\n')
h_file.write('#include "SS_SnapShot.h"\n')
h_file.write('\n')

for reg in ctr_regs:
 reg.cpp(h_file)

h_file.write('\n')
h_file.write('#endif\n')
h_file.write('\n')

h_file.close()