/* Generated automatically by the program `genoutput'
from the machine description file `md'. */
#include "hard-reg-set.h"
output_0 (operands
, insn
)
return AS2 (test
%L0
,%0,%0);
operands
[1] = const0_rtx
;
return AS2 (cmp
%L0
,%1,%0);
output_2 (operands
, insn
)
return AS2 (test
%W0
,%0,%0);
operands
[1] = const0_rtx
;
return AS2 (cmp
%W0
,%1,%0);
output_4 (operands
, insn
)
return AS2 (test
%B0
,%0,%0);
operands
[1] = const0_rtx
;
return AS2 (cmp
%B0
,%1,%0);
output_6 (operands
, insn
)
if (! STACK_TOP_P (operands
[0]))
output_asm_insn ("ftst", operands
);
if (find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
))
output_asm_insn (AS1 (fstp
,%y0
), operands
);
return (char *) output_fp_cc0_set (insn
);
output_8 (operands
, insn
)
if (! STACK_TOP_P (operands
[0]))
output_asm_insn ("ftst", operands
);
if (find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
))
output_asm_insn (AS1 (fstp
,%y0
), operands
);
return (char *) output_fp_cc0_set (insn
);
output_10 (operands
, insn
)
if (CONSTANT_P (operands
[0]) || GET_CODE (operands
[1]) == MEM
)
cc_status
.flags
|= CC_REVERSED
;
return AS2 (cmp
%L0
,%0,%1);
return AS2 (cmp
%L0
,%1,%0);
output_12 (operands
, insn
)
if (CONSTANT_P (operands
[0]) || GET_CODE (operands
[1]) == MEM
)
cc_status
.flags
|= CC_REVERSED
;
return AS2 (cmp
%W0
,%0,%1);
return AS2 (cmp
%W0
,%1,%0);
output_14 (operands
, insn
)
if (CONSTANT_P (operands
[0]) || GET_CODE (operands
[1]) == MEM
)
cc_status
.flags
|= CC_REVERSED
;
return AS2 (cmp
%B0
,%0,%1);
return AS2 (cmp
%B0
,%1,%0);
output_16 (operands
, insn
)
return (char *) output_float_compare (insn
, operands
);
output_17 (operands
, insn
)
return (char *) output_float_compare (insn
, operands
);
output_18 (operands
, insn
)
return (char *) output_float_compare (insn
, operands
);
output_19 (operands
, insn
)
return (char *) output_float_compare (insn
, operands
);
output_20 (operands
, insn
)
return (char *) output_float_compare (insn
, operands
);
output_21 (operands
, insn
)
return (char *) output_float_compare (insn
, operands
);
output_22 (operands
, insn
)
return (char *) output_float_compare (insn
, operands
);
output_23 (operands
, insn
)
return (char *) output_float_compare (insn
, operands
);
output_24 (operands
, insn
)
return (char *) output_float_compare (insn
, operands
);
output_25 (operands
, insn
)
return (char *) output_float_compare (insn
, operands
);
output_32 (operands
, insn
)
/* For small integers, we may actually use testb. */
if (GET_CODE (operands
[1]) == CONST_INT
&& ! (GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))
&& (! REG_P (operands
[0]) || QI_REG_P (operands
[0])))
/* We may set the sign bit spuriously. */
if ((INTVAL (operands
[1]) & ~0xff) == 0)
cc_status
.flags
|= CC_NOT_NEGATIVE
;
return AS2 (test
%B0
,%1,%b0
);
if ((INTVAL (operands
[1]) & ~0xff00) == 0)
cc_status
.flags
|= CC_NOT_NEGATIVE
;
operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 8);
if (QI_REG_P (operands
[0]))
return AS2 (test
%B0
,%1,%h0
);
operands
[0] = adj_offsettable_operand (operands
[0], 1);
return AS2 (test
%B0
,%1,%b0
);
if (GET_CODE (operands
[0]) == MEM
&& (INTVAL (operands
[1]) & ~0xff0000) == 0)
cc_status
.flags
|= CC_NOT_NEGATIVE
;
operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 16);
operands
[0] = adj_offsettable_operand (operands
[0], 2);
return AS2 (test
%B0
,%1,%b0
);
if (GET_CODE (operands
[0]) == MEM
&& (INTVAL (operands
[1]) & ~0xff000000) == 0)
operands
[1] = GEN_INT ((INTVAL (operands
[1]) >> 24) & 0xff);
operands
[0] = adj_offsettable_operand (operands
[0], 3);
return AS2 (test
%B0
,%1,%b0
);
if (CONSTANT_P (operands
[1]) || GET_CODE (operands
[0]) == MEM
)
return AS2 (test
%L0
,%1,%0);
return AS2 (test
%L1
,%0,%1);
output_33 (operands
, insn
)
if (GET_CODE (operands
[1]) == CONST_INT
&& ! (GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))
&& (! REG_P (operands
[0]) || QI_REG_P (operands
[0])))
if ((INTVAL (operands
[1]) & 0xff00) == 0)
/* ??? This might not be necessary. */
if (INTVAL (operands
[1]) & 0xffff0000)
operands
[1] = GEN_INT (INTVAL (operands
[1]) & 0xff);
/* We may set the sign bit spuriously. */
cc_status
.flags
|= CC_NOT_NEGATIVE
;
return AS2 (test
%B0
,%1,%b0
);
if ((INTVAL (operands
[1]) & 0xff) == 0)
operands
[1] = GEN_INT ((INTVAL (operands
[1]) >> 8) & 0xff);
if (QI_REG_P (operands
[0]))
return AS2 (test
%B0
,%1,%h0
);
operands
[0] = adj_offsettable_operand (operands
[0], 1);
return AS2 (test
%B0
,%1,%b0
);
if (CONSTANT_P (operands
[1]) || GET_CODE (operands
[0]) == MEM
)
return AS2 (test
%W0
,%1,%0);
return AS2 (test
%W1
,%0,%1);
output_34 (operands
, insn
)
if (CONSTANT_P (operands
[1]) || GET_CODE (operands
[0]) == MEM
)
return AS2 (test
%B0
,%1,%0);
return AS2 (test
%B1
,%0,%1);
output_38 (operands
, insn
)
if (operands
[1] == const0_rtx
&& REG_P (operands
[0]))
return AS2 (xor%L0
,%0,%0);
if (operands
[1] == const1_rtx
&& (link
= find_reg_note (insn
, REG_WAS_0
, 0))
/* Make sure the insn that stored the 0 is still present. */
&& ! INSN_DELETED_P (XEXP (link
, 0))
&& GET_CODE (XEXP (link
, 0)) != NOTE
/* Make sure cross jumping didn't happen here. */
&& no_labels_between_p (XEXP (link
, 0), insn
)
/* Make sure the reg hasn't been clobbered. */
&& ! reg_set_between_p (operands
[0], XEXP (link
, 0), insn
))
/* Fastest way to change a 0 to a 1. */
return AS2 (mov
%L0
,%1,%0);
output_40 (operands
, insn
)
if (REG_P (operands
[0]) && operands
[1] == const0_rtx
)
return AS2 (xor%L0
,%k0
,%k0
);
if (REG_P (operands
[0]) && operands
[1] == const1_rtx
&& (link
= find_reg_note (insn
, REG_WAS_0
, 0))
/* Make sure the insn that stored the 0 is still present. */
&& ! INSN_DELETED_P (XEXP (link
, 0))
&& GET_CODE (XEXP (link
, 0)) != NOTE
/* Make sure cross jumping didn't happen here. */
&& no_labels_between_p (XEXP (link
, 0), insn
)
/* Make sure the reg hasn't been clobbered. */
&& ! reg_set_between_p (operands
[0], XEXP (link
, 0), insn
))
/* Fastest way to change a 0 to a 1. */
return AS2 (mov
%L0
,%k1
,%k0
);
else if (CONSTANT_P (operands
[1]))
return AS2 (mov
%L0
,%1,%k0
);
return AS2 (mov
%W0
,%1,%0);
output_41 (operands
, insn
)
if (operands
[1] == const0_rtx
&& REG_P (operands
[0]))
return AS2 (xor%W0
,%0,%0);
if (operands
[1] == const1_rtx
&& (link
= find_reg_note (insn
, REG_WAS_0
, 0))
/* Make sure the insn that stored the 0 is still present. */
&& ! INSN_DELETED_P (XEXP (link
, 0))
&& GET_CODE (XEXP (link
, 0)) != NOTE
/* Make sure cross jumping didn't happen here. */
&& no_labels_between_p (XEXP (link
, 0), insn
)
/* Make sure the reg hasn't been clobbered. */
&& ! reg_set_between_p (operands
[0], XEXP (link
, 0), insn
))
/* Fastest way to change a 0 to a 1. */
return AS2 (mov
%W0
,%1,%0);
output_42 (operands
, insn
)
operands
[1] = gen_rtx (REG
, HImode
, REGNO (operands
[1]));
output_43 (operands
, insn
)
if (operands
[1] == const0_rtx
&& REG_P (operands
[0]))
return AS2 (xor%B0
,%0,%0);
if (operands
[1] == const1_rtx
&& (link
= find_reg_note (insn
, REG_WAS_0
, 0))
/* Make sure the insn that stored the 0 is still present. */
&& ! INSN_DELETED_P (XEXP (link
, 0))
&& GET_CODE (XEXP (link
, 0)) != NOTE
/* Make sure cross jumping didn't happen here. */
&& no_labels_between_p (XEXP (link
, 0), insn
)
/* Make sure the reg hasn't been clobbered. */
&& ! reg_set_between_p (operands
[0], XEXP (link
, 0), insn
))
/* Fastest way to change a 0 to a 1. */
/* If mov%B0 isn't allowed for one of these regs, use mov%L0. */
if (NON_QI_REG_P (operands
[0]) || NON_QI_REG_P (operands
[1]))
return (AS2 (mov
%L0
,%k1
,%k0
));
return (AS2 (mov
%B0
,%1,%0));
output_44 (operands
, insn
)
if (operands
[1] == const0_rtx
&& REG_P (operands
[0]))
return AS2 (xor%B0
,%0,%0);
if (operands
[1] == const1_rtx
&& (link
= find_reg_note (insn
, REG_WAS_0
, 0))
/* Make sure the insn that stored the 0 is still present. */
&& ! INSN_DELETED_P (XEXP (link
, 0))
&& GET_CODE (XEXP (link
, 0)) != NOTE
/* Make sure cross jumping didn't happen here. */
&& no_labels_between_p (XEXP (link
, 0), insn
)
/* Make sure the reg hasn't been clobbered. */
&& ! reg_set_between_p (operands
[0], XEXP (link
, 0), insn
))
/* Fastest way to change a 0 to a 1. */
/* If mov%B0 isn't allowed for one of these regs, use mov%W0. */
if (NON_QI_REG_P (operands
[0]) || NON_QI_REG_P (operands
[1]))
return (AS2 (mov
%L0
,%k1
,%k0
));
return AS2 (mov
%B0
,%1,%0);
output_45 (operands
, insn
)
if (STACK_REG_P (operands
[1]))
if (! STACK_TOP_P (operands
[1]))
xops
[0] = AT_SP (SFmode
);
xops
[2] = stack_pointer_rtx
;
output_asm_insn (AS2 (sub
%L2
,%1,%2), xops
);
if (find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
))
output_asm_insn (AS1 (fstp
%S0
,%0), xops
);
output_asm_insn (AS1 (fst
%S0
,%0), xops
);
output_46 (operands
, insn
)
int stack_top_dies
= find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
) != 0;
/* First handle a `pop' insn or a `fld %st(0)' */
if (STACK_TOP_P (operands
[0]) && STACK_TOP_P (operands
[1]))
/* Handle a transfer between the 387 and a 386 register */
if (STACK_TOP_P (operands
[0]) && NON_STACK_REG_P (operands
[1]))
output_op_from_reg (operands
[1], AS1 (fld
%z0
,%y1
));
if (STACK_TOP_P (operands
[1]) && NON_STACK_REG_P (operands
[0]))
output_to_reg (operands
[0], stack_top_dies
);
/* Handle other kinds of writes from the 387 */
if (STACK_TOP_P (operands
[1]))
return AS1 (fstp
%z0
,%y0
);
/* Handle other kinds of reads to the 387 */
if (STACK_TOP_P (operands
[0]) && GET_CODE (operands
[1]) == CONST_DOUBLE
)
return (char *) output_move_const_single (operands
);
if (STACK_TOP_P (operands
[0]))
/* Handle all SFmode moves not involving the 387 */
return (char *) singlemove_string (operands
);
output_47 (operands
, insn
)
if (STACK_REG_P (operands
[1]))
xops
[0] = AT_SP (SFmode
);
xops
[2] = stack_pointer_rtx
;
output_asm_insn (AS2 (sub
%L2
,%1,%2), xops
);
if (find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
))
output_asm_insn (AS1 (fstp
%Q0
,%0), xops
);
output_asm_insn (AS1 (fst
%Q0
,%0), xops
);
return (char *) output_move_double (operands
);
output_48 (operands
, insn
)
if (STACK_TOP_P (operands
[0]))
output_49 (operands
, insn
)
int stack_top_dies
= find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
) != 0;
/* First handle a `pop' insn or a `fld %st(0)' */
if (STACK_TOP_P (operands
[0]) && STACK_TOP_P (operands
[1]))
/* Handle a transfer between the 387 and a 386 register */
if (STACK_TOP_P (operands
[0]) && NON_STACK_REG_P (operands
[1]))
output_op_from_reg (operands
[1], AS1 (fld
%z0
,%y1
));
if (STACK_TOP_P (operands
[1]) && NON_STACK_REG_P (operands
[0]))
output_to_reg (operands
[0], stack_top_dies
);
/* Handle other kinds of writes from the 387 */
if (STACK_TOP_P (operands
[1]))
return AS1 (fstp
%z0
,%y0
);
/* Handle other kinds of reads to the 387 */
if (STACK_TOP_P (operands
[0]) && GET_CODE (operands
[1]) == CONST_DOUBLE
)
return (char *) output_move_const_single (operands
);
if (STACK_TOP_P (operands
[0]))
/* Handle all DFmode moves not involving the 387 */
return (char *) output_move_double (operands
);
output_50 (operands
, insn
)
return (char *) output_move_double (operands
);
output_51 (operands
, insn
)
return (char *) output_move_double (operands
);
output_52 (operands
, insn
)
if ((TARGET_486
|| REGNO (operands
[0]) == 0)
&& REG_P (operands
[1]) && REGNO (operands
[0]) == REGNO (operands
[1]))
xops
[1] = GEN_INT (0xffff);
output_asm_insn (AS2 (and%L0
,%1,%k0
), xops
);
return AS2 (movzx
,%1,%0);
return AS2 (movz
%W0
%L0
,%1,%0);
output_53 (operands
, insn
)
if ((TARGET_486
|| REGNO (operands
[0]) == 0)
&& REG_P (operands
[1]) && REGNO (operands
[0]) == REGNO (operands
[1]))
xops
[1] = GEN_INT (0xff);
output_asm_insn (AS2 (and%L0
,%1,%k0
), xops
);
return AS2 (movzx
,%1,%0);
return AS2 (movz
%B0
%W0
,%1,%0);
output_54 (operands
, insn
)
if ((TARGET_486
|| REGNO (operands
[0]) == 0)
&& REG_P (operands
[1]) && REGNO (operands
[0]) == REGNO (operands
[1]))
xops
[1] = GEN_INT (0xff);
output_asm_insn (AS2 (and%L0
,%1,%k0
), xops
);
return AS2 (movzx
,%1,%0);
return AS2 (movz
%B0
%L0
,%1,%0);
output_55 (operands
, insn
)
operands
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
return AS2 (xor%L0
,%0,%0);
output_56 (operands
, insn
)
if (REGNO (operands
[0]) == 0)
/* This used to be cwtl, but that extends HI to SI somehow. */
operands
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
output_asm_insn (AS2 (mov
%L0
,%0,%1), operands
);
operands
[0] = GEN_INT (31);
return AS2 (sar
%L1
,%0,%1);
output_57 (operands
, insn
)
if (REGNO (operands
[0]) == 0
&& REG_P (operands
[1]) && REGNO (operands
[1]) == 0)
return AS2 (movsx
,%1,%0);
return AS2 (movs
%W0
%L0
,%1,%0);
output_58 (operands
, insn
)
if (REGNO (operands
[0]) == 0
&& REG_P (operands
[1]) && REGNO (operands
[1]) == 0)
return AS2 (movsx
,%1,%0);
return AS2 (movs
%B0
%W0
,%1,%0);
output_59 (operands
, insn
)
return AS2 (movsx
,%1,%0);
return AS2 (movs
%B0
%L0
,%1,%0);
output_60 (operands
, insn
)
int stack_top_dies
= find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
) != 0;
if (NON_STACK_REG_P (operands
[1]))
output_op_from_reg (operands
[1], AS1 (fld
%z0
,%y1
));
if (NON_STACK_REG_P (operands
[0]))
output_to_reg (operands
[0], stack_top_dies
);
if (STACK_TOP_P (operands
[0]))
if (GET_CODE (operands
[0]) == MEM
)
return AS1 (fstp
%z0
,%y0
);
output_62 (operands
, insn
)
int stack_top_dies
= find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
) != 0;
if (GET_CODE (operands
[0]) == MEM
)
else if (STACK_TOP_P (operands
[0]))
output_asm_insn (AS1 (fstp
%z2
,%y2
), operands
);
output_67 (operands
, insn
)
return (char *) output_fix_trunc (insn
, operands
);
output_68 (operands
, insn
)
return (char *) output_fix_trunc (insn
, operands
);
output_71 (operands
, insn
)
return (char *) output_fix_trunc (insn
, operands
);
output_72 (operands
, insn
)
return (char *) output_fix_trunc (insn
, operands
);
output_77 (operands
, insn
)
if (NON_STACK_REG_P (operands
[1]))
output_op_from_reg (operands
[1], AS1 (fild
%z0
,%1));
else if (GET_CODE (operands
[1]) == MEM
)
output_78 (operands
, insn
)
if (NON_STACK_REG_P (operands
[1]))
output_op_from_reg (operands
[1], AS1 (fild
%z0
,%1));
else if (GET_CODE (operands
[1]) == MEM
)
output_79 (operands
, insn
)
if (NON_STACK_REG_P (operands
[1]))
output_op_from_reg (operands
[1], AS1 (fild
%z0
,%1));
else if (GET_CODE (operands
[1]) == MEM
)
output_80 (operands
, insn
)
if (NON_STACK_REG_P (operands
[1]))
output_op_from_reg (operands
[1], AS1 (fild
%z0
,%1));
else if (GET_CODE (operands
[1]) == MEM
)
output_81 (operands
, insn
)
split_di (operands
, 3, low
, high
);
if (GET_CODE (low
[2]) != CONST_INT
|| INTVAL (low
[2]) != 0)
output_asm_insn (AS2 (add
%L0
,%2,%0), low
);
output_asm_insn (AS2 (adc
%L0
,%2,%0), high
);
output_asm_insn (AS2 (add
%L0
,%2,%0), high
);
output_82 (operands
, insn
)
if (REG_P (operands
[0]) && REGNO (operands
[0]) != REGNO (operands
[1]))
if (REG_P (operands
[2]) && REGNO (operands
[0]) == REGNO (operands
[2]))
return AS2 (add
%L0
,%1,%0);
if (! TARGET_486
|| ! REG_P (operands
[2]))
if (operands
[2] == stack_pointer_rtx
)
operands
[1] = operands
[2];
if (operands
[2] != stack_pointer_rtx
)
operands
[1] = SET_SRC (PATTERN (insn
));
return AS2 (lea
%L0
,%a1
,%0);
output_asm_insn (AS2 (mov
%L0
,%1,%0), operands
);
if (operands
[2] == const1_rtx
)
if (operands
[2] == constm1_rtx
)
return AS2 (add
%L0
,%2,%0);
output_83 (operands
, insn
)
if (operands
[2] == const1_rtx
)
if (operands
[2] == constm1_rtx
)
return AS2 (add
%W0
,%2,%0);
output_84 (operands
, insn
)
if (operands
[2] == const1_rtx
)
if (operands
[2] == constm1_rtx
)
return AS2 (add
%B0
,%2,%0);
output_85 (operands
, insn
)
/* Adding a constant to a register is faster with an add. */
/* ??? can this ever happen? */
if (GET_CODE (operands
[1]) == PLUS
&& GET_CODE (XEXP (operands
[1], 1)) == CONST_INT
&& rtx_equal_p (operands
[0], XEXP (operands
[1], 0)))
operands
[1] = XEXP (operands
[1], 1);
if (operands
[1] == const1_rtx
)
if (operands
[1] == constm1_rtx
)
return AS2 (add
%L0
,%1,%0);
return AS2 (lea
%L0
,%a1
,%0);
output_88 (operands
, insn
)
split_di (operands
, 3, low
, high
);
if (GET_CODE (low
[2]) != CONST_INT
|| INTVAL (low
[2]) != 0)
output_asm_insn (AS2 (sub
%L0
,%2,%0), low
);
output_asm_insn (AS2 (sbb
%L0
,%2,%0), high
);
output_asm_insn (AS2 (sub
%L0
,%2,%0), high
);
output_89 (operands
, insn
)
return AS2 (sub
%L0
,%2,%0);
output_90 (operands
, insn
)
return AS2 (sub
%W0
,%2,%0);
output_91 (operands
, insn
)
return AS2 (sub
%B0
,%2,%0);
output_94 (operands
, insn
)
return AS2 (imul
%W0
,%2,%0);
output_95 (operands
, insn
)
if (GET_CODE (operands
[1]) == REG
&& REGNO (operands
[1]) == REGNO (operands
[0])
&& (GET_CODE (operands
[2]) == MEM
|| GET_CODE (operands
[2]) == REG
))
/* Assembler has weird restrictions. */
return AS2 (imul
%W0
,%2,%0);
return AS3 (imul
%W0
,%2,%1,%0);
output_96 (operands
, insn
)
return AS2 (imul
%L0
,%2,%0);
output_97 (operands
, insn
)
if (GET_CODE (operands
[1]) == REG
&& REGNO (operands
[1]) == REGNO (operands
[0])
&& (GET_CODE (operands
[2]) == MEM
|| GET_CODE (operands
[2]) == REG
))
/* Assembler has weird restrictions. */
return AS2 (imul
%L0
,%2,%0);
return AS3 (imul
%L0
,%2,%1,%0);
output_105 (operands
, insn
)
output_asm_insn ("cdq", operands
);
output_asm_insn ("cltd", operands
);
output_107 (operands
, insn
)
output_asm_insn (AS2 (xor%L3
,%3,%3), operands
);
output_108 (operands
, insn
)
output_asm_insn (AS2 (xor%W0
,%3,%3), operands
);
output_109 (operands
, insn
)
if (GET_CODE (operands
[2]) == CONST_INT
&& ! (GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0])))
if (INTVAL (operands
[2]) == 0xffff && REG_P (operands
[0])
&& (! REG_P (operands
[1])
|| REGNO (operands
[0]) != 0 || REGNO (operands
[1]) != 0)
&& (! TARGET_486
|| ! rtx_equal_p (operands
[0], operands
[1])))
/* ??? tege: Should forget CC_STATUS only if we clobber a
remembered operand. Fix that later. */
return AS2 (movzx
,%w1
,%0);
return AS2 (movz
%W0
%L0
,%w1
,%0);
if (INTVAL (operands
[2]) == 0xff && REG_P (operands
[0])
&& !(REG_P (operands
[1]) && NON_QI_REG_P (operands
[1]))
&& (! REG_P (operands
[1])
|| REGNO (operands
[0]) != 0 || REGNO (operands
[1]) != 0)
&& (! TARGET_486
|| ! rtx_equal_p (operands
[0], operands
[1])))
/* ??? tege: Should forget CC_STATUS only if we clobber a
remembered operand. Fix that later. */
return AS2 (movzx
,%b1
,%0);
return AS2 (movz
%B0
%L0
,%b1
,%0);
if (QI_REG_P (operands
[0]) && ~(INTVAL (operands
[2]) | 0xff) == 0)
if (INTVAL (operands
[2]) == 0xffffff00)
operands
[2] = const0_rtx
;
return AS2 (mov
%B0
,%2,%b0
);
operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xff);
return AS2 (and%B0
,%2,%b0
);
if (QI_REG_P (operands
[0]) && ~(INTVAL (operands
[2]) | 0xff00) == 0)
if (INTVAL (operands
[2]) == 0xffff00ff)
operands
[2] = const0_rtx
;
return AS2 (mov
%B0
,%2,%h0
);
operands
[2] = GEN_INT ((INTVAL (operands
[2]) >> 8) & 0xff);
return AS2 (and%B0
,%2,%h0
);
if (GET_CODE (operands
[0]) == MEM
&& INTVAL (operands
[2]) == 0xffff0000)
operands
[2] = const0_rtx
;
return AS2 (mov
%W0
,%2,%w0
);
return AS2 (and%L0
,%2,%0);
output_110 (operands
, insn
)
if (GET_CODE (operands
[2]) == CONST_INT
&& ! (GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0])))
/* Can we ignore the upper byte? */
if ((! REG_P (operands
[0]) || QI_REG_P (operands
[0]))
&& (INTVAL (operands
[2]) & 0xff00) == 0xff00)
if ((INTVAL (operands
[2]) & 0xff) == 0)
operands
[2] = const0_rtx
;
return AS2 (mov
%B0
,%2,%b0
);
operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xff);
return AS2 (and%B0
,%2,%b0
);
/* Can we ignore the lower byte? */
/* ??? what about offsettable memory references? */
if (QI_REG_P (operands
[0]) && (INTVAL (operands
[2]) & 0xff) == 0xff)
if ((INTVAL (operands
[2]) & 0xff00) == 0)
operands
[2] = const0_rtx
;
return AS2 (mov
%B0
,%2,%h0
);
operands
[2] = GEN_INT ((INTVAL (operands
[2]) >> 8) & 0xff);
return AS2 (and%B0
,%2,%h0
);
return AS2 (and%W0
,%2,%0);
output_111 (operands
, insn
)
return AS2 (and%B0
,%2,%0);
output_112 (operands
, insn
)
if (GET_CODE (operands
[2]) == CONST_INT
&& ! (GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0])))
if ((! REG_P (operands
[0]) || QI_REG_P (operands
[0]))
&& (INTVAL (operands
[2]) & ~0xff) == 0)
if (INTVAL (operands
[2]) == 0xff)
return AS2 (mov
%B0
,%2,%b0
);
return AS2 (or%B0
,%2,%b0
);
if (QI_REG_P (operands
[0]) && (INTVAL (operands
[2]) & ~0xff00) == 0)
operands
[2] = GEN_INT (INTVAL (operands
[2]) >> 8);
if (INTVAL (operands
[2]) == 0xff)
return AS2 (mov
%B0
,%2,%h0
);
return AS2 (or%B0
,%2,%h0
);
return AS2 (or%L0
,%2,%0);
output_113 (operands
, insn
)
if (GET_CODE (operands
[2]) == CONST_INT
&& ! (GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0])))
/* Can we ignore the upper byte? */
if ((! REG_P (operands
[0]) || QI_REG_P (operands
[0]))
&& (INTVAL (operands
[2]) & 0xff00) == 0)
if (INTVAL (operands
[2]) & 0xffff0000)
operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
if (INTVAL (operands
[2]) == 0xff)
return AS2 (mov
%B0
,%2,%b0
);
return AS2 (or%B0
,%2,%b0
);
/* Can we ignore the lower byte? */
/* ??? what about offsettable memory references? */
if (QI_REG_P (operands
[0])
&& (INTVAL (operands
[2]) & 0xff) == 0)
operands
[2] = GEN_INT ((INTVAL (operands
[2]) >> 8) & 0xff);
if (INTVAL (operands
[2]) == 0xff)
return AS2 (mov
%B0
,%2,%h0
);
return AS2 (or%B0
,%2,%h0
);
return AS2 (or%W0
,%2,%0);
output_114 (operands
, insn
)
return AS2 (or%B0
,%2,%0);
output_115 (operands
, insn
)
if (GET_CODE (operands
[2]) == CONST_INT
&& ! (GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0])))
if ((! REG_P (operands
[0]) || QI_REG_P (operands
[0]))
&& (INTVAL (operands
[2]) & ~0xff) == 0)
if (INTVAL (operands
[2]) == 0xff)
return AS2 (xor%B0
,%2,%b0
);
if (QI_REG_P (operands
[0]) && (INTVAL (operands
[2]) & ~0xff00) == 0)
operands
[2] = GEN_INT (INTVAL (operands
[2]) >> 8);
if (INTVAL (operands
[2]) == 0xff)
return AS2 (xor%B0
,%2,%h0
);
return AS2 (xor%L0
,%2,%0);
output_116 (operands
, insn
)
if (GET_CODE (operands
[2]) == CONST_INT
&& ! (GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0])))
/* Can we ignore the upper byte? */
if ((! REG_P (operands
[0]) || QI_REG_P (operands
[0]))
&& (INTVAL (operands
[2]) & 0xff00) == 0)
if (INTVAL (operands
[2]) & 0xffff0000)
operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
if (INTVAL (operands
[2]) == 0xff)
return AS2 (xor%B0
,%2,%b0
);
/* Can we ignore the lower byte? */
/* ??? what about offsettable memory references? */
if (QI_REG_P (operands
[0])
&& (INTVAL (operands
[2]) & 0xff) == 0)
operands
[2] = GEN_INT ((INTVAL (operands
[2]) >> 8) & 0xff);
if (INTVAL (operands
[2]) == 0xff)
return AS2 (xor%B0
,%2,%h0
);
return AS2 (xor%W0
,%2,%0);
output_117 (operands
, insn
)
return AS2 (xor%B0
,%2,%0);
output_118 (operands
, insn
)
rtx xops
[2], low
[1], high
[1];
split_di (operands
, 1, low
, high
);
output_asm_insn (AS1 (neg
%L0
,%0), low
);
output_asm_insn (AS2 (adc
%L1
,%0,%1), xops
);
output_asm_insn (AS1 (neg
%L0
,%0), high
);
output_141 (operands
, insn
)
rtx xops
[4], low
[1], high
[1];
split_di (operands
, 1, low
, high
);
if (INTVAL (xops
[0]) > 31)
output_asm_insn (AS2 (mov
%L3
,%2,%3), xops
); /* Fast shift by 32 */
output_asm_insn (AS2 (xor%L2
,%2,%2), xops
);
if (INTVAL (xops
[0]) > 32)
xops
[0] = GEN_INT (INTVAL (xops
[0]) - 32);
output_asm_insn (AS2 (sal
%L3
,%0,%3), xops
); /* Remaining shift */
output_asm_insn (AS3 (shld
%L3
,%0,%2,%3), xops
);
output_asm_insn (AS2 (sal
%L2
,%0,%2), xops
);
output_142 (operands
, insn
)
rtx xops
[4], low
[1], high
[1];
split_di (operands
, 1, low
, high
);
output_asm_insn (AS2 (ror
%B0
,%1,%0), xops
); /* shift count / 2 */
output_asm_insn (AS3_SHIFT_DOUBLE (shld
%L3
,%0,%2,%3), xops
);
output_asm_insn (AS2 (sal
%L2
,%0,%2), xops
);
output_asm_insn (AS3_SHIFT_DOUBLE (shld
%L3
,%0,%2,%3), xops
);
output_asm_insn (AS2 (sal
%L2
,%0,%2), xops
);
xops
[1] = GEN_INT (7); /* shift count & 1 */
output_asm_insn (AS2 (shr
%B0
,%1,%0), xops
);
output_asm_insn (AS3_SHIFT_DOUBLE (shld
%L3
,%0,%2,%3), xops
);
output_asm_insn (AS2 (sal
%L2
,%0,%2), xops
);
output_143 (operands
, insn
)
if (REG_P (operands
[0]) && REGNO (operands
[0]) != REGNO (operands
[1]))
if (TARGET_486
&& INTVAL (operands
[2]) == 1)
output_asm_insn (AS2 (mov
%L0
,%1,%0), operands
);
return AS2 (add
%L0
,%1,%0);
if (operands
[1] == stack_pointer_rtx
)
output_asm_insn (AS2 (mov
%L0
,%1,%0), operands
);
operands
[1] = operands
[0];
operands
[1] = gen_rtx (MULT
, SImode
, operands
[1],
GEN_INT (1 << INTVAL (operands
[2])));
return AS2 (lea
%L0
,%a1
,%0);
return AS2 (sal
%L0
,%b2
,%0);
if (REG_P (operands
[0]) && operands
[2] == const1_rtx
)
return AS2 (add
%L0
,%0,%0);
return AS2 (sal
%L0
,%2,%0);
output_144 (operands
, insn
)
return AS2 (sal
%W0
,%b2
,%0);
if (REG_P (operands
[0]) && operands
[2] == const1_rtx
)
return AS2 (add
%W0
,%0,%0);
return AS2 (sal
%W0
,%2,%0);
output_145 (operands
, insn
)
return AS2 (sal
%B0
,%b2
,%0);
if (REG_P (operands
[0]) && operands
[2] == const1_rtx
)
return AS2 (add
%B0
,%0,%0);
return AS2 (sal
%B0
,%2,%0);
output_147 (operands
, insn
)
rtx xops
[4], low
[1], high
[1];
split_di (operands
, 1, low
, high
);
if (INTVAL (xops
[0]) > 31)
output_asm_insn (AS2 (mov
%L2
,%3,%2), xops
);
output_asm_insn (AS2 (sar
%L3
,%1,%3), xops
); /* shift by 32 */
if (INTVAL (xops
[0]) > 32)
xops
[0] = GEN_INT (INTVAL (xops
[0]) - 32);
output_asm_insn (AS2 (sar
%L2
,%0,%2), xops
); /* Remaining shift */
output_asm_insn (AS3 (shrd
%L2
,%0,%3,%2), xops
);
output_asm_insn (AS2 (sar
%L3
,%0,%3), xops
);
output_148 (operands
, insn
)
rtx xops
[4], low
[1], high
[1];
split_di (operands
, 1, low
, high
);
output_asm_insn (AS2 (ror
%B0
,%1,%0), xops
); /* shift count / 2 */
output_asm_insn (AS3_SHIFT_DOUBLE (shrd
%L2
,%0,%3,%2), xops
);
output_asm_insn (AS2 (sar
%L3
,%0,%3), xops
);
output_asm_insn (AS3_SHIFT_DOUBLE (shrd
%L2
,%0,%3,%2), xops
);
output_asm_insn (AS2 (sar
%L3
,%0,%3), xops
);
xops
[1] = GEN_INT (7); /* shift count & 1 */
output_asm_insn (AS2 (shr
%B0
,%1,%0), xops
);
output_asm_insn (AS3_SHIFT_DOUBLE (shrd
%L2
,%0,%3,%2), xops
);
output_asm_insn (AS2 (sar
%L3
,%0,%3), xops
);
output_149 (operands
, insn
)
return AS2 (sar
%L0
,%b2
,%0);
return AS2 (sar
%L0
,%2,%0);
output_150 (operands
, insn
)
return AS2 (sar
%W0
,%b2
,%0);
return AS2 (sar
%W0
,%2,%0);
output_151 (operands
, insn
)
return AS2 (sar
%B0
,%b2
,%0);
return AS2 (sar
%B0
,%2,%0);
output_153 (operands
, insn
)
rtx xops
[4], low
[1], high
[1];
split_di (operands
, 1, low
, high
);
if (INTVAL (xops
[0]) > 31)
output_asm_insn (AS2 (mov
%L2
,%3,%2), xops
); /* Fast shift by 32 */
output_asm_insn (AS2 (xor%L3
,%3,%3), xops
);
if (INTVAL (xops
[0]) > 32)
xops
[0] = GEN_INT (INTVAL (xops
[0]) - 32);
output_asm_insn (AS2 (shr
%L2
,%0,%2), xops
); /* Remaining shift */
output_asm_insn (AS3 (shrd
%L2
,%0,%3,%2), xops
);
output_asm_insn (AS2 (shr
%L3
,%0,%3), xops
);
output_154 (operands
, insn
)
rtx xops
[4], low
[1], high
[1];
split_di (operands
, 1, low
, high
);
output_asm_insn (AS2 (ror
%B0
,%1,%0), xops
); /* shift count / 2 */
output_asm_insn (AS3_SHIFT_DOUBLE (shrd
%L2
,%0,%3,%2), xops
);
output_asm_insn (AS2 (shr
%L3
,%0,%3), xops
);
output_asm_insn (AS3_SHIFT_DOUBLE (shrd
%L2
,%0,%3,%2), xops
);
output_asm_insn (AS2 (shr
%L3
,%0,%3), xops
);
xops
[1] = GEN_INT (7); /* shift count & 1 */
output_asm_insn (AS2 (shr
%B0
,%1,%0), xops
);
output_asm_insn (AS3_SHIFT_DOUBLE (shrd
%L2
,%0,%3,%2), xops
);
output_asm_insn (AS2 (shr
%L3
,%0,%3), xops
);
output_155 (operands
, insn
)
return AS2 (shr
%L0
,%b2
,%0);
return AS2 (shr
%L0
,%2,%1);
output_156 (operands
, insn
)
return AS2 (shr
%W0
,%b2
,%0);
return AS2 (shr
%W0
,%2,%0);
output_157 (operands
, insn
)
return AS2 (shr
%B0
,%b2
,%0);
return AS2 (shr
%B0
,%2,%0);
output_158 (operands
, insn
)
return AS2 (rol
%L0
,%b2
,%0);
return AS2 (rol
%L0
,%2,%0);
output_159 (operands
, insn
)
return AS2 (rol
%W0
,%b2
,%0);
return AS2 (rol
%W0
,%2,%0);
output_160 (operands
, insn
)
return AS2 (rol
%B0
,%b2
,%0);
return AS2 (rol
%B0
,%2,%0);
output_161 (operands
, insn
)
return AS2 (ror
%L0
,%b2
,%0);
return AS2 (ror
%L0
,%2,%0);
output_162 (operands
, insn
)
return AS2 (ror
%W0
,%b2
,%0);
return AS2 (ror
%W0
,%2,%0);
output_163 (operands
, insn
)
return AS2 (ror
%B0
,%b2
,%0);
return AS2 (ror
%B0
,%2,%0);
output_164 (operands
, insn
)
if (INTVAL (operands
[3]) == 1)
return AS2 (bts
%L0
,%2,%0);
return AS2 (btr
%L0
,%2,%0);
output_165 (operands
, insn
)
return AS2 (btc
%L0
,%1,%0);
output_166 (operands
, insn
)
return AS2 (btc
%L0
,%2,%0);
output_167 (operands
, insn
)
cc_status
.flags
|= CC_Z_IN_NOT_C
;
return AS2 (bt
%L0
,%1,%0);
output_168 (operands
, insn
)
mask
= ((1 << INTVAL (operands
[1])) - 1) << INTVAL (operands
[2]);
operands
[1] = GEN_INT (mask
);
if (QI_REG_P (operands
[0]))
cc_status
.flags
|= CC_NOT_NEGATIVE
;
return AS2 (test
%B0
,%1,%b0
);
if ((mask
& ~0xff00) == 0)
cc_status
.flags
|= CC_NOT_NEGATIVE
;
operands
[1] = GEN_INT (mask
>> 8);
return AS2 (test
%B0
,%1,%h0
);
return AS2 (test
%L0
,%1,%0);
output_169 (operands
, insn
)
mask
= ((1 << INTVAL (operands
[1])) - 1) << INTVAL (operands
[2]);
operands
[1] = GEN_INT (mask
);
if (! REG_P (operands
[0]) || QI_REG_P (operands
[0]))
cc_status
.flags
|= CC_NOT_NEGATIVE
;
return AS2 (test
%B0
,%1,%b0
);
if ((mask
& ~0xff00) == 0)
cc_status
.flags
|= CC_NOT_NEGATIVE
;
operands
[1] = GEN_INT (mask
>> 8);
if (QI_REG_P (operands
[0]))
return AS2 (test
%B0
,%1,%h0
);
operands
[0] = adj_offsettable_operand (operands
[0], 1);
return AS2 (test
%B0
,%1,%b0
);
if (GET_CODE (operands
[0]) == MEM
&& (mask
& ~0xff0000) == 0)
cc_status
.flags
|= CC_NOT_NEGATIVE
;
operands
[1] = GEN_INT (mask
>> 16);
operands
[0] = adj_offsettable_operand (operands
[0], 2);
return AS2 (test
%B0
,%1,%b0
);
if (GET_CODE (operands
[0]) == MEM
&& (mask
& ~0xff000000) == 0)
cc_status
.flags
|= CC_NOT_NEGATIVE
;
operands
[1] = GEN_INT (mask
>> 24);
operands
[0] = adj_offsettable_operand (operands
[0], 3);
return AS2 (test
%B0
,%1,%b0
);
if (CONSTANT_P (operands
[1]) || GET_CODE (operands
[0]) == MEM
)
return AS2 (test
%L0
,%1,%0);
return AS2 (test
%L1
,%0,%1);
output_171 (operands
, insn
)
if (cc_prev_status
.flags
& CC_Z_IN_NOT_C
)
output_173 (operands
, insn
)
if (cc_prev_status
.flags
& CC_Z_IN_NOT_C
)
output_175 (operands
, insn
)
if (TARGET_IEEE_FP
&& (cc_prev_status
.flags
& CC_IN_80387
))
OUTPUT_JUMP ("setg %0", "seta %0", NULL_PTR
);
output_177 (operands
, insn
)
output_179 (operands
, insn
)
if (TARGET_IEEE_FP
&& (cc_prev_status
.flags
& CC_IN_80387
))
OUTPUT_JUMP ("setl %0", "setb %0", "sets %0");
output_181 (operands
, insn
)
output_183 (operands
, insn
)
if (TARGET_IEEE_FP
&& (cc_prev_status
.flags
& CC_IN_80387
))
OUTPUT_JUMP ("setge %0", "setae %0", "setns %0");
output_185 (operands
, insn
)
output_187 (operands
, insn
)
if (TARGET_IEEE_FP
&& (cc_prev_status
.flags
& CC_IN_80387
))
OUTPUT_JUMP ("setle %0", "setbe %0", NULL_PTR
);
output_189 (operands
, insn
)
output_191 (operands
, insn
)
if (cc_prev_status
.flags
& CC_Z_IN_NOT_C
)
output_193 (operands
, insn
)
if (cc_prev_status
.flags
& CC_Z_IN_NOT_C
)
output_195 (operands
, insn
)
if (TARGET_IEEE_FP
&& (cc_prev_status
.flags
& CC_IN_80387
))
OUTPUT_JUMP ("jg %l0", "ja %l0", NULL_PTR
);
output_199 (operands
, insn
)
if (TARGET_IEEE_FP
&& (cc_prev_status
.flags
& CC_IN_80387
))
OUTPUT_JUMP ("jl %l0", "jb %l0", "js %l0");
output_203 (operands
, insn
)
if (TARGET_IEEE_FP
&& (cc_prev_status
.flags
& CC_IN_80387
))
OUTPUT_JUMP ("jge %l0", "jae %l0", "jns %l0");
output_207 (operands
, insn
)
if (TARGET_IEEE_FP
&& (cc_prev_status
.flags
& CC_IN_80387
))
OUTPUT_JUMP ("jle %l0", "jbe %l0", NULL_PTR
);
output_210 (operands
, insn
)
if (cc_prev_status
.flags
& CC_Z_IN_NOT_C
)
output_211 (operands
, insn
)
if (cc_prev_status
.flags
& CC_Z_IN_NOT_C
)
output_212 (operands
, insn
)
if (TARGET_IEEE_FP
&& (cc_prev_status
.flags
& CC_IN_80387
))
OUTPUT_JUMP ("jle %l0", "jbe %l0", NULL_PTR
);
output_214 (operands
, insn
)
if (TARGET_IEEE_FP
&& (cc_prev_status
.flags
& CC_IN_80387
))
OUTPUT_JUMP ("jge %l0", "jae %l0", "jns %l0");
output_216 (operands
, insn
)
if (TARGET_IEEE_FP
&& (cc_prev_status
.flags
& CC_IN_80387
))
OUTPUT_JUMP ("jl %l0", "jb %l0", "js %l0");
output_218 (operands
, insn
)
if (TARGET_IEEE_FP
&& (cc_prev_status
.flags
& CC_IN_80387
))
OUTPUT_JUMP ("jg %l0", "ja %l0", NULL_PTR
);
output_221 (operands
, insn
)
output_223 (operands
, insn
)
xops
[3] = pic_offset_table_rtx
;
output_asm_insn (AS2 (mov
%L2
,%3,%2), xops
);
output_asm_insn ("sub%L2 %l1@GOTOFF(%3,%0,4),%2", xops
);
output_asm_insn (AS1 (jmp
,%*%2), xops
);
ASM_OUTPUT_ALIGN_CODE (asm_out_file
);
output_224 (operands
, insn
)
output_226 (operands
, insn
)
if (GET_CODE (operands
[0]) == MEM
&& ! CONSTANT_ADDRESS_P (XEXP (operands
[0], 0)))
operands
[0] = XEXP (operands
[0], 0);
output_229 (operands
, insn
)
if (GET_CODE (operands
[0]) == MEM
&& ! CONSTANT_ADDRESS_P (XEXP (operands
[0], 0)))
operands
[0] = XEXP (operands
[0], 0);
output_232 (operands
, insn
)
if (GET_CODE (operands
[1]) == MEM
&& ! CONSTANT_ADDRESS_P (XEXP (operands
[1], 0)))
operands
[1] = XEXP (operands
[1], 0);
output_asm_insn (AS1 (call
,%*%1), operands
);
output_asm_insn (AS1 (call
,%P1
), operands
);
output_235 (operands
, insn
)
if (GET_CODE (operands
[1]) == MEM
&& ! CONSTANT_ADDRESS_P (XEXP (operands
[1], 0)))
operands
[1] = XEXP (operands
[1], 0);
output_asm_insn (AS1 (call
,%*%1), operands
);
output_asm_insn (AS1 (call
,%P1
), operands
);
output_238 (operands
, insn
)
if (GET_CODE (operands
[0]) == MEM
&& ! CONSTANT_ADDRESS_P (XEXP (operands
[0], 0)))
operands
[0] = XEXP (operands
[0], 0);
output_asm_insn (AS1 (call
,%*%0), operands
);
output_asm_insn (AS1 (call
,%P0
), operands
);
operands
[2] = gen_rtx (REG
, SImode
, 0);
output_asm_insn (AS2 (mov
%L2
,%2,%1), operands
);
operands
[2] = gen_rtx (REG
, SImode
, 1);
operands
[1] = adj_offsettable_operand (addr
, 4);
output_asm_insn (AS2 (mov
%L2
,%2,%1), operands
);
operands
[1] = adj_offsettable_operand (addr
, 8);
output_239 (operands
, insn
)
output_asm_insn (AS1 (call
,%P0
), operands
);
operands
[2] = gen_rtx (REG
, SImode
, 0);
output_asm_insn (AS2 (mov
%L2
,%2,%1), operands
);
operands
[2] = gen_rtx (REG
, SImode
, 1);
operands
[1] = adj_offsettable_operand (addr
, 4);
output_asm_insn (AS2 (mov
%L2
,%2,%1), operands
);
operands
[1] = adj_offsettable_operand (addr
, 8);
output_242 (operands
, insn
)
function_epilogue (asm_out_file
, get_frame_size ());
output_245 (operands
, insn
)
output_asm_insn ("cld", operands
);
if (GET_CODE (operands
[2]) == CONST_INT
)
if (INTVAL (operands
[2]) & ~0x03)
xops
[0] = GEN_INT ((INTVAL (operands
[2]) >> 2) & 0x3fffffff);
output_asm_insn (AS2 (mov
%L1
,%0,%1), xops
);
output_asm_insn ("rep movsd", xops
);
output_asm_insn ("rep\n\tmovsl", xops
);
if (INTVAL (operands
[2]) & 0x02)
output_asm_insn ("movsw", operands
);
if (INTVAL (operands
[2]) & 0x01)
output_asm_insn ("movsb", operands
);
output_247 (operands
, insn
)
label
= gen_label_rtx ();
output_asm_insn ("cld", operands
);
output_asm_insn (AS2 (xor%L0
,%0,%0), operands
);
output_asm_insn ("repz\n\tcmps%B2", operands
);
output_asm_insn ("je %l0", &label
);
xops
[1] = gen_rtx (MEM
, QImode
,
gen_rtx (PLUS
, SImode
, operands
[1], constm1_rtx
));
xops
[2] = gen_rtx (MEM
, QImode
,
gen_rtx (PLUS
, SImode
, operands
[2], constm1_rtx
));
output_asm_insn (AS2 (movz
%B1
%L0
,%1,%0), xops
);
output_asm_insn (AS2 (movz
%B2
%L3
,%2,%3), xops
);
output_asm_insn (AS2 (sub
%L0
,%3,%0), xops
);
ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (label
));
output_248 (operands
, insn
)
cc_status
.flags
|= CC_NOT_SIGNED
;
xops
[0] = gen_rtx (REG
, QImode
, 0);
xops
[1] = CONST0_RTX (QImode
);
output_asm_insn ("cld", operands
);
output_asm_insn (AS2 (test
%B0
,%1,%0), xops
);
return "repz\n\tcmps%B2";
output_250 (operands
, insn
)
output_asm_insn (AS2 (bsf
%L1
,%1,%0), operands
);
output_asm_insn (AS2 (cmp
%L1
,%0,%1), xops
);
output_asm_insn (AS2 (sbb
%L0
,%2,%2), operands
);
output_asm_insn (AS2 (or%L0
,%2,%0), operands
);
output_252 (operands
, insn
)
output_asm_insn (AS2 (bsf
%W1
,%1,%0), operands
);
output_asm_insn (AS2 (cmp
%W1
,%0,%1), xops
);
output_asm_insn (AS2 (sbb
%W0
,%2,%2), operands
);
output_asm_insn (AS2 (or%W0
,%2,%0), operands
);
output_253 (operands
, insn
)
return (char *) output_387_binary_op (insn
, operands
);
output_254 (operands
, insn
)
return (char *) output_387_binary_op (insn
, operands
);
output_255 (operands
, insn
)
return (char *) output_387_binary_op (insn
, operands
);
output_256 (operands
, insn
)
return (char *) output_387_binary_op (insn
, operands
);
output_257 (operands
, insn
)
return (char *) output_387_binary_op (insn
, operands
);
output_258 (operands
, insn
)
return (char *) output_387_binary_op (insn
, operands
);
output_259 (operands
, insn
)
return (char *) output_387_binary_op (insn
, operands
);
output_260 (operands
, insn
)
return (char *) output_387_binary_op (insn
, operands
);
output_262 (operands
, insn
)
output_asm_insn ("cld", operands
);
output_asm_insn (AS2 (mov
%L0
,%1,%0), xops
);
return "repnz\n\tscas%B2";
char * const insn_template
[] =
char *(*const insn_outfun
[])() =
rtx (*const insn_gen_function
[]) () =
gen_ashldi3_non_const_int
,
gen_ashrdi3_non_const_int
,
gen_lshrdi3_non_const_int
,
char **insn_name_ptr
= insn_name
;
const int insn_n_operands
[] =
const int insn_n_dups
[] =
char *const insn_operand_constraint
[][MAX_RECOG_OPERANDS
] =
{ "f,fm", "fm,f", "", "=a,a", },
{ "f", "rm", "", "=a", },
{ "rm", "f", "", "=a", },
{ "f", "fm", "", "=a", },
{ "fm", "f", "", "=a", },
{ "f,fm", "fm,f", "", "=a,a", },
{ "f", "rm", "", "=a", },
{ "rm", "f", "", "=a", },
{ "=q,*r,qm", "*g,q,qn", },
{ "=*rfm,*rf,f,!*rm", "*rf,*rfm,fG,fF", },
{ "=*rfm,*rf,f,!*rm", "*rf,*rfm,fG,fF", },
{ "=f,m", "0,f", "m,m", },
{ "", "", "", "", "", "", "", "", },
{ "", "", "", "", "", "", "", "", },
{ "", "", "", "", "", "", },
{ "", "", "", "", "", "", },
{ "=rm", "f", "m", "m", "=&q", },
{ "=rm", "f", "m", "m", "=&q", },
{ "=rm", "f", "m", "m", "=&q", },
{ "=rm", "f", "m", "m", "=&q", },
{ "=&r,ro", "%0,0", "o,riF", },
{ "=?r,rm,r", "%r,0,0", "ri,ri,rm", },
{ "=rm,r", "%0,0", "ri,rm", },
{ "=qm,q", "%0,0", "qn,qmn", },
{ "=&r,ro", "0,0", "o,riF", },
{ "=rm,r", "0,0", "ri,rm", },
{ "=rm,r", "0,0", "ri,rm", },
{ "=qm,q", "0,0", "qn,qmn", },
{ "=r,r", "%0,rm", "g,i", },
{ "=r,r", "%0,rm", "g,i", },
{ "=a", "0", "rm", "=&d", },
{ "=a", "0", "rm", "=&d", },
{ "=a", "0", "rm", "=&d", },
{ "=a", "0", "rm", "=&d", },
{ "=r,r,rm,r", "%rm,qm,0,0", "L,K,ri,rm", },
{ "=rm,r", "%0,0", "ri,rm", },
{ "=qm,q", "%0,0", "qn,qmn", },
{ "=rm,r", "%0,0", "ri,rm", },
{ "=rm,r", "%0,0", "ri,rm", },
{ "=qm,q", "%0,0", "qn,qmn", },
{ "=rm,r", "%0,0", "ri,rm", },
{ "=rm,r", "%0,0", "ri,rm", },
{ "=qm,q", "%0,0", "qn,qm", },
{ "=r,rm", "r,0", "M,cI", },
{ "+rm", "", "r", "n", },
{ "", "", "", "", "", "", "", },
{ "=rf", "m", "g", "", "i", },
{ "=rf", "", "g", "", "i", },
{ "D", "S", "n", "i", "=&c", },
{ "=&r", "S", "D", "c", "i", },
{ "=f,f", "0,fm", "fm,0", "", },
{ "=f", "rm", "0", "", },
{ "=f,f", "fm,0", "0,f", "", },
{ "=f", "0", "rm", "", },
{ "=f,f", "0,f", "fm,0", "", },
{ "=f,f", "0,fm", "fm,0", "", },
{ "=f", "rm", "0", "", },
{ "=f", "0", "rm", "", },
{ "=&c", "D", "a", "i", },
const enum machine_mode insn_operand_mode
[][MAX_RECOG_OPERANDS
] =
{ DFmode
, DFmode
, VOIDmode
, HImode
, },
{ DFmode
, SImode
, VOIDmode
, HImode
, },
{ SImode
, DFmode
, VOIDmode
, HImode
, },
{ DFmode
, SFmode
, VOIDmode
, HImode
, },
{ SFmode
, DFmode
, VOIDmode
, HImode
, },
{ DFmode
, DFmode
, HImode
, },
{ SFmode
, SFmode
, VOIDmode
, HImode
, },
{ SFmode
, SImode
, VOIDmode
, HImode
, },
{ SImode
, SFmode
, VOIDmode
, HImode
, },
{ SFmode
, SFmode
, HImode
, },
{ DFmode
, DFmode
, HImode
, },
{ DFmode
, DFmode
, HImode
, },
{ SFmode
, SFmode
, HImode
, },
{ SFmode
, SFmode
, HImode
, },
{ SFmode
, DFmode
, SFmode
, },
{ SImode
, DFmode
, VOIDmode
, VOIDmode
, VOIDmode
, VOIDmode
, VOIDmode
, SImode
, },
{ SImode
, SFmode
, VOIDmode
, VOIDmode
, VOIDmode
, VOIDmode
, VOIDmode
, SImode
, },
{ DImode
, DFmode
, VOIDmode
, VOIDmode
, VOIDmode
, SImode
, },
{ DImode
, SFmode
, VOIDmode
, VOIDmode
, VOIDmode
, SImode
, },
{ DImode
, DFmode
, SImode
, SImode
, SImode
, },
{ DImode
, SFmode
, SImode
, SImode
, SImode
, },
{ SImode
, DFmode
, VOIDmode
, VOIDmode
, SImode
, },
{ SImode
, SFmode
, VOIDmode
, VOIDmode
, SImode
, },
{ SImode
, DFmode
, SImode
, SImode
, SImode
, },
{ SImode
, SFmode
, SImode
, SImode
, SImode
, },
{ DImode
, DImode
, DImode
, },
{ SImode
, SImode
, SImode
, },
{ HImode
, HImode
, HImode
, },
{ QImode
, QImode
, QImode
, },
{ DFmode
, DFmode
, DFmode
, },
{ SFmode
, SFmode
, SFmode
, },
{ DImode
, DImode
, DImode
, },
{ SImode
, SImode
, SImode
, },
{ HImode
, HImode
, HImode
, },
{ QImode
, QImode
, QImode
, },
{ DFmode
, DFmode
, DFmode
, },
{ SFmode
, SFmode
, SFmode
, },
{ HImode
, HImode
, HImode
, },
{ HImode
, HImode
, HImode
, },
{ SImode
, SImode
, SImode
, },
{ SImode
, SImode
, SImode
, },
{ HImode
, QImode
, QImode
, },
{ DFmode
, DFmode
, DFmode
, },
{ SFmode
, SFmode
, SFmode
, },
{ QImode
, HImode
, QImode
, },
{ QImode
, HImode
, QImode
, },
{ DFmode
, DFmode
, DFmode
, },
{ SFmode
, SFmode
, SFmode
, },
{ SImode
, SImode
, SImode
, SImode
, },
{ HImode
, HImode
, HImode
, HImode
, },
{ SImode
, SImode
, SImode
, SImode
, },
{ HImode
, HImode
, HImode
, HImode
, },
{ SImode
, SImode
, SImode
, },
{ HImode
, HImode
, HImode
, },
{ QImode
, QImode
, QImode
, },
{ SImode
, SImode
, SImode
, },
{ HImode
, HImode
, HImode
, },
{ QImode
, QImode
, QImode
, },
{ SImode
, SImode
, SImode
, },
{ HImode
, HImode
, HImode
, },
{ QImode
, QImode
, QImode
, },
{ DImode
, DImode
, QImode
, },
{ DImode
, DImode
, QImode
, },
{ DImode
, DImode
, QImode
, },
{ SImode
, SImode
, SImode
, },
{ HImode
, HImode
, HImode
, },
{ QImode
, QImode
, QImode
, },
{ DImode
, DImode
, QImode
, },
{ DImode
, DImode
, QImode
, },
{ DImode
, DImode
, QImode
, },
{ SImode
, SImode
, SImode
, },
{ HImode
, HImode
, HImode
, },
{ QImode
, QImode
, QImode
, },
{ DImode
, DImode
, QImode
, },
{ DImode
, DImode
, QImode
, },
{ DImode
, DImode
, QImode
, },
{ SImode
, SImode
, SImode
, },
{ HImode
, HImode
, HImode
, },
{ QImode
, QImode
, QImode
, },
{ SImode
, SImode
, SImode
, },
{ HImode
, HImode
, HImode
, },
{ QImode
, QImode
, QImode
, },
{ SImode
, SImode
, SImode
, },
{ HImode
, HImode
, HImode
, },
{ QImode
, QImode
, QImode
, },
{ SImode
, VOIDmode
, SImode
, SImode
, },
{ SImode
, SImode
, SImode
, },
{ SImode
, SImode
, SImode
, },
{ SImode
, SImode
, SImode
, },
{ QImode
, SImode
, SImode
, },
{ SImode
, SImode
, SImode
, VOIDmode
, VOIDmode
, VOIDmode
, SImode
, },
{ SImode
, VOIDmode
, SImode
, },
{ QImode
, SImode
, VOIDmode
, SImode
, },
{ QImode
, SImode
, VOIDmode
, SImode
, },
{ SImode
, SImode
, VOIDmode
, SImode
, },
{ VOIDmode
, QImode
, SImode
, VOIDmode
, SImode
, },
{ VOIDmode
, QImode
, SImode
, VOIDmode
, SImode
, },
{ VOIDmode
, SImode
, SImode
, VOIDmode
, SImode
, },
{ VOIDmode
, QImode
, SImode
, },
{ VOIDmode
, QImode
, SImode
, },
{ VOIDmode
, SImode
, SImode
, },
{ QImode
, BLKmode
, VOIDmode
, },
{ QImode
, DImode
, VOIDmode
, },
{ SImode
, DImode
, VOIDmode
, },
{ BLKmode
, BLKmode
, SImode
, SImode
, SImode
, },
{ SImode
, SImode
, SImode
, SImode
, SImode
, },
{ SImode
, BLKmode
, BLKmode
, SImode
, SImode
, },
{ SImode
, SImode
, SImode
, SImode
, SImode
, },
{ SImode
, SImode
, SImode
, SImode
, },
{ SImode
, SImode
, SImode
, },
{ SImode
, SImode
, SImode
, },
{ HImode
, HImode
, HImode
, },
{ HImode
, HImode
, HImode
, },
{ DFmode
, DFmode
, DFmode
, DFmode
, },
{ DFmode
, SImode
, DFmode
, DFmode
, },
{ DFmode
, SFmode
, DFmode
, DFmode
, },
{ DFmode
, DFmode
, SImode
, DFmode
, },
{ DFmode
, DFmode
, SFmode
, DFmode
, },
{ SFmode
, SFmode
, SFmode
, SFmode
, },
{ SFmode
, SImode
, SFmode
, SFmode
, },
{ SFmode
, SFmode
, SImode
, SFmode
, },
{ SImode
, BLKmode
, QImode
, SImode
, },
{ SImode
, SImode
, QImode
, SImode
, },
const char insn_operand_strict_low
[][MAX_RECOG_OPERANDS
] =
{ 0, 0, 0, 0, 0, 0, 0, 0, },
{ 0, 0, 0, 0, 0, 0, 0, 0, },
{ 0, 0, 0, 0, 0, 0, 0, },
extern int nonimmediate_operand ();
extern int register_operand ();
extern int scratch_operand ();
extern int general_operand ();
extern int VOIDmode_compare_op ();
extern int push_operand ();
extern int memory_operand ();
extern int address_operand ();
extern int nonmemory_operand ();
extern int const_int_operand ();
extern int indirect_operand ();
extern int immediate_operand ();
extern int call_insn_operand ();
extern int symbolic_operand ();
extern int binary_387_op ();
int (*const insn_operand_predicate
[][MAX_RECOG_OPERANDS
])() =
{ nonimmediate_operand
, },
{ nonimmediate_operand
, },
{ nonimmediate_operand
, },
{ nonimmediate_operand
, },
{ nonimmediate_operand
, },
{ nonimmediate_operand
, },
{ register_operand
, scratch_operand
, },
{ register_operand
, scratch_operand
, },
{ register_operand
, scratch_operand
, },
{ register_operand
, scratch_operand
, },
{ nonimmediate_operand
, general_operand
, },
{ nonimmediate_operand
, general_operand
, },
{ nonimmediate_operand
, general_operand
, },
{ nonimmediate_operand
, general_operand
, },
{ nonimmediate_operand
, general_operand
, },
{ nonimmediate_operand
, general_operand
, },
{ nonimmediate_operand
, nonimmediate_operand
, VOIDmode_compare_op
, scratch_operand
, },
{ register_operand
, nonimmediate_operand
, VOIDmode_compare_op
, scratch_operand
, },
{ nonimmediate_operand
, register_operand
, VOIDmode_compare_op
, scratch_operand
, },
{ register_operand
, nonimmediate_operand
, VOIDmode_compare_op
, scratch_operand
, },
{ nonimmediate_operand
, register_operand
, VOIDmode_compare_op
, scratch_operand
, },
{ register_operand
, register_operand
, scratch_operand
, },
{ nonimmediate_operand
, nonimmediate_operand
, VOIDmode_compare_op
, scratch_operand
, },
{ register_operand
, nonimmediate_operand
, VOIDmode_compare_op
, scratch_operand
, },
{ nonimmediate_operand
, register_operand
, VOIDmode_compare_op
, scratch_operand
, },
{ register_operand
, register_operand
, scratch_operand
, },
{ register_operand
, nonimmediate_operand
, },
{ register_operand
, nonimmediate_operand
, },
{ register_operand
, register_operand
, scratch_operand
, },
{ register_operand
, register_operand
, scratch_operand
, },
{ register_operand
, register_operand
, scratch_operand
, },
{ register_operand
, register_operand
, scratch_operand
, },
{ general_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ push_operand
, general_operand
, },
{ push_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ push_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ push_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ push_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ push_operand
, general_operand
, },
{ register_operand
, register_operand
, },
{ general_operand
, general_operand
, },
{ push_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ general_operand
, nonimmediate_operand
, },
{ general_operand
, nonimmediate_operand
, },
{ general_operand
, nonimmediate_operand
, },
{ register_operand
, register_operand
, },
{ register_operand
, register_operand
, },
{ general_operand
, nonimmediate_operand
, },
{ general_operand
, nonimmediate_operand
, },
{ general_operand
, nonimmediate_operand
, },
{ general_operand
, general_operand
, },
{ nonimmediate_operand
, register_operand
, },
{ nonimmediate_operand
, register_operand
, memory_operand
, },
{ general_operand
, register_operand
, 0, 0, 0, 0, 0, scratch_operand
, },
{ general_operand
, register_operand
, 0, 0, 0, 0, 0, scratch_operand
, },
{ general_operand
, register_operand
, 0, 0, 0, scratch_operand
, },
{ general_operand
, register_operand
, 0, 0, 0, scratch_operand
, },
{ general_operand
, register_operand
, memory_operand
, memory_operand
, scratch_operand
, },
{ general_operand
, register_operand
, memory_operand
, memory_operand
, scratch_operand
, },
{ general_operand
, register_operand
, 0, 0, scratch_operand
, },
{ general_operand
, register_operand
, 0, 0, scratch_operand
, },
{ general_operand
, register_operand
, memory_operand
, memory_operand
, scratch_operand
, },
{ general_operand
, register_operand
, memory_operand
, memory_operand
, scratch_operand
, },
{ register_operand
, nonimmediate_operand
, },
{ register_operand
, nonimmediate_operand
, },
{ register_operand
, nonimmediate_operand
, },
{ register_operand
, nonimmediate_operand
, },
{ register_operand
, nonimmediate_operand
, },
{ register_operand
, nonimmediate_operand
, },
{ register_operand
, nonimmediate_operand
, },
{ register_operand
, nonimmediate_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ register_operand
, address_operand
, },
{ register_operand
, nonimmediate_operand
, nonimmediate_operand
, },
{ register_operand
, nonimmediate_operand
, nonimmediate_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ register_operand
, nonimmediate_operand
, nonimmediate_operand
, },
{ register_operand
, nonimmediate_operand
, nonimmediate_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, nonimmediate_operand
, nonimmediate_operand
, },
{ register_operand
, nonimmediate_operand
, nonimmediate_operand
, },
{ register_operand
, nonimmediate_operand
, nonimmediate_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ register_operand
, nonimmediate_operand
, nonimmediate_operand
, },
{ register_operand
, nonimmediate_operand
, nonimmediate_operand
, },
{ register_operand
, register_operand
, general_operand
, register_operand
, },
{ register_operand
, register_operand
, general_operand
, register_operand
, },
{ register_operand
, register_operand
, general_operand
, register_operand
, },
{ register_operand
, register_operand
, general_operand
, register_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ register_operand
, general_operand
, },
{ register_operand
, general_operand
, },
{ register_operand
, general_operand
, },
{ register_operand
, general_operand
, },
{ register_operand
, general_operand
, },
{ register_operand
, general_operand
, },
{ register_operand
, general_operand
, },
{ register_operand
, general_operand
, },
{ register_operand
, general_operand
, },
{ register_operand
, register_operand
, },
{ register_operand
, register_operand
, },
{ register_operand
, register_operand
, },
{ register_operand
, register_operand
, },
{ register_operand
, register_operand
, },
{ register_operand
, register_operand
, },
{ general_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ general_operand
, general_operand
, },
{ register_operand
, register_operand
, nonmemory_operand
, },
{ register_operand
, register_operand
, const_int_operand
, },
{ register_operand
, register_operand
, register_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ register_operand
, register_operand
, nonmemory_operand
, },
{ register_operand
, register_operand
, const_int_operand
, },
{ register_operand
, register_operand
, register_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ register_operand
, register_operand
, nonmemory_operand
, },
{ register_operand
, register_operand
, const_int_operand
, },
{ register_operand
, register_operand
, register_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ general_operand
, general_operand
, nonmemory_operand
, },
{ general_operand
, 0, general_operand
, const_int_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ general_operand
, general_operand
, general_operand
, },
{ register_operand
, general_operand
, },
{ register_operand
, const_int_operand
, const_int_operand
, },
{ general_operand
, const_int_operand
, const_int_operand
, },
{ general_operand
, general_operand
, general_operand
, 0, 0, 0, scratch_operand
, },
{ register_operand
, 0, scratch_operand
, },
{ indirect_operand
, general_operand
, 0, immediate_operand
, },
{ call_insn_operand
, general_operand
, 0, immediate_operand
, },
{ symbolic_operand
, general_operand
, 0, immediate_operand
, },
{ indirect_operand
, general_operand
, },
{ call_insn_operand
, general_operand
, },
{ symbolic_operand
, general_operand
, },
{ 0, indirect_operand
, general_operand
, 0, immediate_operand
, },
{ 0, call_insn_operand
, general_operand
, 0, immediate_operand
, },
{ 0, symbolic_operand
, general_operand
, 0, immediate_operand
, },
{ 0, indirect_operand
, general_operand
, },
{ 0, call_insn_operand
, general_operand
, },
{ 0, symbolic_operand
, general_operand
, },
{ indirect_operand
, memory_operand
, 0, },
{ call_insn_operand
, memory_operand
, 0, },
{ symbolic_operand
, memory_operand
, 0, },
{ memory_operand
, memory_operand
, const_int_operand
, const_int_operand
, scratch_operand
, },
{ address_operand
, address_operand
, const_int_operand
, immediate_operand
, scratch_operand
, },
{ general_operand
, general_operand
, general_operand
, general_operand
, immediate_operand
, },
{ general_operand
, address_operand
, address_operand
, register_operand
, immediate_operand
, },
{ address_operand
, address_operand
, register_operand
, immediate_operand
, },
{ general_operand
, general_operand
, scratch_operand
, },
{ register_operand
, general_operand
, scratch_operand
, },
{ general_operand
, general_operand
, scratch_operand
, },
{ register_operand
, general_operand
, scratch_operand
, },
{ register_operand
, nonimmediate_operand
, nonimmediate_operand
, binary_387_op
, },
{ register_operand
, general_operand
, general_operand
, binary_387_op
, },
{ register_operand
, general_operand
, general_operand
, binary_387_op
, },
{ register_operand
, general_operand
, general_operand
, binary_387_op
, },
{ register_operand
, general_operand
, general_operand
, binary_387_op
, },
{ register_operand
, nonimmediate_operand
, nonimmediate_operand
, binary_387_op
, },
{ register_operand
, general_operand
, general_operand
, binary_387_op
, },
{ register_operand
, general_operand
, general_operand
, binary_387_op
, },
{ register_operand
, general_operand
, register_operand
, immediate_operand
, },
{ register_operand
, address_operand
, register_operand
, immediate_operand
, },
const int insn_n_alternatives
[] =