int hscs1
; /* Control and Status register 1 */
int hswc
; /* Word count register */
int hsba
; /* UNIBUS address register */
int hsda
; /* Desired address register */
int hscs2
; /* Control and Status register 2 */
int hsds
; /* Drive Status */
int hser
; /* Error register */
int hsbae
; /* 11/70 bus extension */
#define ERR 040000 /* hscs1 - composite error */
#define DRY 0200 /* hsds - Drive Ready */
mblks
= 1024; /* RJS03 */
if(bp
->b_dev
.d_minor
>= 8)
mblks
= 2048; /* RJS04 */
if(bp
->b_blkno
>= mblks
) {
hstab
.d_actl
->av_forw
= bp
;
if ((bp
= hstab
.d_actf
) == 0)
if(bp
->b_dev
.d_minor
< 8)
HSADDR
->hscs2
= bp
->b_dev
.d_minor
& 07;
rhstart(bp
, &HSADDR
->hsda
, addr
<<1, &HSADDR
->hsbae
);
if(HSADDR
->hscs1
& ERR
){ /* error bit */
deverror(bp
, HSADDR
->hscs2
, 0);
if (++hstab
.d_errcnt
<= 10) {
hstab
.d_actf
= bp
->av_forw
;
physio(hsstrategy
, &rhsbuf
, dev
, B_READ
);
physio(hsstrategy
, &rhsbuf
, dev
, B_WRITE
);